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| PIC32MX Family Data Sheet 64/100-Pin General Purpose, 32-Bit Flash Microcontrollers (c) 2007 Microchip Technology Inc. Advance Information DS61143A Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61143A-page ii Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 64/100-Pin General Purpose, 32-Bit Flash Microcontrollers High-Performance RISC CPU: * M4KTM 32-Bit Core with 5-Stage Pipeline * Single-Cycle Multiply and High-Performance Divide Unit * MIPS16eTM Mode for Up to 40% Smaller Code Size * User and Kernel Modes to Enable Robust Embedded System * Two 32-Bit Core Register Files to Reduce Interrupt Latency * Prefetch Cache Module to Speed Execution from Flash MIPS32(R) Analog Features: * Up to 16-Channel 10-Bit Analog-to-Digital Converter: - 400 ksps conversion rate - Conversion available during Sleep, Idle * Two Analog Comparators Peripheral Features: * Atomic SET, CLEAR and INVERT Operation on Select Peripheral Registers * Up to 4-Channel Hardware DMA Controller with Automatic Data Size Detection * Two I2CTM Modules * Two UART Modules with: - RS-232, RS-485 and LIN 1.2 support - IrDA(R) with on-chip hardware encoder and decoder * Parallel Master and Slave Port (PMP/PSP) with 8-Bit and 16-Bit Data and Up to 16 Address Lines * Hardware Real-Time Clock/Calendar (RTCC) * Five 16-Bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) * Five Capture Inputs * Five Compare/PWM Outputs * Five External Interrupt pins * 5V Tolerant Input Pins * 8 mA Sink/Source on Select I/O Pins * Configurable Open-Drain Output on Digital I/O Pins Special Microcontroller Features: * * * * * * * * * Operating Voltage Range of 2.5V to 3.6V 32-512K Flash and 8-32K Data Memory Additional 12 KB of Boot Flash Memory Pin-Compatible with most PIC24/dsPIC(R) Devices Multiple Power Management Modes Multiple Interrupt Vectors with Individually Programmable Priority Fail-Safe Clock Monitor Mode Configurable Watchdog Timer with On-Chip, Low-Power RC Oscillator for Reliable Operation Two Programming and Debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS standard enhanced JTAG interface Unintrusive Hardware-Based Instruction Trace IEEE Std 1149.2 Compatible (JTAG) Boundary Scan * * General Purpose Program/ Data Memory (KB) 32/8 64/16 128/16 256/32 128/16 256/32 512/32 Comparators DMA Channels Timers/ Capture/ Compare 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 EUART/ SPI/ I2CTM 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 PMP/PSP Yes Yes Yes Yes Yes Yes Yes Prefetch Cache VREG Trace Device Pins 10-Bit A/D (ch) PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F256H PIC32MX320F128L PIC32MX360F256L PIC32MX360F512L 64 64 64 64 100 100 100 0 0 0 4 0 4 4 Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes No No No No No Yes Yes 16 16 16 16 16 16 16 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 1 JTAG PIC32MX FAMILY Pin Diagram (64-Pin General Purpose) 64-Pin TQFP (General Purpose) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/VREF-/AN1/CN3/RB1 PGD1/PMA6/VREF+/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PIC32MX3XXH PGC2/AN6/OCFA/RB6 PGD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 DS61143A-page 2 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY Pin Diagram (100-Pin General Purpose) 100-Pin TQFP (General Purpose) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD0/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE CN16/PMD15/RD7 CN15/PMD14/RD6 CN14/PMRD/RD5 OC5/CN13/PMWR/RD4 CN19/PMD13/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/AN1/CN3/RB1 PGD1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX3XXL 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 (c) 2007 Microchip Technology Inc. PGC2/AN6/OCFA/RB6 PGD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 VSS VDD CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Advance Information DS61143A-page 3 PIC32MX FAMILY Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 Device Overview .......................................................................................................................................................................... 7 PIC32MX MCU ........................................................................................................................................................................... 19 Instruction Set ............................................................................................................................................................................ 33 Prefetch ...................................................................................................................................................................................... 39 Direct Memory Access (DMA) Controller ................................................................................................................................. 59 Memory Organization ............................................................................................................................................................... 105 Flash Program Memory ............................................................................................................................................................ 127 Resets ...................................................................................................................................................................................... 137 Interrupts .................................................................................................................................................................................. 147 Oscillators................................................................................................................................................................................. 201 Power Saving .......................................................................................................................................................................... 227 I/O Ports ................................................................................................................................................................................... 243 Timer1 ...................................................................................................................................................................................... 265 Timers 2,3,4,5 .......................................................................................................................................................................... 277 Input Capture............................................................................................................................................................................ 293 Output Compare ....................................................................................................................................................................... 301 Serial Peripheral Interface (SPI)............................................................................................................................................... 317 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 343 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 357 Parallel master port ................................................................................................................................................................. 371 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 399 Analog-Digital Converter .......................................................................................................................................................... 419 Comparator .............................................................................................................................................................................. 447 Comparator Reference ............................................................................................................................................................. 459 Special Features ...................................................................................................................................................................... 465 Watchdog Timer ....................................................................................................................................................................... 477 Programming and diagnostics .................................................................................................................................................. 487 Development Support............................................................................................................................................................... 499 Electrical Characteristics .......................................................................................................................................................... 503 Packaging Information.............................................................................................................................................................. 535 DS61143A-page 4 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 5 PIC32MX FAMILY NOTES: DS61143A-page 6 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 64/100-Pin General Purpose, 32-Bit Flash Microcontrollers 1.0 DEVICE OVERVIEW 1.3 Power-Saving Technology This document contains device specific information for the following devices: * * * * * * * PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX320F128L PIC32MX340F256H PIC32MX360F256L PIC32MX360F512L All of the devices in the PIC32MX Family incorporate a range of features that can significantly reduce power consumption during operation. Key features include: * On-the-Fly Clock Switching: The device clock can be changed under software control to any of the four clock sources during operation. * Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. This family introduces a new line of Microchip devices: a 32-bit RISC microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC32MX Family offers a new migration option for those high-performance applications which may be outgrowing their 16-bit platforms. 1.4 Communications 1.1 Easy Migration The PIC32MX Family was designed to provide an easy migration path as the application needs change. The consistent pinout scheme used throughout the entire family aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 100-pin devices. The PIC32MX Family is pin compatible with Microchip PIC24FJ128GA010 devices. The PIC32MX Family incorporates a range of serial communication peripherals to handle a range of application requirements. All devices are equipped with two independent UARTs with built-in IrDA encoder/decoders. There are also two independent SPI modules, and two independent I2C modules that support both Master and Slave modes of operation. 1.5 10-Bit A/D Converter The A/D Converter features 400+ ksps maximum sample rate. This configurable module incorporates a userselectable scan list and auto-convert functions to allow acquisitions without processor intervention. Multiple A/D trigger sources are user-selectable: timer event, external pin, manual and auto-convert. 1.2 1.2.1 Core Features 32-BIT RISC ARCHITECTURE 1.6 External Interface Central to all PIC32MX Family devices is the 32-bit MIPS32 M4K CPU core, offering a wide range of features, such as: Up to 1.5 DMIPS/MHz 32-bit Address and Data paths 32-bit Linear (program space) addressing (2) thirty-two element 32-bit core register files Single-cycle multiply and high-performance divide unit for 32-bit integer math * 16 and 32-bit instructions, optimized for high-level languages, such as `C' * * * * * A Parallel Master Port Parallel Slave Port enables 8/16bit parallel data communications in Master mode with up to 16 address lines; 8-bit Slave modes are also supported. 1.7 Real-Time Clock/Calendar This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 7 PIC32MX FAMILY 1.8 Oscillator Options and Features All of the devices in the PIC32MX Family offer four different oscillator options, allowing users a range of choices in developing application hardware. These include: * A Primary Oscillator (POSC) with two External Crystal modes using crystals or ceramic resonators. * Two External Clock modes with selectable peripheral bus clock output. * A Fast Internal Oscillator (FRC) with a nominal 8 MHz output. * On-board postscalers and/or PLL to provide clock speeds ranging from 31 kHz to maximum specified frequency. * A Secondary Oscillator (SOSC) designed to operate with an external 32.768 kHz crystal. This oscillator can also be used with Timer1 and the integrated RTCC. * An Internal Low-Power RC oscillator (LPRC) having a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The oscillator block also provides a stable reference source for the user-controlled Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. DS61143A-page 8 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 1.9 Device Features, Block Diagrams and Pinout Tables DEVICE FEATURES FOR THE PIC32MX3XXFXXX GENERAL PURPOSE FAMILY PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F256H PIC32MX320F128L PIC32MX360F256L PIC32MX360F512L 512K 32K 4 Yes 6 Instruction, 2 Data 16 2 Yes POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit Mismatch) (PWRT, OST, PLL Lock) MIPS32(R) Enhanced Architecture (Release 2) MIPS16eTM Code Compression Packages 64-pin TQFP 100-pin TQFP TABLE 1-1: Features Operating Frequency Program Memory (Bytes) Data Memory (Bytes) Interrupt Sources/Vectors I/O Ports Total I/O Pins DMA Channels Timers: Total number (16-bit) 32-bit (paired 16-bit) 32-bit core timer Input Capture Channels Output Compare/PWM Channels Input Change Interrupt Notification Serial Communications: Enhanced UART SPI (3-wire/4-wire) I 2CTM DC - 20 MHz 32K 8K 64K 16K 128K 16K DC - 72 MHz 256K 32K 95 / 63 Ports B, C, D, E, F, G 53 0 5 2 1 5 5 19 22 4 0 Ports A, B, C, D, E, F, G 85 128K 16K 256K 32K 2 2 2 Yes Yes Yes Yes No Parallel Communications (PMP/PSP) JTAG Boundary Scan JTAG Debug and Program ICSPTM 2-Wire Debug and Program Instruction Trace Hardware Break Points 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Internal LDO Resets (and delays) Instruction Support (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 9 PIC32MX FAMILY FIGURE 1-1: PIC32MX FAMILY BLOCK DIAGRAM (GENERAL PURPOSE) OSC2/CLKO OSC1/CLKI VDDCORE/VCAP OSC/SOSC Oscillators FRC/LPRC Oscillators PLL DIVIDERS Precision Band Gap Reference SYSCLK PBCLK ENVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(3) VDD, VSS MCLR Timing Generation Peripheral Bus Clocked by SYSCLK CN1-22(1) PORTA(1,4) JTAG BSCAN Interrupt Controller PWM OC1-5 DMAC(2) ICD 32 MIPS32(R) M4KTM CPU Core PORTC(1) IS 32 PORTD(1) 32 DS 32 32 Bus Matrix 32 PORTE(1) Prefetch Module(2) Data RAM Peripheral Bus Clocked by PBCLK PORTB EJTAG INT IC1-5 32 SPI1,2(1) I2C1,2 32 32 32 Peripheral Bridge PMP(1) PORTF(1) 128 128-Bit Wide Program Flash Memory Flash Controller UART1,2 PORTG(1) Comparators Peripheral Bus Clocked by PBCLK Timer1 Timer2 Timer3 Timer4 Timer5 RTCC 10-Bit ADC Note 1: 2: 3: 4: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. Some features are not available on certain devices. BOR functionality is provided when the on-board voltage regulator is enabled. PORTA is not present on 64-pin devices DS61143A-page 10 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 1-2: Function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE Pin Number 64-pin 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 19 20 35 29 12 11 21 14 13 22 39 40 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 100-pin 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 30 31 48 39 21 20 32 23 22 33 63 64 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 I/O I I I I I I I I I I I I I I I I P P O O I I O I I O I O I I I I I I I I I I I I I I I I I I Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA -- -- -- -- ANA ANA -- ANA ANA -- ANA -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Positive Supply for Analog Modules. Ground Reference for Analog Modules. UART1 IrDA(R) Baud Clock. UART2 IrDA Baud Clock. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. A/D Analog Inputs. Description TTL = TTL input buffer ANA = Analog level input/output (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 11 PIC32MX FAMILY TABLE 1-2: Function CN18 CN19 CN20 CN21 CVREF ENVREG IC1 IC2 IC3 IC4 IC5 INT0 INT1 INT2 INT3 INT4 MCLR OC1 OC2 OC3 OC4 OC5 OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 PMA0/ PMALL PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin 32 -- -- -- 23 57 42 43 44 45 52 35 42 43 44 45 7 46 49 50 51 52 17 30 39 40 15 16 17 18 30 100-pin 50 80 47 48 34 86 68 69 70 71 79 55 18 19 66 67 13 72 76 77 78 81 26 44 63 64 24 25 26 27 44 I/O I I I I O I I I I I I I I I I I I O O O O O I I I O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ANA ST ST ST ST ST ST ST ST ST ST ST ST -- -- -- -- -- ST ST ANA ANA ST ST ST ST ST Output Compare Fault A Input. Output Compare Fault B Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger and ICSPTM Programming Clock In-Circuit Debugger and ICSP Programming Data. In-Circuit Debugger and ICSPTM Programming Clock. In-Circuit Debugger and ICSP Programming Data. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Master Clear (Device Reset) Input. Bring this line low to cause a Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. Enable for On-Chip Voltage Regulator. Input Capture Inputs. Interrupt-on-Change Inputs. Description PMA1/ PMALH 29 43 I/O ST Legend: TTL = TTL input buffer ANA = Analog level input/output DS61143A-page 12 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 1-2: Function PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1/ PMA14 PMCS2/ PMA15 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD/ PMRD/PMWR PMWR/ PMENB Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin 8 6 5 4 16 22 32 31 28 27 24 23 45 44 60 61 62 63 64 1 2 3 -- -- -- -- -- -- -- -- 53 52 100-pin 14 12 11 10 29 28 50 49 42 41 35 34 71 70 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 82 81 I/O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O Input Buffer -- -- -- -- -- -- -- -- -- -- -- -- -- -- ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL -- -- Parallel Master Port Read Strobe (Master Mode 2) Parallel Master Port Read/Write Strobe (Master Mode 1). Parallel Master Port Write Strobe (Master Mode 2) Parallel Master Port Enable Strobe (Master Mode 1). ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Parallel Master Port Chip Select 1 Strobe/Address bit 14. Parallel Master Port Chip Select 2 Strobe/Address bit 15. Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). Description Parallel Master Port Address (Demultiplexed Master modes). TTL = TTL input buffer ANA = Analog level input/output (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 13 PIC32MX FAMILY TABLE 1-2: Function RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 100-pin 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description TTL = TTL input buffer ANA = Analog level input/output DS61143A-page 14 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 1-2: Function RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF12 RF13 Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 58 59 34 33 31 32 35 -- -- -- -- 100-pin 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 55 54 53 40 39 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description TTL = TTL input buffer ANA = Analog level input/output (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 15 PIC32MX FAMILY TABLE 1-2: Function RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO SS1 SS2 T1CK T2CK T3CK T4CK T5CK TCK TDI TDO TMS TRCLK TRD0 TRD1 TRD2 TRD3 Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin -- -- 37 36 4 5 6 8 -- -- -- -- 42 35 4 37 32 36 31 34 5 33 6 47 48 14 8 48 -- -- -- -- 27 28 24 23 -- -- -- -- -- 100-pin 90 89 57 56 10 11 12 14 96 97 95 1 68 55 10 57 58 56 59 54 11 53 12 73 74 23 14 74 6 7 8 9 38 60 61 17 91 97 96 95 92 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I I O O I O I/O I/O I I I I I I I O I O O O O O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST -- -- ST I2C I2C I2C IC ST ST -- -- ANA ANA ST ST ST ST ST ST ST ST ST -- ST -- -- -- -- -- 2 Description PORTG Digital I/O. Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. Trace Clock. Trace Data Bit 0. Trace Data Bit 1. Trace Data Bit 2. Trace Data Bit 3. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer TTL = TTL input buffer ANA = Analog level input/output DS61143A-page 16 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 1-2: Function U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDD VDDCAP VDDCORE VREFVREF+ VSS Legend: PIC32MX FAMILY PINOUT DESCRIPTIONS - GENERAL PURPOSE (CONTINUED) Pin Number 64-pin 43 35 34 33 21 29 31 32 100-pin 47 48 52 51 40 39 49 50 I/O I O I O I O I O P P P I I P Input Buffer ST -- ST DIG ST -- ST -- -- -- -- ANA ANA -- UART1 Clear to Send Input. UART1 Request to Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear to Send Input. UART2 Request to Send Output. UART 2 Receive Input. UART2 Transmit Output. Positive Supply for Peripheral Digital Logic and I/O pins. External Filter Capacitor Connection (regulator enabled). Positive Supply for Microcontroller Core Logic (regulator disabled). A/D and Comparator Reference Voltage (Low) Input. A/D and Comparator Reference Voltage (High) Input. Ground Reference for Logic and I/O pins. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Description 10, 26, 38 2, 16, 37, 46, 62 56 56 15 16 9, 25, 41 85 85 28 29 15, 36, 45, 65, 75 TTL = TTL input buffer ANA = Analog level input/output (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 17 PIC32MX FAMILY NOTES: DS61143A-page 18 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 2.0 Note: PIC32MX MCU This data sheet summarizes the features of the PIC32MX of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The MCU module is the heart of the PIC32MX processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction, and writes the results of instruction execution to the proper destinations. 2.1 Features * 5-stage pipeline * 32-bit Address and Data Paths * MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract Instructions - Targeted Multiply Instruction - Zero/One Detect Instructions - Wait Instruction - Conditional Move Instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions * MIPS16eTM Code Compression - 16 bit encodings of 32 bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16 bit data types * Simple Fixed Mapping Translation (FMT) mechanism * Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency * Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign extension-dependent) * Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks * EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value breakpoints - PC tracing w/ trace compression (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 19 PIC32MX 2.2 Architecture Overview The PIC32MX core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. The blocks included with the PIC32MX core are as follows: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Fixed Mapping Translation (FMT) * Dual Internal Bus interfaces * Power Management * MIPS16e support * Enhanced JTAG (EJTAG) Controller FIGURE 2-1: MCU BLOCK DIAGRAM EJTAG MDU Trace TAP Trace I/F Off-Chip Debug I/F FMT Bus Interface Dual Bus I/F System Coprocessor Power Mgmt DS61143-page 20 Advance Information (c) 2007 Microchip Technology Inc. Bus Matrix Execution Core (RF/ALU/Shift) PIC32MX 2.2.1 EXECUTION UNIT 2.2.2 MULTIPLY/DIVIDE UNIT (MDU) The PIC32MX core execution unit implements a load/ store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The PIC32MX core contains thirtytwo 32-bit general-purpose registers used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter & Store Aligner The PIC32MX core includes a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/ or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16bit-wide rs, 15 iterations are skipped, and for a 24-bitwide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 2-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 21 PIC32MX TABLE 2-1: PIC32MX CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the general-purpose register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32 DS61143-page 22 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 2.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (kernel, user, and debug), and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 2-2. TABLE 2-2: COPROCESSOR 0 REGISTERS Function Reserved in the PIC32MX core Enables access via the RDHWR instruction to selected hardware registers Reports the address for the most recent address-related exception Processor cycle count Reserved in the PIC32MX core Timer interrupt control Processor status and control Interrupt system status and control Shadow register set status and control Provides mapping from vectored interrupt to a shadow set Cause of last general exception Program counter at last exception Processor identification and revision Exception vector base register Configuration register Configuration register 1 Configuration register 2 Configuration register 3 Reserved in the PIC32MX core Debug control and exception status Program counter at last debug exception. Reserved in the PIC32MX core. Program counter at last error. Debug handler scratchpad register. (1) Register Register Number Name 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2: Reserved HWREna BadVAddr(1) Count(1) Reserved Compare Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC (1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug (2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Registers used in exception processing. Registers used during debug. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 23 PIC32MX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events, or program errors. Table 2-3 shows the exception types in order of priority. TABLE 2-3: Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL / DDBS AdEL AdES DBE DDBL PIC32MX CORE EXCEPTION TYPES Description Assertion MCLR or a Power-On Reset (POR) EJTAG Debug Single Step. EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG Breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a Reserved Instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. DS61143-page 24 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 2.2.4 INTERRUPT HANDLING 2.2.5 GPR SHADOW REGISTERS The PIC32MX core includes support for peripheral interrupts, two software interrupts, and a timer interrupt. The PIC32MX MCU uses the MIPS External Interrupt Controller (EIC) mode, which redefines the way in which interrupts are handled to provide full support for an external interrupt controller handling prioritization and vectoring of interrupts. This presence of this mode denoted by the VEIC bit in the Config3 register. On the PIC32MX core, the VEIC bit is always set to 1 to indicate the presence of an external interrupt controller. Note: Although EIC mode is designated as "External", the interrupt controller is onchip. Release 2 of the MIPS32 Architecture optionally removes the need to save and restore GPRs on entry to high priority interrupts or exceptions, and to provide specified processor modes with the same capability. This is done by introducing multiple copies of the GPRs, called shadow sets, and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception. The normal GPRs are logically considered shadow set zero. The PIC32MX core implements two sets of registers, the normal GPRs, and one shadow set. This is indicated by the SRSCtlHSS field. The interrupt controller specifies which shadow set should be used upon entry to a particular vector. The shadow registers further improve interrupt latency by avoiding the need to save context when invoking an interrupt handler. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 25 PIC32MX 2.3 Modes of Operation The PIC32MX core supports three modes of operation: user mode, kernel mode, and debug mode. User mode is most often used for applications programs. Kernel mode is typically used for handling exceptions and operating system kernel functions, including CP0 management and I/O device accesses. An additional Debug mode is used during system bring-up and software development. Refer to the EJTAG specification for more information on debug mode. FIGURE 2-2: PIC32MX CORE VIRTUAL ADDRESS MAP 0xFFFFFFFF Fixed Mapped 0xFF400000 0xFF3FFFFF 0xFF200000 0xF1FFFFFF 0xE0000000 0xDFFFFFFF Memory/EJTAG(1) Fixed Mapped Kernel Virtual Address Space Fixed Mapped, 512 MB Kernel Virtual Address Space Unmapped, 512 MB Uncached Kernel Virtual Address Space Unmapped, 512 MB kseg3 kseg2 0xC0000000 0xBFFFFFFF kseg1 0xA0000000 0x9FFFFFFF kseg0 0x80000000 0x7FFFFFFF User Virtual Address Space Fixed Mapped, 2048 MB kuseg 0x00000000 Note 1: This space is mapped to memory in user or kernel mode, and by the EJTAG module in Debug mode. DS61143-page 26 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 2.3.1 FIXED MAPPING TRANSLATION The PIC32MX core provides a simple Fixed Mapping Translation (FMT) mechanism that is smaller and simpler than a full Translation Lookaside Buffer (TLB) found in other MIPS cores. Like a TLB, the FMT performs virtual-to-physical address translation and provides attributes for the different segments. Those segments that are unmapped in a TLB implementation (kseg0 and kseg1) are translated identically by the FMT. Figure 2-3 shows how the FMT is implemented in the PIC32MX core. FIGURE 2-3: ADDRESS TRANSLATION DURING MEMORY ACCESS Virtual Address Physical Address Instruction Address Calculator Instn SRAM FMT SRAM Interface Data SRAM Virtual Address Physical Address Data Address Calculator In general, the FMT also determines the cacheability of each segment. These attributes are controlled via bits in the Config register. Table 2-4 shows the encoding for the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0) fields of the Config register. The PIC32MX core passes these Config fields to the Prefetch Cache module to determine cacheability of Program Memory Flash accesses. Table 2-5 shows how the cacheability of the virtual address segments is controlled by these fields. TABLE 2-4: CACHE COHERENCY ATTRIBUTES Cache Coherency Attribute Uncached. Cacheable Config Register Fields K23, KU, and K0 2 3 (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 27 PIC32MX In the PIC32MX core, no translation exceptions are taken, although address errors are still possible. TABLE 2-5: Segment useg/kuseg CACHEABILITY OF SEGMENTS WITH FIXED MAPPING TRANSLATION Virtual Address Range 0x0000_0000-0x7FFF_FFFF Cacheability Controlled by the KU field (bits 27:25) of the Config register. See Figure 2-4 for mapping. This segment is always uncached when ERL = 1. Controlled by the K0 field (bits 2:0) of the Config register. See Figure 2-4 for mapping. Always uncacheable. Controlled by the K23 field (bits 30:28) of the Config register. See Figure 2-4 for mapping. Controlled by the K23 field (bits 30:28) of the Config register. See Figure 2-4 for mapping. kseg0 kseg1 kseg2 kseg3 0x8000_0000- 0x9FFF_FFFF 0xA000_0000-0xBFFF_FFFF 0xC000_0000-0xDFFF_FFFF 0xE000_0000-0xFFFF_FFFF The FMT performs a simple translation to map from virtual addresses to physical addresses. This mapping is shown in Figure 2-4. FIGURE 2-4: FMT MEMORY MAP (ERL = 0) IN THE PIC32MX CORE Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000 useg/kuseg useg/kuseg 0x4000_0000 reserved 0x2000_0000 0x0000_0000 kseg0/kseg1 0x0000_0000 DS61143-page 28 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX When ERL = 1, useg and kuseg become unmapped (virtual address is identical to the physical address) and uncached. This behavior is the same as if there was a TLB. This mapping is shown in Figure 2-5. FIGURE 2-5: PIC32MX CORE FMT MEMORY MAP (ERL = 1) Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000 reserved 0x8000_0000 useg/kuseg useg/kuseg 0x0000_0000 kseg0/kseg1 0x0000_0000 2.3.2 DUAL INTERNAL BUS INTERFACES 2.3.3 MIPS16E EXECUTION The SRAM interface includes dual instruction and data interfaces. The dual interface enables independent connection to instruction and data devices. It yields the highest performance, since the pipeline can generate simultaneous I and D requests which are then serviced in parallel. The internal buses are connected to the Bus Matrix unit, which is a switch fabric that provides this parallel operation. When the core is operating in MIPS16e mode, instruction fetches only require 16-bits of data to be returned. For improved efficiency, however, the core will fetch 32-bits of instruction data whenever the address is word-aligned. Thus for sequential MIPS16e code, fetches only occur for every other instruction, resulting in better performance and reduced system power. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 29 PIC32MX 2.4 Power Management 2.5.1 DEBUG REGISTERS The PIC32MX core offers a number of power management features, including low-power design, active power management, and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. Three debug registers (DEBUG, DEPC, and DESAVE) have been added to the MIPS Coprocessor 0 (CP0) register set. The DEBUG register shows the cause of the debug exception and is used for setting up singlestep operations. The DEPC, or Debug Exception Program Counter, register holds the address on which the debug exception was taken. This is used to resume program execution after the debug operation finishes. Finally, the DESAVE, or Debug Exception Save, register enables the saving of general-purpose registers used during execution of the debug exception handler. To exit debug mode, a Debug Exception Return (DERET) instruction is executed. When this instruction is executed, the system exits debug mode, allowing normal execution of application and system code to resume. 2.4.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking power-down mode is through execution of the WAIT instruction. For more information on power management, see 11.0 "Power Saving". 2.4.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX core is in the clock tree and clocking registers. The PIC32MX uses extensive use of local gated-clocks to reduce this dynamic power consumption. 2.5.2 EJTAG HARDWARE BREAKPOINTS 2.5 EJTAG Debug Support The PIC32MX core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard user mode and kernel modes of operation, the PIC32MX core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the PIC32MX core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define what registers are selected and how they are used. There are several types of simple hardware breakpoints defined in the EJTAG specification. These stop the normal operation of the MCU and force the system into debug mode. There are two types of simple hardware breakpoints implemented in the PIC32MX core: Instruction breakpoints and Data breakpoints. The PIC32MX core has two data and six instruction breakpoints Instruction breaks occur on instruction fetch operations, and the break is set on the virtual address. A mask can be applied to the virtual address to set breakpoints on a range of instructions. Data breakpoints occur on load/store transactions. Breakpoints are set on virtual address values, similar to the Instruction breakpoint. Data breakpoints can be set on a load, a store, or both. Data breakpoints can also be set based on the value of the load/store operation. Finally, masks can be applied to both the virtual address and the load/store value. 2.5.3 INSTRUCTION TRACING The PIC32MX core includes Trace support for real-time tracing of instruction addresses. The trace information is collected in an off-chip memory, for post-capture processing by trace regeneration software. Off-chip trace memory is accessed through a special trace probe that consists of 4 data pins plus a clock. DS61143-page 30 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 2.6 MCU Initialization Software is required to initialize the following parts of the device after a reset event. 2.6.1 GENERAL-PURPOSE REGISTERS The MCU register file powers up in an unknown state with the exception of r0 which is always 0. Initializing the rest of the register file is not required for proper operation of hardware. Depending on the software environment however, several registers may need to be initialized. Some of these are: * SP - Stack Pointer * GP - Global Pointer * FP - Frame Pointer 2.6.2 COPROCESSOR 0 STATE Miscellaneous CP0 states need to be initialized prior to leaving the boot code. There are various exceptions which are blocked by ERL = 1 or EXL = 1 and which are not cleared by Reset. These can be cleared to avoid taking spurious exceptions when leaving the boot code. TABLE 2-6: CP0 Register Cause Config CP0 INITIALIZATION Action WP (Watch Pending), SW0/1 (Software Interrupts) should be cleared. Typically, the K0, KU and K23 fields should be set to the desired Cache Coherency Algorithm (CCA) value prior to accessing the corresponding memory regions. But in the M4K core, all CCA values are treated identically, so the hardware reset value of these fields need not be modified. Count(1) Should be set to a known value if Timer Interrupts are used. Compare(1) Should be set to a known value if Timer Interrupts are used. The write to compare will also clear any pending Timer Interrupts (Thus, Count should be set before Compare to avoid any unexpected interrupts). Status Desired state of the device should be set. Other CP0 state Other registers should be written before they are read. Some registers are not explicitly writeable, and are only updated as a by-product of instruction execution or a taken exception. Uninitialized bits should be masked off after reading these registers. Note 1: When the Count register is equal to the Compare register a timer interrupt is signaled. There is a mask bit in the interrupt controller to disable passing this interrupt to the MCU if desired. 2.7 I/O Pin Configuration The MCU module has EJTAG pins that may be configured as user-available I/O pins. If EJTAG is used for debug, it is important to make sure that software does not clear DDPCON (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 31 PIC32MX NOTES: DS61143-page 32 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 3.0 INSTRUCTION SET The PIC32MX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32MX does not support the following features: * CoreExtend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Table 3-1 provides a summary of instructions implemented by the PIC32MX family core. TABLE 3-1: Instruction ADD ADDI ADDIU ADDIUPC ADDU AND ANDI B BAL BEQ BEQL PIC32MX FAMILY INSTRUCTION SET Description Integer Add Integer Add Immediate Unsigned Integer Add Immediate Unsigned Integer Add Immediate to PC (MIPS16eTM only) Unsigned Integer Add Logical AND Logical AND Immediate Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) Branch and Link (Assembler idiom for: BGEZAL r0, offset) Branch On Equal Branch On Equal Likely Function Rd = Rs + Rt Rt = Rs + Immed Rt = Rs +U Immed Rt = PC +u Immed Rd = Rs +U Rt Rd = Rs & Rt Rt = Rs & (016 || Immed) PC += (int)offset GPR[31> = PC + 8 PC += (int)offset if Rs == Rt PC += (int)offset if Rs == Rt PC += (int)offset else Ignore Next Instruction if !Rs[31> PC += (int)offset GPR[31> = PC + 8 if !Rs[31> PC += (int)offset GPR[31> = PC + 8 if !Rs[31> PC += (int)offset else Ignore Next Instruction if !Rs[31> PC += (int)offset else Ignore Next Instruction if !Rs[31> && Rs != 0 PC += (int)offset if !Rs[31> && Rs != 0 PC += (int)offset else Ignore Next Instruction if Rs[31> || Rs == 0 PC += (int)offset BGEZ BGEZAL Branch on Greater Than or Equal To Zero Branch on Greater Than or Equal To Zero And Link BGEZALL Branch on Greater Than or Equal To Zero And Link Likely BGEZL Branch on Greater Than or Equal To Zero Likely BGTZ BGTZL Branch on Greater Than Zero Branch on Greater Than Zero Likely BLEZ Branch on Less Than or Equal to Zero (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 33 PIC32MX FAMILY TABLE 3-1: Instruction BLEZL PIC32MX FAMILY INSTRUCTION SET (CONTINUED) Description Branch on Less Than or Equal to Zero Likely Function if Rs[31> || Rs == 0 PC += (int)offset else Ignore Next Instruction if Rs[31> PC += (int)offset GPR[31> = PC + 8 if Rs[31> PC += (int)offset GPR[31> = PC + 8 if Rs[31> PC += (int)offset else Ignore Next Instruction if Rs[31> PC += (int)offset else Ignore Next Instruction if Rs != Rt PC += (int)offset if Rs != Rt PC += (int)offset else Ignore Next Instruction Break Exception Rd = NumLeadingOnes(Rs) Rd = NumLeadingZeroes(Rs) See Software User's Manual PC = DEPC Exit Debug Mode Rt = Status; StatusIE = 0 LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; StatusIE = 1 if SR[2> PC = ErrorEPC else PC = EPC SR[1> = 0 SR[2> = 0 LL = 0 Rt = ExtractField(Rs, pos, size) Rt = InsertField(Rs, Rt, pos, size) PC = PC[31:28> || offset<<2 BLTZ BLTZAL Branch on Less Than Zero Branch on Less Than Zero And Link BLTZALL Branch on Less Than Zero And Link Likely BLTZL Branch on Less Than Zero Likely BNE BNEL Branch on Not Equal Branch on Not Equal Likely BREAK CLO CLZ COP0 DERET DI DIV DIVU EHB Breakpoint Count Leading Ones Count Leading Zeroes Coprocessor 0 Operation Return from Debug Exception Atomically Disable Interrupts Divide Unsigned Divide Execution Hazard Barrier EI ERET Atomically Enable Interrupts Return from Exception EXT INS J Extract Bit Field Insert Bit Field Unconditional Jump DS61143A-page 34 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 3-1: Instruction JAL JALR JALR.HB JALRC JR JR.HB JRC LB LBU LH LHU LL Jump and Link Jump and Link Register Jump and Link Register with Hazard Barrier Jump and Link Register Compact - do not execute instruction in jump delay slot (MIPS16eTM only) Jump Register Jump Register with Hazard Barrier PIC32MX FAMILY INSTRUCTION SET (CONTINUED) Description Function GPR[31> = PC + 8 PC = PC[31:28> || offset<<2 Rd = PC + 8 PC = Rs Like JALR, but also clears execution and instruction hazards Rd = PC + 2 PC = Rs PC = Rs Like JR, but also clears execution and instruction hazards Jump Register Compact - do not execute instruction in PC = Rs jump delay slot (MIPS16e only) Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word Rt = (byte)Mem[Rs+offset> Rt = (ubyte))Mem[Rs+offset> Rt = (half)Mem[Rs+offset> Rt = (uhalf)Mem[Rs+offset> Rt = Mem[Rs+offset> LL = 1 LLAdr = Rs + offset Rt = immediate << 16 Rt = Mem[Rs+offset> Rt = Mem[PC+offset> See Architecture Reference Manual See Architecture Reference Manual HI | LO += (int)Rs * (int)Rt HI | LO += (uns)Rs * (uns)Rt Rt = CPR[0, Rd, sel> Rd = HI Rd = LO if Rt 1/4 0 then Rd = Rs if Rt = 0 then Rd = Rs HI | LO -= (int)Rs * (int)Rt HI | LO -= (uns)Rs * (uns)Rt CPR[0, n, Sel> = Rt HI = Rs LO = Rs HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt)31..0 HI | LO = (int)Rs * (int)Rd HI | LO = (uns)Rs * (uns)Rd LUI LW LWPC LWL LWR MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MUL MULT MULTU NOP NOR OR Load Upper Immediate Load Word Load Word, PC relative Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move From Coprocessor 0 Move From HI Move From LO Move Conditional on Not Zero Move Conditional on Zero Multiply-Subtract Multiply-Subtract Unsigned Move To Coprocessor 0 Move To HI Move To LO Multiply with register write Integer Multiply Unsigned Multiply No Operation (Assembler idiom for: SLL r0, r0, r0) Logical NOR Logical OR Rd = ~(Rs | Rt) Rd = Rs | Rt (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 35 PIC32MX FAMILY TABLE 3-1: Instruction ORI RDHWR RDPGPR RESTORE ROTR ROTRV SAVE SB SC PIC32MX FAMILY INSTRUCTION SET (CONTINUED) Description Logical OR Immediate Read Hardware Register Read GPR from Previous Shadow Set Restore registers and deallocate stack frame (MIPS16eTM only) Rotate Word Right Rotate Word Right Variable Store Byte Store Conditional Word Function Rt = Rs | Immed Allows unprivileged access to registers enabled by HWREna register Rt = SGPR[SRSCtlPSS, Rd> See Architecture Reference Manual Rd = Rtsa-1..0 || Rt31..sa Rd = RtRs-1..0 || Rt31..Rs Save registers and allocate stack frame (MIPS16e only) See Architecture Reference Manual (byte)Mem[Rs+offset> = Rt if LL = 1 mem[Rs+offset> = Rt Rt = LL Trap to SW Debug Handler Rd = (byte)Rs Rd = (half)Rs (half)Mem[Rs+offset> = Rt Rd = Rt << sa Rd = Rt << Rs[4:0> if (int)Rs < (int)Rt Rd = 1 else Rd = 0 if (int)Rs < (int)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 Rd = (int)Rt >> sa Rd = (int)Rt >> Rs[4:0> Rd = (uns)Rt >> sa Rd = (uns)Rt >> Rs[4:0> NOP Rt = (int)Rs - (int)Rd Rt = (uns)Rs - (uns)Rd Mem[Rs+offset> = Rt See Architecture Reference Manual See Architecture Reference Manual See Software User's Manual SystemCallException SDBBP SEB SEH SH SLL SLLV SLT Software Debug Break Point Sign-Extend Byte Sign-Extend Half Store Half Shift Left Logical Shift Left Logical Variable Set on Less Than SLTI Set on Less Than Immediate SLTIU Set on Less Than Immediate Unsigned SLTU Set on Less Than Unsigned SRA SRAV SRL SRLV SSNOP SUB SUBU SW SWL SWR SYNC SYSCALL Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit No Operation Integer Subtract Unsigned Subtract Store Word Store Word Left Store Word Right Synchronize System Call DS61143A-page 36 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 3-1: Instruction TEQ TEQI TGE TGEI TGEIU TGEU TLT TLTI TLTIU TLTU TNE TNEI WAIT WRPGPR WSBH XOR XORI ZEB ZEH Trap if Equal Trap if Equal Immediate Trap if Greater Than or Equal Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate Unsigned Trap if Greater Than or Equal Unsigned Trap if Less Than Trap if Less Than Immediate Trap if Less Than Immediate Unsigned Trap if Less Than Unsigned Trap if Not Equal Trap if Not Equal Immediate Wait for Interrupts Write to GPR in Previous Shadow Set Word Swap Bytes Within Halfwords Exclusive OR Exclusive OR Immediate Zero-extend byte (MIPS16eTM only) Zero-extend half (MIPS16e only) PIC32MX FAMILY INSTRUCTION SET (CONTINUED) Description Function if Rs == Rt TrapException if Rs == (int)Immed TrapException if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < (int)Rt TrapException if (int)Rs < (int)Immed TrapException if (uns)Rs < (uns)Immed TrapException if (uns)Rs < (uns)Rt TrapException if Rs != Rt TrapException if Rs != (int)Immed TrapException Stall until interrupt occurs SGPR[SRSCtlPSS, Rd> = Rt Rd = Rt23..16 || Rt31..24 || Rt7..0 || Rt15..8 Rd = Rs ^ Rt Rt = Rs ^ (uns)Immed Rt = (ubyte) Rs Rt = (uhalf) Rs (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 37 PIC32MX FAMILY NOTES: DS61143A-page 38 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 4.0 Note: PREFETCH CACHE This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 4.1 * * * * * * * * Features The Prefetch cache increases performance for applications executing out of the cacheable program flash memory region by implementing instruction caching, data caching, and instruction prefetching. 16 Fully Associative Lockable Cache Lines 16-byte Cache Lines Up to 4 Cache Lines allocated to Data 2 Cache Lines with Address Mask to hold repeated instructions Pseudo LRU replacement policy All Cache Lines are software writable 16-byte parallel memory fetch Predictive Instruction Prefetch FIGURE 4-1: PREFETCH MODULE BLOCK DIAGRAM FSM BMX/CPU CTRL Tag Logic Cache Line CTRL Bus Ctrl Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Pre-Fetch Tag CTRL PreFetch Pre-Fetch RDATA Cache Line Address Encode BMX/CPU RDATA PFM (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 39 PIC32MX FAMILY TABLE 4-1: Virtual Address PREFETCH SFR SUMMARY Name 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- -- Bit 30/22/14/6 -- -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- -- Bit 27/19/11/3 -- -- -- -- Bit 26/18/10/2 -- -- -- Bit 25/17/9/1 -- -- PFMWS<2:0> DCSZ<1:0> Bit 24/16/8/0 -- CHECOH BF88_4000 CHECON PREFEN<1:0> BF88_4004 CHECONCLR BF88_4008 CHECONSET BF88_400C CHECONINV BF88_4010 CHEACC 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHEWEN -- -- -- -- -- -- -- Clears selected bits in CHECON, read yields undefined value Sets selected bits in CHECON, read yields undefined value Inverts selected bits in CHECON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHEIDX<3:0> BF88_4014 CHEACCCLR BF88_4018 CHEACCSET BF88_401C CHEACCINV BF88_4020 CHETAG 31:0 31:0 31:0 31:24 23:16 15:8 7:0 LTAGBOOT -- Clears selected bits in CHEACC, read yields undefined value Sets selected bits in CHEACC, read yields undefined value Inverts selected bits CHEACC, read yields undefined value -- -- -- LTAG<23:16> LTAG<15:8> LTAG<7:4> LVALID LLOCK LTYPE -- Clears selected bits in CHETAG, read yields undefined value Sets selected bits in CHETAG, read yields undefined value Inverts selected bits CHETAG, read yields undefined value -- -- -- -- LMASK<7:5> -- -- -- -- -- -- -- LMASK<15:8> -- -- -- -- Clears selected bits in CHEMSK, read yields undefined value Sets selected bits in CHEMSK, read yields undefined value Inverts selected bits CHEMSK, read yields undefined value CHEW0<31:24> CHEW0<23:16> CHEW0<15:8> CHEW0<7:0> CHEW1<31:24> CHEW1<23:16> CHEW1<15:8> CHEW1<7:0> CHEW2<31:24> CHEW2<23:16> CHEW2<15:8> CHEW2<7:0> CHEW3<31:24> CHEW3<23:16> CHEW3<15:8> CHEW3<7:0> -- -- -- -- -- -- -- CHELRU<24> CHELRU<23:16> CHELRU<15:8> CHELRU<7:0>> CHEHIT<31:24> CHEHIT<23:16> CHEHIT<15:8> CHENIT<7:0> -- -- -- -- -- -- -- -- -- BF88_4024 CHETAGCLR BF88_4028 CHETAGSET BF88_402C CHETAGINV BF88_4030 CHEMSK 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_4034 CHEMSKCLR BF88_4038 CHEMSKSET BF88_403C CHEMSKINV BF88_4040 CHEW0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_4050 CHEW1 31:24 23:16 15:8 7:0 BF88_4060 CHEW2 31:24 23:16 15:8 7:0 BF88_4070 CHEW3 31:24 23:16 15:8 7:0 BF88_4080 CHELRU 31:24 23:16 15:8 7:0 BF88_4090 CHEHIT 31:24 23:16 15:8 7:0 DS61143A-page 40 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 4-1: Virtual Address PREFETCH SFR SUMMARY (CONTINUED) Name 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 BF88_40A0 CHEMIS CHEMIS<31:24> CHEMIS<23:16> CHEMIS<15:8> CHEMIS<7:0> PFABT<31:24> PFABT<23:16> PFABT<15:8> PFABT<7:0> BF88_40C0 PFABT 31:24 23:16 15:8 7:0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 41 PIC32MX FAMILY 4.2 Prefetch Registers CHECON: CACHE CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CHECOH bit 16 U-0 -- r-0 -- r-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 U-0 -- R/W-0 R/W-0 U-0 -- R/W-1 R/W-1 PFMWS<2:0> bit 0 R/W-1 U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-17 bit 16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) REGISTER 4-1: DCSZ<1:0> PREFEN<1:0> Unimplemented: Read as `0' CHECOH: Cache Coherency setting on a PFM Program Cycle bit 1 = Invalidate all data and instruction lines 0 = Invalidate all data lnes and instruction lines that are not locked Unimplemented: Read as `0' Reserved: Must be written with zeros Unimplemented: Read as `0' DCSZ<1:0>: Data Cache Size in Lines bits 11 = Enable data caching with a size of 4 Lines 10 = Enable data caching with a size of 2 Lines 01 = Enable data caching with a size of 1 Line 00 = Disable data caching Changing this field causes all lines to be re-initialized to the "invalid" state. Unimplemented: Read as `0' PREFEN<1:0>: Predictive Prefetch Cache Enable bits 11 = Enable predictive prefetch cache for both cacheable and non-cacheable regions 10 = Enable predictive prefetch cache for non-cacheable regions only 01 = Enable predictive prefetch cache for cacheable regions only 00 = Disable predictive prefetch cache Unimplemented: Read as `0' bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3 DS61143A-page 42 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-1: bit 2-0 CHECON: CACHE CONTROL REGISTER (CONTINUED) PFMWS<2:0>: PFM Access Time Defined in terms of SYSLK Wait states bits 111 = Seven Wait states 110 = Six Wait states 101 = Five Wait state 100 = Four Wait states 011 = Three Wait states 010 = Two Wait states 001 = One Wait state 000 = Zero Wait states (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 43 PIC32MX FAMILY REGISTER 4-2: R/W-0 CHEWEN bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CHEACC: CACHE ACCESS U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 CHEIDX<3:0> CHEWEN: Cache Access Enable bits for registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3 1 = The cache line selected by CHEIDX is writable 0 = The cache line selected by CHEIDX is not writable Unimplemented: Read as `0' CHEIDX<3:0>: Cache Line Index bits The value selects the cache line for reading or writing. bit 30-4 bit 3-0 DS61143A-page 44 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-3: R/W-0 LTAGBOOT bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-0 LVALID R/W-0 LLOCK R/W-1 LTYPE r-0 -- bit 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHETAG(1): CACHE TAG REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-x bit 16 R/W-x bit 8 LTAG<23:16> LTAG<15:8> LTAG<7:4> LTAGBOOT: Line TAG Address Boot 1 = The line is in the 0x1D000000 (physical) area of memory 0 = The line is in the 0x1FC00000 (physical) area of memory Unimplemented: Read as `0' LTAG<23:4>: Line TAG Address bits LTAG bits are compared against physical address <23:4> to determine a hit. Because its address range and position of Flash in kernel space and user space, the LTAG Flash address is identical for virtual addresses, (system) physical addresses, and Flash physical addresses. LVALID: Line Valid bit 1 = The line is valid and is compared to the physical address for hit detection 0 = The line is not valid and is not compared to the physical address for hit detection LLOCK: Line Lock bit 1 = The line is locked and will not be replaced 0 = The line is not locked and can be replaced LTYPE: Line Type bit 1 = The line caches instruction words 0 = The line caches data words Reserved: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>). bit 30-24 bit 23-4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 45 PIC32MX FAMILY REGISTER 4-4: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-5 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 LMASK<7:5> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CHEMSK(1): CACHE TAG MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 LMASK<15:8> Unimplemented: Read as `0' LMASK<15:5>: Line Mask bits 1 = Enables mask logic to force a match on the corresponding bit position in LTAG (CHETAG<23:4>) and the physical address. 0 = Only writeable for values of CHEIDX (CHEACC<3:0>) equal to OxOA and OxOB. Disables mask logic. Unimplemented: Read as `0' The TAG Mask of the Line pointed to by CHEIDX (CHEACC<3:07>). bit 4-0 Note 1: DS61143A-page 46 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-5: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW0: CACHE WORD 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEW0<31:24> CHEW0<23:16> CHEW0<15:8> CHEW0<7:0> CHEW0<31:0>: Word 0 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 47 PIC32MX FAMILY REGISTER 4-6: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1: CACHE WORD 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEW1<31:24> CHEW1<23:16> CHEW1<15:8> CHEW1<7:0> CHEW1<31:0>: Word 1 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. DS61143A-page 48 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-7: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW2 CACHE WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEW2<31:24> CHEW2<23:16> CHEW2<15:8> CHEW2<7:0> CHEW2<31:0>: Word 2 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 49 PIC32MX FAMILY REGISTER 4-8: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 Note 1: W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3(1): CACHE WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEW3<31:24> CHEW3<23:16> CHEW3<15:8> CHEW3<7:0> CHEW3<31:0>: Word 3 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. This register is a window into the cache data array and is readable only if the device is not code-protected. DS61143A-page 50 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-9: U-0 -- bit 31 R-0 bit 23 R-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-25 bit 24-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU: CACHE LRU REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0 CHELRU<24> bit 24 R-0 bit 16 R-0 bit 8 CHELRU<23-16> CHELRU<15-8> CHELRU<7-0> Unimplemented: Read as `0' CHELRU<24:0>: Cache Least Recently Used State Encoding bits CHELRU indicates the Pseudo-LRU state of the cache. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 51 PIC32MX FAMILY REGISTER 4-10: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT: CACHE HIT STATISTICS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEHIT<31:24> CHEHIT<23:16> CHEHIT<15:8> CHEHIT<7:0> CHEHIT<31:0>: Cache Hit Count bits Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable accesses do not modify this value. DS61143A-page 52 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 4-11: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEMIS: CACHE MISS STATISTICS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHEMIS<31:24> CHEMIS<23:16> CHEMIS<15:8> CHEMIS<7:0> CHEMIS<31:0>: Cache Miss Count bits Incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. Non-cacheable accesses do not modify this value. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 53 PIC32MX FAMILY REGISTER 4-12: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PFABT: PREFETCH CACHE ABORT STATISTICS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 PFABT<31:24> PFABT<23:16> PFABT<15:8> PFABT<7:0> PFABT<31:0>: Prefab Abort Count bits Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load or store. DS61143A-page 54 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 4.3 Prefetch Configuration TABLE 4-2: DCSZ<1:0> 00 01 10 11 The CHECON register controls the configurations available for instruction and data caching of Program Flash Memory. In addition to normal instruction caching, the prefetch cache has the ability to cache lines specifically for Flash Memory data. The CHECON.DCSZ field controls the number of lines allocated to program data caching. Table 4-2 shows the cache line relationship for values of DCSZ. The data caching capability is for read only data such as constants, parameters, table data, etc., that are not modified. PROGRAM DATA CACHE Lines Allocated to Program Data None Cache Line Number 15 Cache Line Number 14 and 15 Cache Line Number 12 through 15 The CHECON.PREFEN field controls predictive prefetching, which allows the prefetch module to speculatively fetch the next 16-byte aligned set of instructions. The prefetch module loads data into the data array only on accesses to cacheable regions (CCA bits = 3). EXAMPLE 4-1: EXAMPLE CODE: INITIALIZATION CODE FOR PREFETCH MODULE /* Prefetch Cache Initialization */ tmp = _CP0_GET_CONFIG(); // read CONFIG register tmp |= 1; // kseg0 cacheable _CP0_SET_CONFIG(tmp); // write CONFIG register CHECON = (1<<4) | 3; // 3 wait-states, // Prefetching enabled for cached memory 4.3.1 LINE LOCKING Each line in the cache can be locked to hold its contents. A line is locked if both LVALID=1 and LLOCK=1. If LVALID=0 and LLOCK=1, the prefetch module issues a preload request (see below). Locking cache lines may reduce the performance of general program flow. However, if one or two functions calls consume a significant percent of overall processing, locking their address can provide improved performance. Though any number of lines can be locked, the cache works most efficiently when locking either 1 or 4 lines. If locking 4 lines, choose lines whose line number divide by 4 have the same quotient. This locks an entire LRU group which benefits the LRU algorithm. For example, lines 8, 9, A, and B each have a quotient of 2 when divided by 4. If cache lines are manually filled, it is recommended that the following sequence be used. 1. 2. 3. Choose a cache line to fill. Set the Lock and Valid bits of the cache line by writing to CHETAG. Write to each word of the cache line by writing to CHEW0, CHEW1, CHEW2, and CHEW3. EXAMPLE 4-2: EXAMPLE CODE: LOCKING A LINE IN PREFETCH MODULE #define LOCKED_LINE_NUM 3 /* lock first line of func1() in cache */ CHEACC = (1<<31) | LOCKED_LINE_NUM; tmp = (unsigned long)func1; ltagboot = (tmp & 0x00c00000) ? 0 : 1; // 0x9fc????? or 0x9d0????? CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 55 PIC32MX FAMILY 4.3.2 PRELOAD BEHAVIOR 4.3.3 ADDRESS MASK Application code can direct the prefetch module to preform a preload of a cache line and lock it with instructions or data from the flash. The Preload function uses the CHEACC.CHEIDX register field to select the cache line into which the load is directed. Setting CHEACC.CHEWEN to a `1' enables writes to the CHETAG register. Writing CHETAG.LVALID = 0 and CHETAG.LLOCK = 1 causes a preload request to the prefetch module. The controller acknowledges the request in the cycle after the write and if possible stops any outstanding flash access and stalls any CPU load from the cache or Flash. When it has finished or stalled the previous transaction, it initiates a flash read to fetch the instructions or data requested using the address in CHETAG.LTAG. After the programmed number of wait states as defined by CHECON.PFMWS, the controller updates the data array with the values read from flash. On the update it sets CHETAG.LVALID = 1. The LRU state of the line is not affected. Once the controller finishes updating the cache, it allows CPU requests to complete. If this request misses the cache, the controller initiates a flash read which incurs the full flash access time. Cache lines 10 and 11 allow masking of the CPU address and tag address to force a match on corresponding bits. The CHEMSK.LMASK field is set up to compliment the interrupt vector spacing field in the CPU. This feature allows boot code to lock the first four instruction of a vector in the cache. If all vectors contain identical instructions in their first four locations, then setting the CHEMSK.LMASK to match the vector spacing and the LTAG to match the vector base address causes all the vector addresses to hit the cache. The prefetch module responds with zero wait states and immediately initiates a fetch of the next set of four instruction for the requesting vector if prefetch is enabled. Using CHEMSK.LMASK is restricted to aligned address ranges. Its size allows for a max range of 32KB and a minimum spacing of 32B. Using the two lines, in conjunction provides the ability to have different ranges and different spacing. Setting up the address mask such that more than one line will match an address causes undefined results. Therefore, it is highly recommended to set up masking before entering cacheable code. EXAMPLE 4-3: EXAMPLE CODE: DUPLICATION OF CODE USING MASK REGISTERS #define INT_LINE_NUM 10 CHEACC = (1<<31) | INT_LINE_NUM; tmp = (unsigned long)intbase; ltagboot = (tmp & 0x00c00000) ? 0 : 1; // 0x9fc????? or 0x9d0????? CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid CHEMSK = 0xe0; // first 4 instructions of intbase() replicated 8 times on 32-byte boundaries DS61143A-page 56 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 4.3.4 PREDICTIVE PREFETCH BEHAVIOR 4.3.5 COHERENCY SUPPORT When configured for predictive prefetch on cacheable addresses, the module predicts the next line address and returns it into the pseudo LRU line of the cache. If enabled, the prefetch function starts predicting based on the first CPU instruction fetch. When the first line is placed in the cache, the module simply increments the address to the next 16-byte aligned address and starts a flash access. When running linear code (i.e. no jumps), the flash returns the next set of instructions into the prefetch buffer on or before all instructions can be executed from the previous line. If at any time during a predicted flash access, a new CPU address does not match the predicted one, the flash access will be changed to the correct address. This behavior does not cause the CPU access to take any longer than without prediction. If an access that misses the cache hits the prefetch buffer, the instructions are placed in the pseudo LRU line along with its address tag. The pseudo LRU value is marked as the most recently used line and other lines are updated accordingly. If an access misses both the cache and the prefetch buffer, the access passes to the flash and those returning instructions are placed in the pseudo LRU line. When configured for predictive prefetch on non-cacheable addresses, the controller only uses the prefetch buffer. The LRU cache line is not updated for hits or fills so the cache remains intact. For linear code, enabling predictive prefetch for non-cacheable addresses allows the CPU to fetch instructions in zero wait states. It is not useful to use non-cacheable predictive prefetching when accesses to the flash are set for zero wait states. The controller holds prefetched instructions on the output of the flash for up to 3 clock cycles (while the CPU is fetching from the buffer). This consumes more power without any benefit for zero wait state flash accesses. Predictive data prefetching is not supported. However, a data access in the middle of a predictive instruction fetch causes the prefetch controller to stop the flash access for the instruction fetch and to start the data load from flash. The predictive prefetch does not resume, but instead waits for another instruction fetch. At which time, it either fills the buffer because of a miss, or starts a prefetch because of a hit. It is not possible to execute out of cache while programming the flash memory. The flash controller stalls the cache during the programming sequence. Therefore, user code that initiates a programming sequence must not be located in a cacheable address region. If CHECON.CHECOH = 1, then coherency is strictly supported by invalidating, unlocking, and clearing masks for all lines whenever the Flash Program Memory is written or programmed. If CHECON.CHECOH = 0, then only lines that are not locked are forced invalid. Lines that are locked are retained. 4.4 Prefetch Module Interrupts and Exceptions The prefetch module does not generate any interrupts. Exceptions can occur if cache lines are marked as valid manually by writing to individual CHETAG registers then executing code that hits one of these lines containing invalid instructions. Also manually placing data into an un-locked cache line may cause a coherency problem from an eviction due to a cache miss in the middle of the loading algorithm. 4.4.1 I/O PIN CONFIGURATION The prefetch module does not use any external pins. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 57 PIC32MX FAMILY NOTES: DS61143A-page 58 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 5.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without the CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, I2CTM, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four Identical Channels, each featuring: - Auto-Increment Source and Destination Address registers - Source and Destination Pointers * Automatic Word-Size Detection: - Transfer granularity down to byte level - Bytes need not be word-aligned at source and destination * Fixed Priority Channel Arbitration * Flexible DMA Channel Operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation Module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable * Extended Addressing mode: - Extended Addressing mode allows large memory to memory copies TABLE 5-1: DMA CONTROLLER FEATURES Different Source and Destination Sizes Memory to Peripheral Transfers Channel Auto-Enable Unaligned Transfers Memory to Memory Transfers Channel Chaining Events Start/Stop Available DMA Modes Normal Addressing Mode <= 256B Yes No Yes No Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Extended Addressing Mode <= 64 KB (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 59 CRC Calculation Transfer Length Pattern Match Detection PIC32MX FAMILY FIGURE 5-1: DMA CONTROLLER BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus Address Decoder Channel 0 Control I0 SE L Channel 1 Control I1 I2 Y Bus Interface Device Bus + Bus Arbitration Global Control (DMACON) Channel n Control In L SE Channel Priority Arbitration 5.1 DMA Controller Registers DMA GLOBAL SFR SUMMARY Name DMACON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- ON -- Bit 30/22/14/6 -- -- FRZ -- Bit 29/21/13/5 -- -- SIDL -- Bit 28/20/12/4 -- -- SUSPEND -- Bit 27/19/11/3 -- -- -- -- Bit 26/18/10/2 -- -- -- -- Bit 25/17/9/1 -- -- -- Bit 24/16/8/0 -- -- -- -- TABLE 5-2: Virtual Address BF88_3000 BF88_3004 BF88_3008 BF88_300C BF88_3010 DMACONCLR DMACONSET DMACONINV DMASTAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- -- -- -- -- Write clears selected bits in DMACON, read yields undefined value Write sets selected bits in DMACON, read yields undefined value Write inverts selected bits in DMACON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- RDWR -- -- -- -- -- -- -- -- -- -- DMACH<1:0> BF88_3020 DMAADDR 31:24 23:16 15:8 7:0 DMAADDR<31:24> DMAADDR<23:16> DMAADDR<15:8> DMAADDR<7:0> DS61143A-page 60 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 5-3: Virtual Address BF88_3030 DMA CRC SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- -- CRCEN Bit 30/22/14/6 -- -- -- CRCAPP Bit 29/21/13/5 -- -- -- -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 -- -- Bit 26/18/10/2 -- -- PLEN<4:0> -- CRCCH<1:0> Bit 25/17/9/1 -- -- Bit 24/16/8/0 -- -- DCRCCON BF88_3034 DCRCCONCLR BF88_3038 DCRCCONSET BF88_303C DCRCCONINV BF88_3040 DCRCDATA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in DCRCCON, read yields undefined value Write sets selected bits in DCRCCON, read yields undefined value Write inverts selected bits in DCRCCON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- DCRCDATA<15:8> DCRCDATA<7:0> Write clears selected bits in DCRCDATA, read yields undefined value Write sets selected bits in DCRCDATA, read yields undefined value Write inverts selected bits in DCRCDATA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3044 DCRCDATACLR BF88_3048 DCRCDATASET BF88_304C DCRCDATAINV BF88_3050 DCRCXOR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 DCRCXOR<15:8> DCRCXOR<7:0> Write clears selected bits in DCRCXOR, read yields undefined value Write sets selected bits in DCRCXOR, read yields undefined value Write inverts selected bits in DCRCXOR, read yields undefined value BF88_3054 DCRCXORCLR BF88_3058 DCRCXORSET BF88_305C DCRCXORINV 31:0 31:0 31:0 TABLE 5-4: Virtual Address (1) BF88_3060 DMA CHANNEL 0 SFR SUMMARY Name DCH0CON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- CHEN Bit 30/22/14/6 -- -- -- CHAED Bit 29/21/13/5 -- -- -- CHCHN Bit 28/20/12/4 -- -- -- CHAEN Bit 27/19/11/3 -- -- -- CHXM Bit 26/18/10/2 -- -- -- CHEDET Bit 25/17/9/1 -- -- -- Bit 24/16/8/0 -- -- CHCHNS CHPRI<1:0> BF88_3064 BF88_3068 BF88_306C BF88_3070 DCH0CONCLR DCH0CONSET DCH0CONINV DCH0ECON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CFORCE -- Write clears selected bits in DCH0CON, read yields undefined value Write sets selected bits in DCH0CON, read yields undefined value Write inverts selected bits in DCH0CON, read yields undefined value -- -- -- -- -- -- -- CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN -- -- -- Write clears selected bits in DCH0ECON, read yields undefined value Write sets selected bits in DCH0ECON, read yields undefined value Write inverts selected bits in DCH0ECON, read yields undefined value -- CHSDIE -- CHSDIF -- CHSHIE -- CHSHIF -- CHDDIE -- CHDDIF -- CHDHIE -- CHDHIF -- CHBCIE -- CHBCIF -- CHCCIE -- CHCCIF -- CHTAIE -- CHTAIF -- CHERIE -- CHERIF BF88_3074 DCH0ECONCLR BF88_3078 DCH0ECONSET BF88_307C DCH0ECONINV BF88_3080 DCH0INT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_3084 BF88_3088 BF88_308C BF88_3090 DCH0INTCLR DCH0INTSET DCH0INTINV DCH0SSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in DCH0INT, read yields undefined value Write sets selected bits in DCH0INT, read yields undefined value Write inverts selected bits in DCH0INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits in DCH0SSA, read yields undefined value Write sets selected bits in DCH0SSA, read yields undefined value Write inverts selected bits in DCH0SSA, read yields undefined value BF88_3094 BF88_3098 BF88_309C Note 1: 2: DCH0SSACLR DCH0SSASET DCH0SSAINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 61 PIC32MX FAMILY TABLE 5-4: Virtual Address (1) BF88_30A0 DMA CHANNEL 0 SFR SUMMARY (CONTINUED) Name DCH0DSA 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits in DCH0DSA, read yields undefined value Write sets selected bits in DCH0DSA, read yields undefined value Write inverts selected bits in DCH0DSA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_30A4 BF88_30A8 BF88_30AC BF88_30B0 DCH0DSACLR DCH0DSASET DCH0DSAINV DCH0SSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSSIZ<7:0> Write clears selected bits in DCH0SSIZ, read yields undefined value Write sets selected bits in DCH0SSIZ, read yields undefined value Write inverts selected bits in DCH0SSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_30B4 DCH0SSIZCLR BF88_30B8 BF88_30BC BF88_30C0 DCH0SSIZSET DCH0SSIZINV DCH0DSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits in DCH0DSIZ, read yields undefined value Write sets selected bits in DCH0DSIZ, read yields undefined value Write inverts selected bits in DCH0DSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_30C4 DCH0DSIZCLR BF88_30C8 DCH0DSIZSET BF88_30CC BF88_30D0 DCH0DSIZINV DCH0SPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSPTR<7:0> BF88_30E0 DCH0DPTR 31:24 23:16 15:8 7:0 CHDPTR<15:8>(2) CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_30F0 DCH0CSIZ 31:24 23:16 15:8 7:0 CHCSIZ<7:0> Write clears selected bits in DCH0CSIZ, read yields undefined value Write sets selected bits in DCH0CSIZ, read yields undefined value Write inverts selected bits in DCH0CSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_30F4 DCH0CSIZCLR BF88_30F8 DCH0CSIZSET BF88_30FC BF88_3100 DCH0CSIZINV DCH0CPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHCPTR<7:0> BF88_3110 DCH0DAT 31:24 23:16 15:8 7:0 CHPDAT<7:0> Write clears selected bits in DCH0DAT, read yields undefined value Write sets selected bits in DCH0DAT, read yields undefined value Write inverts selected bits in DCH0DAT, read yields undefined value BF88_3114 BF88_3118 BF88_311C Note 1: 2: DCH0DATCLR DCH0DATSET DCH0DATINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. DS61143A-page 62 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 5-5: Virtual Address BF88_1070 BF88_1040 BF88_1120 Note 1: DMA CHANNEL 0 INTERRUPT REGISTER SUMMARY(1) Name IEC1 IFS1 IPC9 23:16 23:16 7:0 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 DMA3IE DMA3IF DMA0IP<2:0> Bit 26/18/10/2 DMA2IE DMA2IF Bit 25/17/9/1 DMA1IE DMA1IF Bit 24/16/8/0 DMA0IE DMA0IF DMA0IS<1:0> This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers. TABLE 5-6: Virtual Address BF88_3120 DMA CHANNEL 1 SFR SUMMARY Name DCH1CON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- CHEN Bit 30/22/14/6 -- -- -- CHAED Bit 29/21/13/5 -- -- -- CHCHN Bit 28/20/12/4 -- -- -- CHAEN Bit 27/19/11/3 -- -- -- CHXM Bit 26/18/10/2 -- -- -- CHEDET Bit 25/17/9/1 -- -- -- Bit 24/16/8/0 -- -- CHCHNS CHPRI<1:0> BF88_3124 BF88_3128 BF88_312C BF88_3130 DCH1CONCLR DCH1CONSET DCH1CONINV DCH1ECON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CFORCE -- Write clears selected bits in DCH1CON, read yields undefined value Write sets selected bits in DCH1CON, read yields undefined value Write inverts selected bits in DCH1CON, read yields undefined value -- -- -- -- -- -- -- CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN - -- -- BF88_3134 DCH1ECONCLR BF88_3138 DCH1ECONSET BF88_313C DCH1ECONINV BF88_3140 DCH1INT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- CHSDIE -- CHSDIF Write clears selected bits in DCH1ECON, read yields undefined value Write sets selected bits in DCH1ECON, read yields undefined value Write inverts selected bits in DCH1ECON, read yields undefined value -- CHSHIE -- CHSHIF -- CHDDIE -- CHDDIF -- CHDHIE -- CHDHIF -- CHBCIE -- CHBCIF -- CHCCIE -- CHCCIF -- CHTAIE -- CHTAIF -- CHERIE -- CHERIF BF88_3144 BF88_3148 BF88_314C BF88_3150 DCH1INTCLR DCH1INTSET DCH1INTINV DCH1SSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in DCH1INT, read yields undefined value Write sets selected bits in DCH1INT, read yields undefined value Write inverts selected bits in DCH1INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits in DCH1SSA, read yields undefined value Write sets selected bits in DCH1SSA, read yields undefined value Write inverts selected bits in DCH1SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits in DCH1DSA, read yields undefined value Write sets selected bits in DCH1DSA, read yields undefined value Write inverts selected bits in DCH1DSA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3154 BF88_3158 BF88_315C BF88_3160 DCH1SSACLR DCH1SSASET DCH1SSAINV DCH1DSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_3164 BF88_3168 BF88_316C BF88_3170 DCH1DSACLR DCH1DSASET DCH1DSAINV DCH1SSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSSIZ<7:0> Write clears selected bits in DCH1SSIZ, read yields undefined value Write sets selected bits in DCH1SSIZ, read yields undefined value Write inverts selected bits in DCH1SSIZ, read yields undefined value BF88_3174 BF88_3178 BF88_317C Note 1: 2: DCH1SSIZCLR DCH1SSIZSET DCH1SSIZINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 63 PIC32MX FAMILY TABLE 5-6: Virtual Address BF88_3180 DMA CHANNEL 1 SFR SUMMARY (CONTINUED) Name DCH1DSIZ 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- Bit 30/22/14/6 -- -- Bit 29/21/13/5 -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 -- -- Bit 26/18/10/2 -- -- Bit 25/17/9/1 -- -- Bit 24/16/8/0 -- -- CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits in DCH1DSIZ, read yields undefined value Write sets selected bits in DCH1DSIZ, read yields undefined value Write inverts selected bits in DCH1DSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3184 BF88_3188 BF88_318C BF88_3190 DCH1DSIZCLR DCH1DSIZSET DCH1DSIZINV DCH1SPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSPTR<7:0> BF88_31A0 DCH1DPTR 31:24 23:16 15:8 7:0 CHDPTR<15:8>(2) CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_31B0 DCH1CSIZ 31:24 23:16 15:8 7:0 CHCSIZ<7:0> Write clears selected bits in DCH1CSIZ, read yields undefined value Write sets selected bits in DCH1CSIZ, read yields undefined value Write inverts selected bits in DCH1CSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_31B4 DCH1CSIZCLR BF88_31B8 DCH1CSIZSET BF88_31BC BF88_31C0 DCH1CSIZINV DCH1CPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHCPTR<7:0> BF88_31D0 DCH1DAT 31:24 23:16 15:8 7:0 CHPDAT<7:0> Write clears selected bits in DCH1DAT, read yields undefined value Write sets selected bits in DCH1DAT, read yields undefined value Write inverts selected bits in DCH1DAT, read yields undefined value BF88_31D4 BF88_31D8 BF88_31DC Note 1: 2: DCH1DATCLR DCH1DATSET DCH1DATINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. TABLE 5-7: Virtual Address BF88_1070 BF88_1040 BF88_1120 Note 1: DMA CHANNEL 1 INTERRUPT REGISTER SUMMARY(1) Name IEC1 IFS1 IPC9 23:16 23:16 15:8 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 DMA3IE DMA3IF DMA1IP<2:0> Bit 26/18/10/2 DMA2IE DMA2IF Bit 25/17/9/1 DMA1IE DMA1IF Bit 24/16/8/0 DMA0IE DMA0IF DMA1IS<1:0> This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A-page 64 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 5-8: Virtual Address(1) BF88_31E0 DMA CHANNEL 2 SFR SUMMARY Name DCH2CON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- CHEN Bit 30/22/14/6 -- -- -- CHAED Bit 29/21/13/5 -- -- -- CHCHN Bit 28/20/12/4 -- -- -- CHAEN Bit 27/19/11/3 -- -- -- CHXM Bit 26/18/10/2 -- -- -- CHEDET Bit 25/17/9/1 -- -- -- Bit 24/16/8/0 -- -- CHCHNS CHPRI<1:0> BF88_31E4 BF88_31E8 BF88_31EC BF88_31F0 DCH2CONCLR DCH2CONSET DCH2CONINV DCH2ECON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CFORCE -- Write clears selected bits in DCH2CON, read yields undefined value Write sets selected bits in DCH2CON, read yields undefined value Write inverts selected bits in DCH2CON, read yields undefined value -- -- -- -- -- -- -- CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN -- -- -- Write clears selected bits in DCH2ECON, read yields undefined value Write sets selected bits in DCH2ECON, read yields undefined value Write inverts selected bits in DCH2ECON, read yields undefined value -- CHSDIE -- CHSDIF -- CHSHIE -- CHSHIF -- CHDDIE -- CHDDIF -- CHDHIE -- CHDHIF -- CHBCIE -- CHBCIF -- CHCCIE -- CHCCIF -- CHTAIE -- CHTAIF -- CHERIE -- CHERIF BF88_31F4 BF88_31F8 BF88_31FC BF88_3200 DCH2ECONCLR DCH2ECONSET DCH2ECONINV DCH2INT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_3204 BF88_3208 BF88_320C BF88_3210 DCH2INTCLR DCH2INTSET DCH2INTINV DCH2SSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in DCH2INT, read yields undefined value Write sets selected bits in DCH2INT, read yields undefined value Write inverts selected bits in DCH2INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits in DCH2SSA, read yields undefined value Write sets selected bits in DCH2SSA, read yields undefined value Write inverts selected bits in DCH2SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits in DCH2DSA, read yields undefined value Write sets selected bits in DCH2DSA, read yields undefined value Write inverts selected bits in DCH2DSA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3214 BF88_3218 BF88_321C BF88_3220 DCH2SSACLR DCH2SSASET DCH2SSAINV DCH2DSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_3224 BF88_3228 BF88_322C BF88_3230 DCH2DSACLR DCH2DSASET DCH2DSAINV DCH2SSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSSIZ<7:0> Write clears selected bits in DCH2SSIZ, read yields undefined value Write sets selected bits in DCH2SSIZ, read yields undefined value Write inverts selected bits in DCH2SSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3234 BF88_3238 BF88_323C BF88_3240 DCH2SSIZCLR DCH2SSIZSET DCH2SSIZINV DCH2DSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits in DCH2DSIZ, read yields undefined value Write sets selected bits in DCH2DSIZ, read yields undefined value Write inverts selected bits in DCH2DSIZ, read yields undefined value BF88_3244 BF88_3248 BF88_324C Note 1: 2: DCH2DSIZCLR DCH2DSIZSET DCH2DSIZINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 65 PIC32MX FAMILY TABLE 5-8: Virtual Address(1) BF88_3250 DMA CHANNEL 2 SFR SUMMARY (CONTINUED) Name DCH2SPTR 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- -- -- Bit 30/22/14/6 -- -- -- -- -- Bit 29/21/13/5 -- -- -- -- -- Bit 28/20/12/4 -- -- -- -- -- Bit 27/19/11/3 -- -- -- -- -- Bit 26/18/10/2 -- -- -- -- -- Bit 25/17/9/1 -- -- -- -- -- Bit 24/16/8/0 -- -- -- -- -- CHSPTR<7:0> BF88_3260 DCH2DPTR 31:24 23:16 15:8 7:0 CHDPTR<15:8>(2) CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3270 DCH2CSIZ 31:24 23:16 15:8 7:0 CHCSIZ<7:0> Write clears selected bits in DCH2CSIZ, read yields undefined value Write sets selected bits in DCH2CSIZ, read yields undefined value Write inverts selected bits in DCH2CSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3274 BF88_3278 BF88_327C BF88_3280 DCH2CSIZCLR DCH2CSIZSET DCH2CSIZINV DCH2CPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHCPTR<7:0> BF88_3290 DCH2DAT 31:24 23:16 15:8 7:0 CHPDAT<7:0> Write clears selected bits in DCH2DAT, read yields undefined value Write sets selected bits in DCH2DAT, read yields undefined value Write inverts selected bits in DCH2DAT, read yields undefined value BF88_3294 BF88_3298 BF88_329C Note 1: 2: DCH2DATCLR DCH2DATSET DCH2DATINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. TABLE 5-9: Virtual Address BF88_1070 BF88_1040 BF88_1120 Note 1: DMA CHANNEL 2 INTERRUPT REGISTER SUMMARY(1) Name IEC1 IFS1 IPC9 23:16 23:16 23:16 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 DMA3IE DMA3IF DMA2IP<2:0> Bit 26/18/10/2 DMA2IE DMA2IF Bit 25/17/9/1 DMA1IE DMA1IF Bit 24/16/8/0 DMA0IE DMA0IF DMA2IS<1:0> This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers. DS61143A-page 66 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 5-10: Virtual Address(1) BF88_32A0 DMA CHANNEL 3 SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- -- CHEN Bit 30/22/14/6 -- -- -- CHAED Bit 29/21/13/5 -- -- -- CHCHN Bit 28/20/12/4 -- -- -- CHAEN Bit 27/19/11/3 -- -- -- CHXM Bit 26/18/10/2 -- -- -- CHEDET Bit 25/17/9/1 -- -- -- Bit 24/16/8/0 -- -- CHCHNS DCH3CON CHPRI<1:0> BF88_32A4 DCH3CONCLR BF88_32A8 BF88_32AC BF88_32B0 DCH3CONSET DCH3CONINV DCH3ECON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CFORCE -- Write clears selected bits in DCH3CON, read yields undefined value Write sets selected bits in DCH3CON, read yields undefined value Write inverts selected bits in DCH3CON, read yields undefined value -- -- -- -- -- -- -- CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN -- -- -- Write clears selected bits in DCH3ECON, read yields undefined value Write sets selected bits in DCH3ECON, read yields undefined value Write inverts selected bits in DCH3ECON, read yields undefined value -- CHSDIE -- CHSDIF -- CHSHIE -- CHSHIF -- CHDDIE -- CHDDIF -- CHDHIE -- CHDHIF -- CHBCIE -- CHBCIF -- CHCCIE -- CHCCIF -- CHTAIE -- CHTAIF -- CHERIE -- CHERIF BF88_32B4 DCH3ECONCLR BF88_32B8 DCH3ECONSET BF88_32BC DCH3ECONINV BF88_32C0 DCH3INT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_32C4 BF88_32C8 BF88_32CC BF88_32D0 DCH3INTCLR DCH3INTSET DCH3INTINV DCH3SSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in DCH3INT, read yields undefined value Write sets selected bits in DCH3INT, read yields undefined value Write inverts selected bits in DCH3INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits in DCH3SSA, read yields undefined value Write sets selected bits in DCH3SSA, read yields undefined value Write inverts selected bits in DCH3SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits in DCH3DSA, read yields undefined value Write sets selected bits in DCH3DSA, read yields undefined value Write inverts selected bits in DCH3DSA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_32D4 BF88_32D8 BF88_32DC BF88_32E0 DCH3SSACLR DCH3SSASET DCH3SSAINV DCH3DSA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_32E4 BF88_32E8 BF88_32EC BF88_32F0 DCH3DSACLR DCH3DSASET DCH3DSAINV DCH3SSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSSIZ<7:0> Write clears selected bits in DCH3SSIZ, read yields undefined value Write sets selected bits in DCH3SSIZ, read yields undefined value Write inverts selected bits in DCH3SSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_32F4 DCH3SSIZCLR BF88_32F8 BF88_32FC BF88_3300 DCH3SSIZSET DCH3SSIZINV DCH3DSIZ 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits in DCH3DSIZ, read yields undefined value Write sets selected bits in DCH3DSIZ, read yields undefined value Write inverts selected bits in DCH3DSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3304 BF88_3308 BF88_330C BF88_3310 DCH3DSIZCLR DCH3DSIZSET DCH3DSIZINV DCH3SPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHSPTR<7:0> Note 1: 2: The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 67 PIC32MX FAMILY TABLE 5-10: Virtual Address(1) BF88_3320 DMA CHANNEL 3 SFR SUMMARY (CONTINUED) Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- Bit 30/22/14/6 -- -- Bit 29/21/13/5 -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 -- -- Bit 26/18/10/2 -- -- Bit 25/17/9/1 -- -- Bit 24/16/8/0 -- -- DCH3DPTR CHDPTR<15:8>(2) CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3330 DCH3CSIZ 31:24 23:16 15:8 7:0 CHCSIZ<7:0> Write clears selected bits in DCH3CSIZ, read yields undefined value Write sets selected bits in DCH3CSIZ, read yields undefined value Write inverts selected bits in DCH3CSIZ, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_3334 BF88_3338 BF88_333C BF88_3340 DCH3CSIZCLR DCH3CSIZSET DCH3CSIZINV DCH3CPTR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CHCPTR<7:0> BF88_3350 DCH3DAT 31:24 23:16 15:8 7:0 CHPDAT<7:0> Write clears selected bits in DCH3DAT, read yields undefined value Write sets selected bits in DCH3DAT, read yields undefined value Write inverts selected bits in DCH3DAT, read yields undefined value BF88_3354 BF88_3358 BF88_335C Note 1: 2: DCH3DATCLR DCH3DATSET DCH3DATINV 31:0 31:0 31:0 The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n. These bits are relevant in Extended Addressing mode only. TABLE 5-11: Virtual Address BF88_1070 BF88_1040 BF88_1120 Note 1: DMA CHANNEL 3 INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC9 23:16 23:16 31:24 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 DMA3IE DMA3IF DMA3IP<2:0> Bit 26/18/10/2 DMA2IE DMA2IF Bit 25/17/9/1 DMA1IE DMA1IF Bit 24/16/8/0 DMA0IE DMA0IF DMA3IS<1:0> This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers. DS61143A-page 68 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 FRZ R/W-0 SIDL R/W-0 SUSPEND U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DMACON: DMA CONTROLLER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' ON: DMA On bit 1 = DMA module is enabled 0 = DMA module is disabled FRZ: DMA Freeze bit(1) 1 = DMA is frozen during Debug mode 0 = DMA continues to run during Debug mode Note: FRZ is writable in Debug Exception mode only, it is forced to `0' in Normal mode. SIDL: Stop in Idle Mode bit 1 = DMA transfers are frozen during Sleep 0 = DMA transfers continue during Sleep SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 69 PIC32MX FAMILY REGISTER 5-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-4 bit 3 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- R-0 RDWR U-0 -- R-0 R-0 bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DMASTAT: DMA STATUS REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 DMACH<1:0> Unimplemented: Read as `0' RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write Unimplemented: Read as `0' DMACH<1:0>: DMA Channel bits This register contains the value of the most recent active DMA channel. bit 2 bit 1-0 Note 1: DS61143A-page 70 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-3: R-0 bit 31 R-0 bit 23 R-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 Note 1: W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR: DMA ADDRESS REGISTER(1) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 24 R-0 bit 16 R-0 bit 8 DMAADDR<31:24> DMAADDR<23:16> DMAADDR<15:8> DMAADDR<7:0> DMAADDR<31:0>: DMA Module Address bits This register contains the address of the most recent DMA access. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 71 PIC32MX FAMILY REGISTER 5-4: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 CRCEN bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-13 bit 12-8 bit 7 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CRCAPP U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 PLEN<4:0> bit 8 R/W-0 bit 0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCRCCON: DMA CRC CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 CRCCH<1:0> Unimplemented: Read as `0' PLEN<4:0>: Polynomial Length bits Denotes the length of the polynomial -1. CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally CRCAPP: CRC Append Mode bit 1 = Data read will be passed to the CRC, to be included in the CRC calculation, but is not written to the destination register. When a block transfer completes, the calculated CRC will be written to the location given by DCHxDSA 0 = Channel behaves normally, with the CRC being calculated as data is transferred from the source to the destination Unimplemented: Read as `0' CRCCH<1:0>: CRC Channel Select bits 11 = CRC is assigned to Channel 3 10 = CRC is assigned to Channel 2 01 = CRC is assigned to Channel 1 00 = CRC is assigned to Channel 0 bit 6 bit 5-2 bit 1-0 DS61143A-page 72 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-5: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCRCDATA: DMA CRC DATA REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 DCRCDATA<15:8> DCRCDATA<7:0> Unimplemented: Read as `0' DCRCDATA<15:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits > PLEN will return `0' on any read. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 73 PIC32MX FAMILY REGISTER 5-6: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCRCXOR: DMA CRC XOR ENABLE REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 DCRCXOR<15:8> DCRCXOR<7:0> Unimplemented: Read as `0' DCRCXOR<15:0>: CRC XOR Register bits 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted directly in from the previous stage in the register The LSb of the DCRCXOR register will be always set. Note 1: DS61143A-page 74 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-7: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 CHEN bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-9 bit 8 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CHAED R/W-0 CHCHN R/W-0 CHAEN R/W-0 CHXM R-0 CHEDET R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXCON: DMA CHANNEL X CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 CHCHNS bit 8 R/W-0 bit 0 CHPRI<1:0> Unimplemented: Read as `0' CHCHNS: Chain Channel Selection bit 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) Note: The chain selection bit takes effect when chaining is enabled, i.e., CHCHN = 1. CHEN: Channel Enable bit 1 = Channel is enabled 0 = Channel is disabled CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained to channel higher in natural priority 0 = Do not chain to channel higher in natural priority CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete CHXM: Channel Extended Addressing Mode Enable bit 1 = Extended Addressing mode is enabled 0 = Extended Addressing mode is disabled CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 75 PIC32MX FAMILY REGISTER 5-8: U-0 -- bit 31 R/W-1 bit 23 R/W-1 bit 15 S-0 CFORCE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-24 bit 23-16 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) S-0 CABORT R/W-0 PATEN R/W-0 SIRQEN R/W-0 AIRQEN U-0 -- U-0 -- U-0 -- bit 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-1 bit 16 R/W-1 bit 8 CHAIRQ<7:0> CHSIRQ<7:0> Unimplemented: Read as `0' CHAIRQ<7:0>: IRQ that will abort Channel Transfer bits 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag *** 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag bit 15-8 CHSIRQ<7:0>: IRQ that will Start Channel Transfer bits 11111111 = Interrupt 255 will initiate a DMA transfer *** 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer bit 7 CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a `1' 0 = This bit always reads `0' CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a `1' 0 = This bit always reads `0' PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer bit 6 bit 5 bit 4 DS61143A-page 76 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-8: bit 3 DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER (CONTINUED) AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as `0' bit 2-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 77 PIC32MX FAMILY REGISTER 5-9: U-0 -- bit 31 R/W-0 CHSDIE bit 23 U-0 -- bit 15 R/W-0 CHSDIF bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-24 bit 23 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CHSHIF R/W-0 CHDDIF R/W-0 CHDHIF R/W-0 CHBCIF R/W-0 CHCCIF R/W-0 CHTAIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CHSHIE R/W-0 CHDDIE R/W-0 CHDHIE R/W-0 CHBCIE R/W-0 CHCCIE R/W-0 CHTAIE DCHXINT: DMA CHANNEL X INTERRUPT CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-0 CHERIE bit 16 U-0 -- bit 8 R/W-0 CHERIF bit 0 Unimplemented: Read as `0' CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as `0' bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15-8 DS61143A-page 78 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-9: bit 7 DCHXINT: DMA CHANNEL X INTERRUPT CONTROL REGISTER (CONTINUED) CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR == CHSSIZ) 0 = No interrupt is pending CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR == CHSSIZ/2) 0 = No interrupt is pending CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR == CHDSIZ) 0 = No interrupt is pending CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR == CHDSIZ/2) 0 = No interrupt is pending CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs 0 = No interrupt is pending CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected Either the source or the destination address is invalid. 0 = No interrupt is pending bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 79 PIC32MX FAMILY REGISTER 5-10: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DCHXSSA: DMA CHANNEL X SOURCE START ADDRESS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. DS61143A-page 80 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-11: R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DCHXDSA: DMA CHANNEL X DESTINATION START ADDRESS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 81 PIC32MX FAMILY REGISTER 5-12: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXSSIZ: DMA CHANNEL X SOURCE SIZE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-x bit 0 CHSSIZ<7:0> Unimplemented: Read as `0' CHSSIZ<7:0>: Channel Source Size bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): 255 = 255-byte source size *** 2 = 2-byte source size 1 = 1-byte source size 0 = 256-byte source size CHXM = 1 (DCHxCON<3>) (Extended Addressing mode): These bits make up the Most Significant bits of the transfer size. DS61143A-page 82 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-13: U-0 -- bit 31 U-0 -- bit 23 R-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R-x R-x R-x R-x R-x R-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXDSIZ: DMA CHANNEL X DESTINATION SIZE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-x bit 8 R/W-x bit 0 CHDSIZ<15:8> CHDSIZ<7:0> Unimplemented: Read as `0' CHDSIZ<15:0>: Channel Destination Size bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): CHDSIZ<15:8> Unused, read as `0', write has no effect. CHDSIZ<7:0> Read/Write Normal mode transfer size: 255 = 255-byte destination size *** 2 = 2-byte destination size 1 = 1-byte destination size 0 = 256-byte destination size CHXM = 1 (DCHxCON<3>) (Extended Addressing mode): CHDSIZ<15:0> Read Extended mode transfer size: 65535 = 65535-byte destination size *** 2 = 2-byte destination size 1 = 1-byte destination size 0 = 65536-byte destination size. CHDSIZ<15:8> write has no effect. CHDSIZ<7:0> write sets the LSB of Extended mode transfer size. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 83 PIC32MX FAMILY REGISTER 5-14: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXSPTR: DMA CHANNEL X SOURCE POINTER REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 CHSPTR<7:0> Unimplemented: Read as `0' CHSPTR<7:0>: Channel Source Pointer bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): 255 = Points to 255th byte of the source *** 1 = Points to 1st byte of the source 0 = Points to 0th byte of the source CHXM =1 (DCHxCON<3>) (Extended Addressing mode): These bits comprise the Most Significant bits of the pointer. Note: This is reset on pattern detect, when in Pattern Detect mode. DS61143A-page 84 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-15: U-0 -- bit 31 U-0 -- bit 23 R-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXDPTR: CHANNEL X DESTINATION POINTER REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 bit 8 CHDPTR<15:8> CHDPTR<7:0> Unimplemented: Read as `0' CHDPTR<15:0>: Channel Destination Pointer bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): CHDPTR<15:8> Unused, read as `0'. CHDPTR<7:0> Normal Mode Destination Pointer: 255 = Points to 255th byte of the destination *** 1 = Points to 1st byte of the destination 0 = Points to 0th byte of the destination CHXM = 1 (DCHxCON<3>) (Extended Addressing mode): CHDPTR<15:0> Extended Mode Destination Pointer: 65535 = Points to byte 65535 (0xFFFF) of the source/destination *** 255 = Points to byte 255 of the source/destination *** 1 = Points to byte 1 of the source/destination 0 = Points to byte 0 of the source/destination (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 85 PIC32MX FAMILY REGISTER 5-16: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXCSIZ: DMA CHANNEL X CELL-SIZE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-x bit 0 CHCSIZ<7:0> Unimplemented: Read as `0' CHCSIZ<7:0>: Channel Cell Size bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): 255 = 255 bytes transferred on an event *** 2 = 2 bytes transferred on an event 1 = 1 byte transferred on an event 0 = 256 bytes transferred on an event CHXM = 1 (DCHxCON<3>) (Extended Addressing mode): These bits are not used in Extended Addressing mode. DS61143A-page 86 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 5-17: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXCPTR: DMA CHANNEL X CELL POINTER REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 CHCPTR<7:0> Unimplemented: Read as `0' CHCPTR<7:0>: Channel Cell Progress Pointer bits CHXM = 0 (DCHxCON<3>) (Normal Addressing mode): 255 = 255 Bytes have been transferred since the last event *** 1 = 1 Bytes have been transferred since the last event 0 = 0 Bytes have been transferred since the last event CHXM = 1 (DCHxCON<3>) (Extended Addressing mode): These bits are not used in Extended Addressing mode. Note: This is reset on pattern detect, when in Pattern Detect mode (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 87 PIC32MX FAMILY REGISTER 5-18: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DCHXDAT: DMA CHANNEL X PATTERN DATA REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-x bit 0 CHPDAT<7:0> Unimplemented: Read as `0' CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused. DS61143A-page 88 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 5.2 DMA Controller Operation * A DMA channel will transfer data from a source to a destination without CPU intervention. DMA controller configuration resources: * The DMA Controller and the corresponding DMA channel have to be enabled using the ON (DMACON<15>) and the CHEN (DCHxCON<7>) bits. * The source and destination of the transfer are programmable using the DCHxSSA and DCHxDSA registers respectively. * The source and destination are further independently configurable using the DCHxSSIZ and DCHxDSIZ registers. * A DMA transfer can be initiated in one of two ways: - Software can initiate a transfer by setting the channel CFORCE (DCHxECON<7>) bit. - An interrupt event occurs that matches the CHSIRQ (DCHxECON<15:8>) interrupt and SIRQEN = 1 (DCHxECON<4>). The user can select any interrupt on the device to start a DMA transfer. * At each event requiring a DMA transfer, a number of bytes specified by the cell size (DCHxCSIZ) will be transferred (one or more transactions will occur). * The channel keeps track of the number of bytes transferred from the source to destination, using Source and Destination Pointers (DCHxSPTR and DCHxDPTR). * The Source and Destination Pointers are readonly and are updated after every transaction. * Interrupts are generated when the Source or Destination pointer is half of the source or destination size (DCHxSSIZ/2 or DCHxDSIZ/2), or when the source or destination counter equals the size of the source or destination. These interrupts are CHSHIF, CHDHIF and CHSDIF, CHDDIF, respectively. * The Source and Destination Pointers are reset: - On any device Reset. - When the DMA is turned off (ON bit (DMACON<15>) is `0'). - A block transfer completes (regardless of the state of CHAEN (DCHxCON<4>)). - A pattern match terminates a transfer (regardless of the state of auto-enable CHAEN (DCHxCON<4>)). - The CABORT (DCHxECON<6>) flag is written. - If the channel source address (DCHxSSA) is updated, the Source Pointer (DCHxSPTR) will be reset. - Similarly, updates to the Destination Address (DCHxDSA) will cause the Destination Pointer (DCHxDPTR) to be reset. Normally, the DMA channel remains enabled until the DMA channel has completed a block transfer unless the auto-enable feature is turned on (i.e., CHAEN = 1). When the channel is disabled, further transfers will be prohibited until the channel is re-enabled (CHEN is set to `1'). A DMA transfer request will be stopped/aborted by: - Writing the CABORT bit (DCHxECON<6>). - Pattern match occurs if pattern match is enabled PATEN = 1 (DCHxECON<5>), provided that channel CHAEN is not set. - Interrupt event occurs on the device that matches the CHAIRQ (DCHxECON<23:16>) interrupt if enabled by AIRQEN (DCHxECON<3>). - An address error is detected. - A block transfer completes provided that Channel Auto-Enable mode (CHAEN) is not set. When a channel abort interrupt occurs, the Channel Abort Interrupt Flag, CHTAIF, (DCHxINT<1>) is set. This allows the user to detect and recover from an aborted DMA transfer. When a transfer is aborted, any transaction currently underway will be completed. * * * 5.2.1 DMA CONTROLLER TERMINOLOGY Event: Any system event that can initiate or abort a DMA transfer. Transaction: A single-word transfer (up to 4 bytes), comprised of read and write operations. Cell Transfer: The number of bytes transferred when a DMA channel has a transfer initiated before waiting for another event (given by the DCHCSIZ register). A cell transfer comprises one or more transactions. Block Transfer: Defined as the number of bytes transferred when a channel is enabled. The number of bytes is the larger of either DCHxSSIZ or DCHxDSIZ. A block transfer comprises one or more cell transfers. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 89 PIC32MX FAMILY 5.3 Normal Addressing Mode The mode is enabled by clearing the CHXM bit (DCHxCON<3>). Normal Addressing mode transfer features: * In Normal Addressing mode, the transfer size is limited to a maximum of 256 bytes transferred per channel. * The Source and Destination Pointers wrap around based on the selected source and destination size. * A block transfer is complete when the block size bytes have been transferred. The block size is the larger of source and destination sizes: - blockSize = max (DCHxSSIZ, DCHxDSIZ). * A DMA event will transfer cell size (DCHxCSIZ) bytes from source to destination. However, if DCHxCSIZ is greater than the block size, then just block size bytes will be transferred. * If using interrupts: - Set the conditions that will generate an interrupt in the DCHxINT register (at least error interrupt enable and abort interrupt enable, usually block complete interrupt). - Set the DMA channel interrupt priority and subpriority in the INT controller. - Enable the DMA channel interrupt in the INT controller. * Enable the selected DMA channel with CHEN (DCHxCON<7>). * If not using system events to start the DMA transfer use CFORCE (DCHxECON<7>) to start transfer. * Until the DMA transfer is complete you can do some other processing. * If transfer complete interrupts (cell complete, block complete, etc.) are enabled, a notification will be presented in the ISR that the DMA transfer completed. * Otherwise, the DMA channel can be polled to see if the transfer is completed using, for example, CHBCIF (DCHxINT<3>). Refer to Example 5-1. 5.3.1 NORMAL ADDRESSING MODE TRANSFER CONFIGURATION Microchip recommends taking the following steps to configure a DMA transfer in Normal Addressing mode: * Disable the DMA channel interrupts in the INT controller. * Clear any existing channel interrupt flags in the INT controller. * Enable the DMA controller (if not already enabled) in DMACON register. * Set Channel Control register: Priority, Auto-Enable mode, etc., in DCHxCON. Use CHXM = 0 (DCHxCON<3>) for Normal Addressing mode. (Don't enable the channel yet!) * Set the channel event control: clear/set the events starting and aborting the transfer. If needed, also set the pattern match enable in DCHxECON. * If using a pattern match, set the pattern in the DCHxDAT register. * Set the transfer source and destination physical addresses (DCHxSSA and DCHxDSA registers). * Set the source and destination sizes (DCHxSSIZ, DCHxDSIZ registers). * Set the cell transfer size (DCHxCSIZ). * Clear any existing event flag in the DCHxINT register. DS61143A-page 90 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-1: CONFIGURING THE DMA FOR NORMAL ADDRESSING MODE OPERATION /* The following code example illustrates a DMA channel 0 configuration for a normal addressing transfer. */ IEC1CLR=0x00010000; // disable DMA channel 0 interrupts IFS1CLR=0x00010000; // clear existing DMA channel 0 interrupt flag DMACONSET=0x00008000; DCH0CON=0x3; CH0ECON=0; // enable the DMA controller // channel off, pri 3, normal mode, no chaining // no start or stop irq's, no pattern match // // // // // // program the transfer transfer source physical address transfer destination physical address source size 256 bytes destination size 256 bytes 256 bytes transferred per event DCH0SSA=0x1d010000; DCH0DSA=0x1d020000; DCH0SSIZ=0; DCH0DSIZ=0; DCH0CSIZ=0; DCH0INTCLR=0x00ff00ff; DCH0CONSET=0x80; // clear existing events, disable all interrupts // turn channel on // initiate a transfer // set CFORCE to 1 DCH0ECONSET=0x00000080; // do something else // poll to see that the transfer was done while(TRUE) { register int pollCnt; // use a poll counter. // polling continuously the DMA controller in a tight // loop would affect the performance of the DMA transfer int dmaFlags=DCH0INT; if( (dmaFlags&0xb) { break; } pollCnt=100; while(pollCnt--); } // one of CHERIF (DCHxINT<0>), CHTAIF (DCHxINT<1>) // or CHBCIF (DCHxINT<3>) flags set // transfer completed // use an adjusted value here // wait before reading again the DMA controller // check the transfer completion result (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 91 PIC32MX FAMILY 5.4 Extended Addressing Mode The mode is enabled by setting the CHXM bit (DCHxCON<3>) Extended Addressing mode transfer features: * The maximum transfer size per channel is 64 Kbytes. * The source and destination sizes are concatenated and the size is 16 bits wide. DCHxSSIZ will comprise the Most Significant bits of the channel transfer size, the Destination Size Register (DCHxDSIZ) will make up the Least Significant bits of the transfer size. * The Source and Destination Pointers (DCHxSPTR/DCHxDPTR) are concatenated in the same way as the source and destination sizes. A read of the DCHxDPTR register will return the full 16-bit Channel Transfer Pointer (DCHxSPTR concatenated with DCHxDPTR). A read of DCHxSPTR in this mode will return the high-order bits of the Transfer pointer. * Cell size is identical to block size. DCHxCSIZ and DCHxCPTR are not used. * Set the channel event control: clear/set the events starting and aborting the transfer. If needed, also set the pattern match enable in DCHxECON. * If using a pattern match, set the pattern in the DCHxDAT register. * Set the transfer source and destination physical addresses (DCHxSSA and DCHxDSA registers). * Set the block transfer size (DCHxSSIZ and DCHxDSIZ). * Clear any existing event flag in DCHxINT register. * If using interrupts: - Set the conditions that will generate an interrupt in the DCHxINT register (at least error interrupt enable and abort interrupt enable, usually block complete interrupt). - Set the DMA channel interrupt priority and subpriority in the INT controller. - Enable the DMA channel interrupt in the INT controller. * Enable the selected DMA channel with CHEN (DCHxCON<7>). * If not using system events to start the DMA transfer use CFORCE (DCHxECON<7>) to start transfer. * Until the DMA transfer is complete, you can do some other processing. * If you enabled block complete interrupt you'll be notified in the ISR that the DMA transfer completed. * Otherwise, you can poll the DMA channel to see if the transfer is completed using, for example, CHBCIF (DCHxINT<3>). Refer to Example 5-2. 5.4.1 EXTENDED ADDRESSING MODE CONFIGURATION The following steps are recommended to be taken to configure a DMA transfer in Extended Addressing mode: * Disable the DMA channel interrupts in the INT controller. * Clear any existing channel interrupt flags in the INT controller * Enable the DMA controller (if not already enabled) in DMACON register. * Set Channel Control register: Priority, Auto-Enable mode, etc., in DCHxCON. Use CHXM = 1 (DCHxCON<3>) for Extended Addressing mode. Don't enable the channel yet. DS61143A-page 92 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-2: CONFIGURING THE DMA FOR EXTENDED ADDRESSING MODE OPERATIONC /* The following code example illustrates a DMA channel 0 configuration for the extended addressing mode transfer. */ IEC1CLR=0x00010000; IFS1CLR=0x00010000; DMACONSET=0x00008000; DCH0CON=0xb; DCH0ECON=0; DCH0SSA=0x1d010000; DCH0DSA=0x1d020000; DCH0SSIZ=(BYTE)(1024>>8); DCH0DSIZ=(BYTE)1024; DCH0INTCLR=0x00ff00ff; DCH0CONSET=0x80; // disable DMA channel 0 interrupts // clear any existing DMA channel 0 interrupt flag // enable the DMA controller // channel off, priority 3, extended mode, no chaining // // // // // // no start or stop irq's, no pattern match program the transfer transfer source physical address transfer destination physical address set block size MSB in src size set block size LSB in dst size // clear existing events, disable all interrupts // turn channel on // initiate a transfer // set CFORCE to 1 DCH0ECONSET=0x00000080; // do something else // poll to see that the transfer was done while(TRUE) { register int pollCnt; // use a poll counter. // polling continuously the DMA controller in a tight // loop would affect the performance of the DMA transfer int dmaFlags=DCH0INT; if( (dmaFlags&0xb) { break; } pollCnt=100; while(pollCnt--); } // one of CHERIF (DCHxINT<0>), CHTAIF (DCHxINT<1>) // or CHBCIF (DCHxINT<3>) flags set // transfer completed // use an adjusted value here // wait before reading again the DMA controller // check the transfer completion result (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 93 PIC32MX FAMILY 5.5 Pattern Match Termination The Pattern Match mode is enabled by setting the PATEN bit (DCHxECON<5>). This feature is useful in applications where a variable data size is required and eases the setup of the DMA channel. A good usage is for transferring ASCII command strings from an UART, 5.5.1 PATTERN MATCH MODE CONFIGURATION The Pattern Match mode is an option for use when performing DMA transfers in Normal or Extended Addressing modes. Therefore, the steps needed in Pattern Match mode are identical to those used in Normal/Extended Addressing mode configuration. An extra step is needed to store the desired pattern in DCHxDAT register. The following steps are recommended to be taken to configure a DMA transfer in Pattern Match mode: * Disable the DMA channel interrupts in the INT controller. * Clear any existing channel interrupt flags in the INT controller. * Enable the DMA controller (if not already enabled) in DMACON register. * Set Channel Control register: Priority, Auto-Enable mode, etc., in DCHxCON. Use CHXM = 0/1 for Normal/Extended Addressing mode. Don't enable the channel yet. * Set the channel event control: clear/set the events starting and aborting the transfer. Set the pattern match enable PATEN in DCHxECON. * Set the pattern in the DCHxDAT register. * Set the transfer source and destination physical addresses (DCHxSSA and DCHxDSA registers). * If using Normal Addressing mode: - Set the source and destination sizes (DCHxSSIZ, DCHxDSIZ registers). - Set the cell transfer size (DCHxCSIZ). DS61143A-page 94 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-3: CONFIGURING THE DMA FOR PATTERN MATCH OPERATION /* The following code example illustrates a DMA channel 0 configuration for the normal addressing mode transfer with pattern match enabled. Transfer from the UART1 a DCH0SSA=VirtToPhys(&U1RXREG); DCH0DSA=0x1d020000; DCH0SSIZ=1; DCH0DSIZ=0; DCH0CSIZ=1; DCH0INTCLR=0x00ff00ff; DCH0INTSET=0x00090000; IPC9CLR=0x0000001f; IPC9SET=0x00000016; IEC1SET=0x00010000; DCH0CONSET=0x80; // clear existing events, disable all interrupts // enable Block Complete and error interrupts // clear the DMA channel 0 priority and subpriority // set IPL 5, subpriority 2 // enable DMA channel 0 interrupt // turn channel on // wait for an UART RX interrupt to initiate a transfer // do something else // will get an interrupt when the transfer is done // or when an address error occurred (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 95 PIC32MX FAMILY 5.6 Channel Chaining Mode 5.7 Channel Auto-Enable Mode The Chaining mode is enabled by setting the Chaining Enable it CHCEN bit (DCHxCON<5>) and Chaining Direction bit CHCHNS (DCHxCON<8>). Channel chaining is an enhancement to the DMA channel operation. A good usage is for transferring data packets from one peripheral to memory and then from memory to another peripheral. This module is also useful for implementing data acquisition in multiple buffers. Chaining mode features: * A channel (slave channel) can be chained to an adjacent channel (master channel). When the master channel completes a block transfer the slave channel will be enabled. * At this point, any event on the slave channel will initiate a cell transfer. If the channel has an event pending, a cell transfer will begin immediately. * Channels are chained in natural priority order where channel 0 has the highest priority and channel 3 the lowest. A specific channel can be enabled by an adjacent channel, either higher, or lower, in natural order, by configuring the CHCHNS (DCHxCON<8>) bit. Chaining must be enabled, CHCHN (DCHxCON<5>) = 1. * An important feature of the DMA controller is the ability to allow events while the channel is disabled using the CHAED (DCHxCON<6>) bit. This bit is particularly useful in Chained mode where the slave channel needs to be ready to start a transfer as soon as the channel is enabled by the master channel. The Auto-Enable mode is enabled by setting the CHAEN bit (DCHxCON<4>). Channel auto-enable function is an enhancement to the DMA channel operation. The channel auto-enable can be used to keep a channel active, even if a block transfer completes or a pattern match occurs. This prevents the user from having to re-enable the channel each time a block transfer completes. This mode is useful for applications that do repeated pattern matching. 5.7.1 AUTO-ENABLE MODE CONFIGURATION The Auto-Enable mode is an extra option for use when performing DMA transfers in Normal or Extended Addressing modes. Therefore, the steps needed in Auto-Enable mode are identical to those used in Normal/Extended Addressing mode configuration, with the following differences (refer to Section 5.3.1 "Normal Addressing Mode Transfer Configuration"): * The CHAEN bit has to be set before enabling the channel (setting the CHEN bit (DCHxCON<7>)). * The channel will behave as normal except that normal termination of a transfer will not result in the channel being disabled. * Normal block transfer completion is defined as: - block transfer complete - pattern match detect * As before, the Channel Pointers will be reset. 5.6.1 CHAINING MODE CONFIGURATION The Chaining mode is an option for use when performing DMA transfers in Normal or Extended Addressing modes. Therefore, the steps needed in Chaining mode are identical to those used in Normal/Extended Addressing mode configuration, with the following differences (refer to Section 5.3.1 "Normal Addressing Mode Transfer Configuration"): * Two diffferent channels have to be configured and the slave channel has to have chaining enable (CHCHN) and chaining direction (CHCHNS) set. Refer to Example 5-4. DS61143A-page 96 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-4: CONFIGURING THE DMA FOR CHAINING MODE OPERATION /* The following code example illustrates a DMA channel 0 configuration for the normal addressing mode transfer with pattern match enabled. DMA channel 0 transfer from the UART1 to a RAM buffer while DMA channel 1 transfers data from the RAM buffer to UART2. Transferred strings are at most 256 characters long. Transfer on UART2 will start as soon as the UART1 transfer is completed. */ unsigned char myBuff<256>;// transfer buffer IEC1CLR=0x00010000; IFS1CLR=0x00010000; DMACONSET=0x00008000; DCH0CON=0x3; DCH1CON=0x62; // disable DMA channel 0 interrupts // clear any existing DMA channel 0 interrupt flag // enable the DMA controller // // // // channel 0 off, priority 3, normal mode, no chaining channel 1 off, priority 2, normal mode, chain to higher priority (ch 0), enable events detection while disabled DCH0ECON=(27 <<8)| 0x30; DCH1ECON=(42 <<8)| 0x30; DCH0DAT=DCH1DAT='\r'; // start irq is UART1 RX, pattern enabled // start irq is UART1 TX, pattern enabled // pattern value, carriage return program channel 0 transfer // transfer source physical address transfer destination physical address source size is 1 byte dst size at most 256 bytes one byte per UART transfer request program channel 1 transfer transfer source physical address // transfer destination physical address source size at most 256 bytes dst size is 1 byte one byte per UART transfer request // DCH0SSA=VirtToPhys(&U1RXREG); DCH0DSA=VirtToPhys(myBuff); // DCH0SSIZ=1; // DCH0DSIZ=0; // DCH0CSIZ=1; // // DCH1SSA=VirtToPhys(myBuff); // DCH1DSA=VirtToPhys(&U2TXREG); DCH1SSIZ=0; // DCH1DSIZ=0; // DCH1CSIZ=1; // DCH0INTCLR=0x00ff00ff; DCH1INTCLR=0x00ff00ff; DCH1INTSET=0x00090000; // DMA0: clear events, disable interrupts // DMA1: clear events, disable interrupts // DMA1: enable Block Complete and error interrupts IPC9CLR=0x00001f1f; IPC9SET=0x00000b16; IEC1SET=0x00020000; DCH0CONSET=0x80; // do something else // // // // // clear the DMA channels 0 and 1 priority and subpriority set IPL 5, subpriority 2 for DMA channel 0 set IPL 2, subpriority 3 for DMA channel 1 enable DMA channel 1 interrupt // turn channel on // the UART1 RX interrupts will initiate the DMA channel 0 transfer // once this transfer is complete, the DMA channel 1 will start // upon DMA channel 1 transfer completion will get an interrupt while(!intCh1Ocurred); // poll DMA channel 1 interrupt (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 97 PIC32MX FAMILY 5.8 CRC Module Operation 5.9 CRC Background Mode The DMA module has one integrated CRC generation module shared by all channels. The CRC module is a highly configurable, 16-bit CRC generator. The CRC module can be assigned to any available DMA channel by setting the CRCCH bits (DCRCCON<1:0>) appropriately. The CRC is enabled by setting the CRCEN bit (DCRCCON<7>). The CRC generator will take 1 system clock to process each byte of data read from the source. This implies that if 32 bits of data are read from the source, the CRC generation will take 4 system clocks to process the data. The CRC module modifies the behavior of the DMA channel associated with the CRC module. The two operating modes for a DMA channel associated with the CRC module are: * Background Mode: CRC is calculated in the background, with normal DMA behavior maintained. * Append Mode: Data read from the source is not written to the destination, but the CRC data is accumulated in the CRC data register. The accumulated CRC is written to the destination address when a block transfer completes. CRC Configurable resources: * The terms of the polynomial can be programmed using the DCRCXOR<15:0> bits. Considering the CRC polynomial: x16 + x12 + x5 + 1, 17 bits are needed to define this polynomial. However, the value to be written to the DCRCXOR register will be 0b0001 0000 0010 0000, i.e., 0x1020. The LSb and MSb do not have to be specified, they are always set. The actual value used for the polynomial generator will be 0x11021. The length of the polynomial generator can be programmed using the PLEN (DCRCCON<12:8>) bits. For the above polynomial, the size will be 16. The PLEN will be programmed with length -1, i.e., 0x0F. The CRC module can be assigned to any available DMA channel by setting the CRCCH bits (DCRCCON<2:0>) appropriately. The CRC is enabled by setting the CRCEN bit (DCRCCON<7>). The CRC generator can be seeded by writing to the DCRCDATA register before enabling the channel that will use the CRC module. The CRC can be read as it progresses by reading the DCRCDATA register at any time during the CRC generation. Data Order: As data is read from the source register, the data is fed into the CRC generator MSB first. Note: The CRC Background mode is enabled by clearing CRCAPP (DCRCCON<6>). In this mode, the behavior of the DMA channel is maintained with data read from the channel source being passed to the CRC module and then written back to the destination. In the Background mode, the calculated CRC is left in the DCRCDATA register at the end of the block transfer. This mode can be used to calculate a CRC as data is moved from source to destination. A good example of where this can be used is to calculate a CRC as data is transmitted to or received from the UART module. When the data transfer is complete the user can read the calculated CRC and either append it to the transmitted data or verify the received CRC data. 5.9.1 CRC BACKGROUND MODE CONFIGURATION Microchip recommends taking the following steps to configure a CRC calculation in Background mode: * Seed the CRC generator by writing the initial seed to the DCRCDATA register. * Set the polynomial generator by writing to the DCRCXOR register. * Set the polynomial generator length by writing the PLEN (DCRCCON<12:8>). * Attach the CRC calculation to the desired DMA channel performing the Normal/Extended Addressing mode transfer by writing the CRCCH (DCRCCON<2:0>). * Use the Background mode by clearing the CRCAPP (DCRCCON<6>) bit. * Enable the CRC calculation by setting the CRCEN (DCRCCON<7>). * Once the DMA transfer begins, the CRC calculation will begin as well. * Once the DMA transfer ends, the CRC result will be available by reading the DCRCDATA register. Refer to Example 5-5.. Note: The configuration steps specific for the CRC configuration are shown. The DMA transfer configuration is the same as previously explained (see Section 5.2 "DMA Controller Operation"). * * * * * * DS61143A-page 98 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-5: CRC BACKGROUND MODE OPERATION /* The following code example illustrates a DMA calculation using the CRC background mode. Data is transferred from a 12K bytes Flash buffer to a RAM buffer and the CRC is calculated while the transfer takes place. */ unsigned int blockCrc; IEC1CLR=0x00010000; IFS1CLR=0x00010000; DMACONSET=0x00008000; DCRCDATA=0xffff; DCRCXOR=0x1021; DCRCCON=0x0f80; // CRC of the flash block // disable DMA channel 0 interrupts // clear any existing DMA channel 0 interrupt flag // enable the DMA controller // // // // seed the CRC generator Use the standard CCITT CRC 16 polynomial: X^16+X^12+X^5+1 CRC enabled, polynomial length 16, background mode CRC attached to the DMA channel 0. DCH0CON=0x0b; DCH0ECON=0; DCH0SSA=VirtToPhys(flashBuff); DCH0DSA=VirtToPhys(ramBuff); DCH0SSIZ=(BYTE)((12*1024)>>8); DCH0DSIZ=(BYTE)((12*1024)); DCH0INTCLR=0x00ff00ff; DCH0CONSET=0x80; DCH0ECONSET=0x00000080; // channel off, priority 3, extended mode, no chaining // no start irqs, no match enabled // // // // // program channel transfer transfer source physical address transfer destination physical address source size takes MSB dst size takes LSB // DMA0: clear events, disable interrupts // channel 0 on // initiate a transfer // set CFORCE to 1 // do something else while the transfer takes place // poll to see that the transfer was done BOOL error=FALSE; while(TRUE) { register int pollCnt; // don't poll in a tight loop int dmaFlags=DCH0INT; if( (dmaFlags& 0x3) { // CHERIF (DCHxINT<0>) or CHTAIF (DCHxINT<1> set error=TRUE; // error or aborted... break; } else if (dmaFlags&0x8) { // CHBCIF (DCHxINT<3>) set break; // transfer completed normally } pollCnt=100; // use an adjusted value here while(pollCnt--); // wait before polling again } if(!error) { blockCrc=DCRDATA; } else { } // read the CRC of the transferred flash block // process error (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 99 PIC32MX FAMILY 5.10 CRC Append Mode 5.10.1 The CRC Append mode is enabled by setting CRCAPP (DCRCCON<6>). In this mode, the behavior of the DMA channel is changed. Data read from the source will be fed into the CRC generation module. No data is written to the destination address in CRC Append mode until a block transfer completes or a pattern match occurs. On completion, the CRC value will be written to the address given by the Destination register (DCHxDSA). This mode can be used for the CRC calculation of a memory buffer, without actually performing a DMA transfer to a destination. CRC Append mode Features: * Only the source is considered when deciding if a block transfer is complete. * The destination address (DCHxDSA) is only used as the location to write the generated CRC to. * The destination size (DCHxDSIZ) can have a maximum size of 4. - If DCHxDSIZ is greater than 4, only 4 bytes are written at the end of the transfer. - If DCHxDSIZ is less than 4, only DCHxDSIZ bytes of the CRC are written to the destination address. - The high bytes (bits 31:16) are written as 0's if more than 16 bits of the CRC are written. - PLEN (CRCCON<12:8>) has no effect on the number of CRC bits that will be written to the Destination register. - When Extended Addressing mode is enabled, DCHxDSIZ forms part of the size of the data block to be transferred. DCHxDSIZ is not available to be used to limit number of bytes of the CRC to be stored and the entire 32-bit CRC will be written to DCHxDSA when a block transfer completes. * No CRC written back on an abort IRQ, user abort, bus error, etc. CRC APPEND MODE CONFIGURATION Microchip recommends taking the following steps to configure a CRC calculation in Background mode: * Seed the CRC generator by writing the initial seed to the DCRCDATA register. * Set the polynomial generator by writing to the DCRCXOR register. * Set the polynomial generator length by writing the PLEN (DCRCCON<12:8>). * Attach the CRC calculation to the desired DMA channel performing the Normal/Extended Addressing mode transfer by writing the CRCCH (DCRCCON<2:0>). * Use the Append mode by setting the CRCAPP (DCRCCON<6>) bit. * Enable the CRC calculation by setting the CRCEN (DCRCCON<7>). * Program the DMA transfer destination with the physical address of a variable where the CRC is to be stored. * Once the DMA transfer begins, the CRC calculation will begin as well. * Once the DMA transfer ends, the CRC result will be deposited at the programmed DMA destination address. Refer to Example 5-6. Note: The configuration steps specific for the CRC configuration are shown. The DMA transfer configuration is the same as previously explained (see Section 5.2 "DMA Controller Operation"). DS61143A-page 100 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-6: CRC APPEND MODE OPERATION /* The following code example illustrates a DMA calculation using the CRC append mode. The CRC of a 12K bytes flash buffer is calculated without performing any data transfer. As soon as the CRC calculation is completed the CRC value of the flash buffer is available in a local variable for further use. */ unsigned int blockCrc; IEC1CLR=0x00010000; IFS1CLR=0x00010000; DMACONSET=0x00008000; DCRCDATA=0xffff; DCRCXOR=0x1021; DCRCCON=0x0fc0; // CRC of the flash block // disable DMA channel 0 interrupts // clear any existing DMA channel 0 interrupt flag // enable the DMA controller // // // // seed the CRC generator Use the standard CCITT CRC 16 polynomial: X^16+X^12+X^5+1 CRC enabled, polynomial length 16, append mode CRC attached to the DMA channel 0. DCH0CON=0x0b; DCH0ECON=0; DCH0SSA=VirtToPhys(flashBuff); DCH0DSA=VirtToPhys(&blockCrc); DCH0SSIZ=(BYTE)((12*1024)>>8); DCH0DSIZ=(BYTE)((12*1024)); DCH0INTCLR=0x00ff00ff; DCH1INTCLR=0x00ff00ff; DCH0CONSET=0x80; DCH0ECONSET=0x00000080; // channel off, priority 3, extended mode, no chaining // no start irqs, no match enabled // // // // // program channel transfer transfer source physical address transfer destination physical address source size takes MSB dst size takes LSB // DMA0: clear events, disable interrupts // DMA1: clear events, disable interrupts // channel 0 on // initiate a transfer // set CFORCE to 1 // do something else while the CRC calculation takes place // poll to see that the transfer was done BOOL error=FALSE; while(TRUE) { register int pollCnt; // don't poll in a tight loop int dmaFlags=DCH0INT; if( (dmaFlags& 0x3) { // CHERIF (DCHxINT<0>) or CHTAIF (DCHxINT<1> set error=TRUE; // error or aborted... break; } else if (dmaFlags&0x8) { // CHBCIF (DCHxINT<3>) set break; // transfer completed normally } pollCnt=100; // use an adjusted value here while(pollCnt--); // wait before polling again } if(error) { // process error } // the block CRC is available in the blockCrc variable (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 101 PIC32MX FAMILY 5.11 DMA Interrupts The DMA device has the ability to generate interrupts reflecting the events that occurr during the channel's data transfer. The different kinds of DMA interrupt flags are: * CHERIF (DCHxINT<0>): Channel Error interrupts, enabled using CHERIE (DCHxINT<16>). * CHTAIF (DCHxINT<1>): Channel Abort interrupts, enabled using CHTAIE (DCHxINT<17>). * CHBCIF (DCHxINT<3>): Channel Block complete interrupts, enabled using CHBCIE (DCHxINT<19>). * CHCCIF (DCHxINT<2>): Channel Cell complete interrupts, enabled using CHCCIE (DCHxINT<18>). * CHSDIF (DCHxINT<7>): Channel Source pointer reached the end of the source, enabled by CHSDIE (DCHxINT<23>). * CHSHIF (DCHxINT<6>): Channel Source pointer reached midpoint of the source, enabled by CHSHIE (DCHxINT<22>). * CHDDIF (DCHxINT<5>): Channel Destination Pointer reached the end of the destination, enabled by CHDDIE (DCHxINT<21>) * CHDHIF (DCHxINT<4>): Channel Destination Pointer reached midpoint of the destination, enabled by CHDHIE (DCHxINT<20>). All the interrupts belonging to a DMA channel map to the corresponding channel interrupt vector. The corresponding interrupt flags are: * * * * DMA0IF (IFS1<16>) DMA1IF (IFS1<17>) DMA2IF (IFS1<18>) DMA3IF (IFS1<19>) All these interrupt flags must be cleared in software. A DMA channel is enabled as a source of interrupts via the respective DMA interrupt enable bits: * * * * DMA0IE (IEC1<16>) DMA1IE (IEC1<17>) DMA2IE (IEC1<18>) DMA3IE (IEC1<19>) The interrupt priority level bits and interrupt subpriority level bits must be also be configured: * DMA0IP<2:0> (IPC9<4:2>), DMA0IS<1:0> (IPC9<1:0>). * DMA1IP<2:0> (IPC9<12:10>), DMA1IS<1:0> (IPC9<9:8>). * DMA2IP<2:0> (IPC9<20:18>), DMA2IS<1:0> (IPC9<17:16>). * DMA3IP<2:0> (IPC9<28:26>), DMA3IS<1:0> (IPC9<25:24>). In addition to enabling the DMA interrupts, Interrupt Service Routines (ISRs) are required for each different interrupt vector used. See Example 5-7 and Example 5-8. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. DS61143A-page 102 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 5-7: DMA INITIALIZATION WITH INTERRUPTS /* The following code example illustrates a DMA channel 0 interrupt configuration. When the DMA channel 0 interrupt is generated, the CPU will jump to the vector assigned to DMA0 interrupt. */ IEC1CLR=0x00010000; IFS1CLR=0x00010000; DMACONSET=0x00008000; DCH0CON=0x03; DCH0ECON=0; // disable DMA channel 0 interrupts // clear any existing DMA channel 0 interrupt flag // enable the DMA controller // channel off, priority 3, normal mode, no chaining // no start or stop irq's, no pattern match // // // // // // program the transfer transfer source physical address transfer destination physical address source size 256 bytes destination size 256 bytes 256 bytes transferred pe event DCH0SSA=0x1d010000; DCH0DSA=0x1d020000; DCH0SSIZ=0; DCH0DSIZ=0; DCH0CSIZ=0; DCH0INTCLR=0x00ff00ff; DCH0INTSET=0x00090000; IPC9CLR=0x0000001f; IPC9SET=0x00000016; IEC1SET=0x00010000; DCH0CONSET=0x80; DCH0ECONSET=0x00000080; // do something else // clear existing events, disable all interrupts // enable Block Complete and error interrupts // clear the DMA channel 0 priority and subpriority // set IPL 5, subpriority 2 // enable DMA channel 0 interrupt // turn channel on // initiate a transfer // set CFORCE to 1 // will get an interrupt when the block transfer is done // or when error occurred EXAMPLE 5-8: DMA CHANNEL 0 ISR /* The following code example demonstrates a simple Interrupt Service Routine for DMA channel 0 interrupts. The user's code at this vector should perform any application specific operations and must clear the DMA0 interrupt flags before exiting. */ void __ISR(_DMA0_VECTOR, IPL5) __DMA0Interrupt(void) { int dmaFlags=DCH0INT&0xff; // read the interrupt flags // perform application specific operations in response to any interrupt flag set DCH0INTCLR=0x000000ff; IFS1CLR = 0x00010000; } // clear the DMA channel interrupt flags // Be sure to clear the DMA0 interrupt flags // before exiting the service routine. Note: The DMA ISR code example shows MPLAB(R) C32 C compiler specific syntax. Refer to your compiler manual regarding support for ISRs. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 103 PIC32MX FAMILY 5.12 I/O Pin Control The DMA controller module does not use any I/O pins. DS61143A-page 104 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 6.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 6.1 PIC32MX Memory Layout The PIC32MX microcontrollers provides 4 GB of unified virtual memory address space. All memory regions including program, data memory, SFRs, and Configuration registers reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX to execute from data memory. Key Features: * * * * * * * * 32-bit native data width Separate User and Kernel mode address space Flexible program Flash memory partitioning Flexible data RAM partitioning for data and program space Separate boot Flash memory for protected code Robust bus exception handling to intercept run-away code. Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable and non-cacheable address regions The PIC32MX microcontrollers implement two address spaces: Virtual and Physical. All hardware resources such as program memory, data memory and peripherals are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by peripherals such as DMA and Flash controller that access memory independently of CPU. The entire 4 GB virtual address space is divided into two primary regions - user and kernel space. The lower 2 GB of space forms the User mode segment, called useg/kuseg. The upper 2 GB of virtual address space forms the kernel-only space. The kernel space is divided into four segments of 512 MB each: kseg 0, kseg 1, kseg 2 and kseg 3. Only Kernel mode applications can access kernel space memory. The peripheral registers are only visible through kernel space. The Fixed Mapping Translation (FMT) unit translates the memory segments into corresponding physical address regions. A virtual memory segment may also be cached, provided the cache module is available on the device. Please note that the kseg 1 memory segment is not cacheable, while kseg 0 and useg/kuseg are cacheable. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 105 PIC32MX FAMILY FIGURE 6-1: VIRTUAL TO PHYSICAL FIXED MEMORY MAPPING Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF KSEG2/KSEG3 0xC0000000 Internal RAM (User Partition) Internal Boot Flash Internal Flash (User Partition) 0xBF000000 + BMXDUDBA 0xBFC00000 KSEG1 0xBF800000 0xBD000000 0xAFFFFFFF Internal Peripherals Internal Program Flash 0xBD000000 + BMXPUPBA 0x4FFFFFFF Reserved Internal RAM Reserved 0x40000000 0xA0000000 0x9FC00000 Internal Boot Flash KSEG0 0x9D000000 0x8FFFFFFF Internal Program Flash Reserved Internal RAM Internal Boot Flash 0x1FC00000 Internal RAM (User Partition) Internal Peripherals 0x80000000 USEG/KUSEG 0x7F000000 0x1F800000 0x7D000000+ BMXPUPBA 0x0FFFFFFF Program Flash (User Partition) Internal Program Flash 0x1D000000 0x0FFFFFFF BMXDUDBA Reserved Reserved Internal RAM 0x00000000 0x00000000 DS61143A-page 106 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 6.2 Virtual Address BF88_2000 Bus Matrix Registers BUS MATRIX REGISTER SUMMARY Name BMXCON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- -- -- Bit 30/22/14/6 -- -- -- BMXWSDRM Bit 29/21/13/5 -- -- -- -- Bit 28/20/12/4 -- Bit 27/19/11/3 -- Bit 26/18/10/2 BMXCHEDMA BMXERRDMA -- Bit 25/17/9/1 -- Bit 24/16/8/0 -- TABLE 6-1: BMXERRIXI BMXERRICD -- -- -- -- BMXERRDS BMXERRIS -- BMXARB<2:0> -- BF88_2004 BMXCONCLR BF88_2008 BMXCONSET BF88_200C BMXCONINV BF88_2010 BMXDKPBA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears selected bits in BMXCON, read yields undefined value Write sets selected bits in BMXCON, read yields undefined value Write inverts selected bits in BMXCON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- BMXDKPBA<15:8> BMXDKPBA<7:0> Write clears selected bits in BMXDKPBA, read yields undefined value Write sets selected bits in BMXDKPBA, read yields undefined value Write inverts selected bits in BMXDKPBA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_2014 BF88_2018 BF88_201C BF88_2020 BMXDKPBACLR BMXDKPBASET BMX DKPBAINV BMXDUDBA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BMXDUDBA<15:8> BMXDUDBA<7:0> Write clears selected bits in BMXDUDBA, read yields undefined value Write sets selected bits in BMXDUDBA, read yields undefined value Write inverts selected bits in BMXDUDBA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_2024 BF88_2028 BF88_202C BF88_2030 BMXDUDBACLR BMXDUDBASET BMXDUDBAINV BMX DUPBA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BMXDUPBA<15:8> BMXDUPBA<7:0> Write clears selected bits in BMXDUPBA, read yields undefined value Write sets selected bits in BMXDUPBA, read yields undefined value Write inverts selected bits in BMXDUPBA, read yields undefined value BMXDRMSZ<31:24> BMXDRMSZ<23:16> BMXDRMSZ<15:8> BMXDRMSZ<7:0> -- -- -- -- -- -- -- -- BMXPUPBA<15:8> BMXPUPBA<7:0> BMXPFMSZ<31:24> BMXPFMSZ<23:16> BMXPFMSZ<15:8> BMXPFMSZ<7:0> BMXBOOTSZ<31:24> BMXBOOTSZ<23:16> BMXBOOTSZ<15:8> BMXBOOTSZ<7:0> -- -- -- -- BMXPUPBA<19:16> BF88_2034 BF88_2038 BF88_203C BMX DUPBACLR BMX DUPBASET BMX DUPBAINV 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_2040 BMXDRMSZ BF88_2044 BMXPUPBA 31:24 23:16 15:8 7:0 BF88_2048 BMXPFMSZ 31:24 23:16 15:8 7:0 BF88_204C BMXBOOTSZ 31:24 23:16 15:8 7:0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 107 PIC32MX FAMILY REGISTER 6-1: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-27 bit 26 W = Writable bit n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 BMXWSDRM U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 BMXARB<2:0> bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 BMXERRIXI R/W-1 BMXERRICD R/W-1 BMXERRDMA R/W-1 BMXERRDS BMXCON: BUS MATRIX CONFIGURATION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 BMXCHEDMA U-0 -- U-0 -- bit 24 R/W-1 BMXERRIS bit 16 U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit 1 = Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled) 0 = Disable program Flash memory (data) cacheability for DMA accesses (hits are still read from the cache, but misses do not update the cache) Unimplemented: Read as `0' BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access BMXERRIS: Bus error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access Unimplemented: Read as `0' bit 25-21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15-7 DS61143A-page 108 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 6-1: bit 6 BMXCON: BUS MATRIX CONFIGURATION REGISTER (CONTINUED) BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup Unimplemented: Read as `0' BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111...011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 000 = Arbitration Mode 0 bit 5-3 bit 2-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 109 PIC32MX FAMILY REGISTER 6-2: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-11 bit 10-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 bit 8 BMXDKPBA<15:8> BMXDKPBA<7:0> Unimplemented: Read as `0' BMXDKPBA<15:11>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM BMXDKPBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments DS61143A-page 110 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 6-3: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-11 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 bit 8 BMXDUDBA<15:8> BMXDUDBA<7:0> Unimplemented: Read as `0' BMXDUDBA<15:11>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM Note: If non-zero, the value must be greater than BMXDKPBA. BMXDUDBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments bit 10-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 111 PIC32MX FAMILY REGISTER 6-4: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-11 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 bit 8 BMXDUPBA<15:8> BMXDUPBA<7:0> Unimplemented: Read as `0' BMXDUPBA<15:11>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM Note: If non-zero, BMXDUPBA must be greater than BMXDUDBA. BMXDUPBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments bit 10-0 DS61143A-page 112 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 6-5: R bit 31 R bit 23 R bit 15 R bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R R R R R R R bit 0 R R R R R R R bit 8 R R R R R R R bit 16 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R R R R bit 24 BMXDRMSZ<31:24> BMXDRMSZ<23:16> BMXDRMSZ<15:8> BMXDRMSZ<7:0> BMXDRMSZ: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: .......0x00002000 = device has 8 KB RAM 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 113 PIC32MX FAMILY REGISTER 6-6: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-20 bit 19-11 bit 10-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-0 bit 16 R-0 bit 8 BMXPUPBA<19:16> BMXPUPBA<15:8> BMXPUPBA<7:0> Unimplemented: Read as `0' BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits When non-zero, this value selects the PFM relative base address for User mode program space. BMXPUPBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments DS61143A-page 114 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 6-7: R bit 31 R bit 23 R bit 15 R bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R R R R R R R bit 0 R R R R R R R bit 8 R R R R R R R bit 16 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER R R R R R R R bit 24 BMXPFMSZ<31:24> BMXPFMSZ<23:16> BMXPFMSZ<15:8> BMXPFMSZ<7:0> BMXPFMSZ: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00008000 = device has 32 KB Flash 0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash 0x00040000 = device has 256 KB Flash 0x00080000 = device has 512 KB Flash (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 115 PIC32MX FAMILY REGISTER 6-8: R bit 31 R bit 23 R bit 15 R bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R R R R R R R bit 0 R R R R R R R bit 8 R R R R R R R bit 16 BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER R R R R R R R bit 24 BMXBOOTSZ<31:24> BMXBOOTSZ<23:16> BMXBOOTSZ<15:8> BMXBOOTSZ<7:0> BMXBOOTSZ: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00003000 = device has 12 KB boot Flash DS61143A-page 116 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 6.3 User and Kernel Memory Areas There are two modes of operation of the PIC32MX core: User mode and Kernel mode. To support these modes, the virtual address space is also divided into two segments, kernel segments and user segments. The lower 2 GBytes of virtual addresses form the User mode partition, and the upper 2 GBytes forms the Kernel mode partition. Most application will run only in Kernel mode. For these applications, the entire program can reside in the kernel address space providing full access to all resources. FIGURE 6-2: USER/KERNEL ADDRESS SEGMENTS 0xFFFFFFFF KERNEL SEGMENTS (KSEG 0,1,2,3) 0x80000000 0x7FFFFFFF USER / KERNEL SEGMENT (USEG / KUSEG) 0x00000000 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 117 PIC32MX FAMILY 6.4 PIC32MX Address Map 6.4.1 PHYSICAL MEMORY ADDRESS Table 6-2 shows the address map of the PIC32MX microcontroller. On reset, the PIC32MX starts executing code from 0xBFC0_0000 virtual address which reside in the kseg1 segment (non cacheable segment). The Kernel Program Flash address space starts at physical address 0x1D000000, whereas the user program flash space starts at physical address 0xBD000000 + BMXPUPBA register value. Similarly, the internal RAM is also divided into Kernel and User partitions. The kernal RAM space starts at physical address 0x00000000, whereas the User RAM space starts at physical address 0xBF000000 + BMXDUDBA register value. By default the entire Flash memory and RAM are mapped to the Kernel mode application only. TABLE 6-2: PIC32MX ADDRESS MAP Virtual Addresses Physical Addresses Begin Address 0x1FC00000 0x1D000000 0x1D000000 0x00000000 BMXDKPBA 0x1F800000 0xBD000000 + BMXPUPBA 0xBF000000 + BMXDUDBA 0xBF000000 + BMXDUPBA End Address 0x1FC02FFF 0x1D00000 + BMXPUPBA - 1 0x1D000000 + BMXPUPBA - 1 BMXDKPBA - 1 BMXDUDBA -1 0x1F8FFFFF 0xBD000000 + PFM Size - 1 0xBF000000 + BMXDUPBA - 1 0xBF000000 + RAM Size(3) - 1 Size in Bytes Calculation 12 KB BMXPUPBA BMXPUPBA BMXDKPBA BMXDUDBA BMXDKPBA 1 MB PFM Size BMXPUPBA BMXDUPBA BMXDUDBA DRM Size BMXDUPBA Memory Type Begin Address Boot Flash Kernel Address Space Program Flash(1) Program Flash(2) RAM (Data) RAM (Prog) Peripheral User Address Space Program Flash RAM (Data) RAM (Prog) 0xBFC00000 0xBD000000 0x9D000000 0x80000000 0x80000000 + BMXDKPBA 0xBF800000 0x7D000000 + BMXPUPBA 0x7F000000 + BMXDUDBA 0x7F000000 + BMXDUPBA End Address 0xBFC02FFF 0xBD000000 + BMXPUPBA - 1 0x9D000000 + BMXPUPBA - 1 0x80000000 + BMXDKPBA - 1 0x80000000 + BMXDUDBA -1 0xBF8FFFFF 0x7D000000 + PFM Size - 1 0x7F000000 + BMXDUPBA - 1 0x7F000000 + RAM Size(3) - 1 Note 1: 2: 3: Program Flash virtual addresses in the non-cacheable range (KSEG1). Program Flash virtual addresses in the cacheable and prefetchable range (KSEG0). The RAM size varies between PIC32MX device family members. DS61143A-page 118 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 6.5 Program Flash Memory Wait States 6.6 Program Flash Memory Partitioning For optimal performance, PFMWS(CHECON<2:0>) must be programmed to the minimum value possible. There are two parameters that determine this value: Flash Access Time - 50 nSec for the PIC32MX processor family. CPU Core frequency - The Core frequency is programmable. Care must be taken when changing frequencies to make sure that there are enough wait states to prevent any Flash memory access timing violations. To find out the number of flash wait states required, divide the core clock frequency (in MHz) by 20 and take the integer part of the result. The value that is written to PFMWS (CHECON<2:0>) is one less. For example, core clock frequency is 72MHZ. The number of wait states will be 72 / 20 = 3.6, i.e., 3 wait states. Therefore the actual value written to PFMWS bits will be 2. The Program Flash Memory can be partitioned for User and Kernel mode programs as shown in Figure 6-3. At Reset, the User mode partition does not exist (BMXPUPBA is initialized to `0'). The entire Program Flash Memory is mapped to Kernel mode program space starting at virtual address KSEG1: 0xBD000000 (or KSEG0: 0x9D000000). To set up a partition for the User mode program, initialize BMXPUPBA as follows: BMXPUPBA = BMXPFMSZ - USER_FLASH_PGM_SZ The USER_FLASH_PGM_SZ is the partition size of the User mode program. BMXPFMSZ is the bus matrix register that holds the total size of Program Flash Memory. Example: Assuming the PIC32MX device has 512 Kbytes of Flash memory, the BMXPFMSZ will contain 0x00080000. To create a user Flash program partition of 20 Kbytes (0x5000): BMXPUPBA = 0x80000 - 0x5000 = 0x7B000 The size of the user Flash will be 20K and the size left for the kernel Flash will be 512k - 20k = 492K. The user Flash partition will extend from 0x7D07B000 to 0x7d07FFFF (virtual addresses). The Kernel mode partition always starts from KSEG1: 0xBD000000 or KSEG0: 0x9D000000. In the above example, the kernel partition will extend from 0xBD000000 to 0xBD07AFFF (492 Kbytes in size). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 119 PIC32MX FAMILY FIGURE 6-3: FLASH PARTITIONING Virtual Address Physical Address KSEG0: 0x9D000000 +BMXPUPBA KSEG1: 0xBD000000 +BMXPUPBA Kernel Flash Size(1) Flash Partition for Kernel Program (KSEG 0/1) 0x1D000000 KSEG0: 0x9D000000 KSEG1: 0xBD000000 User Flash Size(2) 0x7D000000+ BMXPUPBA Optional Flash Partition for User Program (USEG/KUSEG) 0xBD000000+ BMXPUPBA 0x00000000 Note 1: 2: 3: Kernel Flash Size = BMXPUPBA User Flash Size = BMXPFMSZ-BMXPUPBA If BMXPUPBA is `0', then: K Flash Size = BMXPFMSZ (i.e., all the Flash) Usr Flash Size = 0 6.6.1 RAM PARTITIONING The RAM memory can be divided into 4 partitions. These are: 1. 2. 3. 4. Kernel Data Kernel Program User Data User Program In order to execute from data RAM, a kernel or user program partition must be defined. At Power-on Reset, the entire data RAM is assigned to the kernel data partition. This partition always starts from the base of the data RAM. See Figure 6-4 for details. The registers controlling the RAM partitions are BMXDKPBA, BMXDUDBA, and BMXDUPBA. For a detailed discussion on how to use these registers for partitioning the RAM, please refer to the Memory Organization chapter of PIC32MX Family Reference Manual (DS61132). DS61143A-page 120 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 6-4: RAM PARTITIONING Virtual Address Physical Address KSEG0: 0x80000000 +BMXDUDBA KSEG1: 0xA0000000 +BMXDUDBA 0x00000000 +BMXDUDBA Optional Kernel Program Partition KSEG 0/1 0x00000000 +BMXDKPBA Kernel Data Partition KSEG 0/1 0x00000000 Kernel Program Kernel Data RAM Size(2) RAM Size(1) KSEG0: 0x80000000 +BMXDKPBA KSEG1: 0xA0000000 +BMXDKPBA KSEG0: 0x80000000 KSEG1: 0xA0000000 User Program User Data RAM Size(4) RAM Size(3) Optional User Program RAM Partition (USEG/KUSEG) 0x7F000000 +BMXDUPBA Optional User RAM Partition (USEG/KUSEG) 0x7F000000 +BMXDUDBA 0x00000000 0xBF000000 +BMXDUDBA 0xBF000000 +BMXDUPBA Note 1: 2: 3: 4: 5: Kernel Data RAM Size = BMXDKPBA Kernel Program RAM Size = BMXDUDBA - BMXDKPBA User Data RAM Size = BMXDUPBA - BMXDUDBA User Program RAM Size = DRM Size - BMXDUPBA If BMXDKPBA, BMXDUDBA or BMXDUPBA is `0', then: Kernel Data RAM Size = BMXDRMSZ (i.e., all RAM) Kernel Program RAM Size = 0 User Data RAM Size = 0 User Program RAM Size = 0 6.6.2 ADDRESS DECODE Table 6-3 shows the address map for system resources available to the CPU when it is operating in either User mode or Kernel mode. Table 6-4 shows the address map for system resources mapped in KSEG0 that are available to the CPU when it is operating in Kernel mode. Table 6-5 shows the address map for system resources mapped in KSEG1 that are available to the CPU when it is operating in Kernel mode. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 121 PIC32MX FAMILY TABLE 6-3: Virtual Address 0x0000_0000 0x7D00_0000 + BMXPUPBA - 1 0x7D00_0000 + BMXPUPBA 0x7D00_7FFF 0x7D00_FFFF 0x7D01_FFFF 0x7D03_FFFF 0x7D07_FFFF 0x7D08_0000 0x7D08_0000 + BMXDUPBA - 1 0x7F00_0000 + BMXDUDBA 0x7F00_0000 + BMXDUPBA - 1 0x7F00_0000 + BMXDUPBA 0x7F00_1FFF 0x7F00_3FFF 0x7F00_7FFF 0x7F0_8000 0x7FFF_FFFF USEG/KUSEG ADDRESS MAP Physical Address 0x4000_0000 0xBD00_0000 + BMXPUPBA - 1 0xBD00_0000 + BMXPUPBA 0xBD00_7FFF RSVD 0xBD00_FFFF RSVD 0xBD01_FFFF RSVD 0xBD03_FFFF RSVD 0xBD07_FFFF 0xBD08_0000 0xBD08_0000 + BMXDUPBA - 1 0xBF00_0000 + BMXDUDBA 0xBF00_0000 + BMXDUPBA - 1 0xBF00_0000 + BMXDUPBA 0xBF00_1FFF 0xBF00_3FFF 0xBF00_7FFF 0xBF0_8000 0xBFFF_FFFF DRM User Program DRM=8KB RSVD DRM=16KB RSVD DRM=32KB RSVD DRM=32KB RSVD DRM=32KB RSVD DRM=16KB DRM=16KB DRM User Program DRM=8KB DRM User Program DRM User Program DRM User Program DRM User Data DRM User Data DRM User Data DRM User Data DRM User Data RSVD PFM User Program PFM User Program PFM User Program PFM User Program PFM User Program PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF 032x 064x 128x 256x 512x RSVD RSVD RSVD RSVD RSVD DS61143A-page 122 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 6-4: Virtual Address 0x8000_0000 0x8000_0000 + BMXDKPBA - 1 0x8000_0000 + BMXDKBPA 0x8000_0000 + BMXDUDBA - 1 KSEG0 ADDRESS MAP Physical Address 0x0000_0000 0x0000_0000 + BMXDKPBA - 1 0x0000_0000 + BMXDKBPA 0x0000_0000 + BMXDUDBA - 1 Note 1 Note 1 Note 1 Note 1 Note 1 DRM Kernel Program DRM Kernel Program DRM Kernel Program DRM Kernel Program DRM Kernel Program PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF 032x 064x 128x 256x 512x DRM Kernel Data DRM Kernel Data DRM Kernel Data DRM Kernel Data DRM Kernel Data 0x8000_1FFF 0x8000_3FFF 0x8000_7FFF 0x9CFF_FFFF 0x9D00_0000 0x9D00_0000 + BMXPUPBA - 1 0x9D00_7FFF 0x9D00_FFFF 0x9D01_FFFF 0x9D03_FFFF 0x9D07_FFFF 0x9D08_0000 0x9FBF_FFFF 0x9FC0_0000 0x9FC0_2FFF 0x9FC0_3000 0x9FFF_EFFF 0x9FFF_F000 0x9FFF_FFFF 0x0000_1FFF 0x0000_3FFF 0x0000_7FFF 0x1CFF_FFFF 0x1D00_0000 0x1D00_0000 + BMXPUPBA - 1 DRM=8KB RSVD DRM=8KB DRM=16KB RSVD DRM=32KB RSVD DRM=32KB RSVD PFM Kernel Program DRM=32KB RSVD PFM Kernel Program DRM=16KB DRM=16KB PFM Kernel Program PFM Kernel Program PFM Kernel Program Note 2 0x1D00_7FFF RSVD 0x1D00_FFFF Note 2 Note 2 Note 2 Note 2 RSVD 0x1D01_FFFF RSVD 0x1D03_FFFF RSVD 0x1D07_FFFF 0x1D08_0000 0x1FBF_FFFF 0x1FC0_0000 0x1FC0_2FFF 0x1FC0_3000 0x1FFF_EFFF 0x1FFF_F000 0x1FFF_FFFF Test Flash Test Flash Test Flash Test Flash Test Flash RSVD RSVD RSVD RSVD RSVD Boot Flash Boot Flash Boot Flash Boot Flash Boot Flash RSVD Note 1: Not available in KSEG0 if mapped to USEG/KUSEG (i.e. BMXDUDBA or BMXDUPBA non-zero). 2: Not available in KSEG0 if mapped in USEG/KUSEG (i.e. BMXPUPBA non-zero). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 123 PIC32MX FAMILY TABLE 6-5: Virtual Address 0xA000_0000 0xA000_0000 + BMXDKPBA - 1 0xA000_0000 + BMXDKBPA 0xA000_0000 + BMXDUDBA - 1 KSEG1 ADDRESS MAP Physical Address 0x0000_0000 0x0000_0000 + BMXDKPBA - 1 0x0000_0000 + BMXDKBPA 0x0000_0000 + BMXDUDBA - 1 Note 1 Note 1 Note 1 Note 1 Note 1 DRM Kernel Program PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF PIC32MX3XXF 032x 064x 128x 256x 512x DRM Kernel Data DRM Kernel Data DRM Kernel Data DRM Kernel Data DRM Kernel Data DRM Kernel Program DRM Kernel Program DRM Kernel Program DRM Kernel Program 0xA000_1FFF 0xA000_3FFF 0xA000_7FFF 0xA000_8000 0xBCFF_FFFF 0xBD00_0000 0xBD00_0000 + BMXPUPBA - 1 0xBD00_0000 + BMXPUPBA 0xBD00_7FFF 0xBD00_FFFF 0xBD01_FFFF 0xBD03_FFFF 0xBD07_FFFF 0xBD08_0000 0xBF7F_FFFF 0xBF80_0000 0xBF8F_FFFF 0xBF90_0000 0xBFB_FFFF 0xBFC0_0000 0xBFC0_2FFF 0xBFC0_3000 0xBFFF_EFFF 0xBFFF_F000 0x0000_1FFF 0x0000_3FFF 0x0000_7FFF 0x0000_8000 0x1CFF_FFFF 0x1D00_0000 0x1D00_0000 + BMXPUPBA - 1 0x1D00_0000 + BMXPUPBA 0x1D00_7FFF DRM=8KB RSVD DRM=8KB DRM=16KB RSVD DRM=32KB RSVD DRM=32KB RSVD PFM Kernel Program DRM=16KB DRM=16KB DRM=32KB RSVD PFM Kernel Program PFM Kernel Program PFM Kernel Program PFM Kernel Program Note 2 Note 2 Note 2 Note 2 Note 2 RSVD 0x1D00_FFFF RSVD 0x1D01_FFFF RSVD 0x1D03_FFFF RSVD 0x1D07_FFFF 0x1D08_0000 0x1F7F_FFFF 0x1F80_0000 0x1F8F_FFFF 0x1F90_0000 0x1FB_FFFF 0x1FC0_0000 0x1FC0_2FFF 0x1FC0_3000 0x1FFF_EFFF 0x1FFF_F000 Test Flash Test Flash Test Flash Test Flash Test Flash RSVD RSVD RSVD RSVD RSVD Boot Flash Boot Flash Boot Flash Boot Flash Boot Flash RSVD RSVD RSVD RSVD RSVD Peripherals Peripherals Peripherals Peripherals Peripherals RSVD 0xBFFF_FFFF 0x1FFF_FFFF Note 1: Not available in KSEG1 if mapped to USEG/KUSEG (i.e. BMXDUDBA or BMXDUPBA non-zero). 2: Not available in KSEG1 if mapped in USEG/KUSEG (i.e. BMXPUPBA non-zero). DS61143A-page 124 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 6.6.3 PERIPHERAL REGISTERS LOCATIONS Table 6-6 contains the peripheral address map for the PIC32MX device. Peripherals located on the PB Bus are mapped to 512 byte boundaries. Peripherals on the FPB Bus are mapped to 4 Kbyte boundaries. TABLE 6-6: Peripheral WDT RTCC TMR1 TMR2 TMR3 TMR4 TMR5 Input Capture1 Input Capture2 Input Capture3 Input Capture4 Input Capture5 Output Compare1 Output Compare2 Output Compare3 Output Compare4 Output Compare5 I2C1 I2C2 SPI1 SPI2 UART1 UART2 Parallel Master Port GPIO ADC PERIPHERAL ADDRESS TABLE Virtual Address Start BF80_0000 BF80_0200 BF80_0600 BF80_0800 BF80_0A00 BF80_0C00 BF80_0E00 BF80_2000 BF80_2200 BF80_2400 BF80_2600 BF80_2800 BF80_3000 BF80_3200 BF80_3400 BF80_3600 BF80_3800 BF80_5000 BF80_5200 BF80_5800 BF80_5A00 BF80_6000 BF80_6200 BF80_7000 BF80_8000 BF80_9000 BF80_9800 BF80_A000 BF80_F000 BF80_F200 BF80_F400 BF80_F600 BF88_1000 BF88_2000 BF88_3000 BF88_4000 BF88_6000 Physical Address End Start 1F80_0000 1F80_0200 1F80_0600 1F80_0800 1F80_0A00 1F80_0C00 1F80_0E00 1F80_2000 1F80_2200 1F80_2400 1F80_2600 1F80_2800 1F80_3000 1F80_3200 1F80_3400 1F80_3600 1F80_3800 1F80_5000 1F80_5200 1F80_5800 1F80_5A00 1F80_6000 1F80_6200 1F80_7000 1F80_8000 1F80_9000 1F80_9800 1F80_A000 1F80_F000 1F80_F200 1F80_F400 1F80_F600 1F88_1000 1F88_2000 1F88_3000 1F88_4000 1F88_6000 End 1F80_01FF 1F80_03FF 1F80_07FF 1F80_09FF 1F80_0BFF 1F80_0DFF 1F80_0FFF 1F80_21FF 1F80_23FF 1F80_25FF 1F80_27FF 1F80_29FF 1F80_31FF 1F80_33FF 1F80_35FF 1F80_37FF 1F80_39FF 1F80_51FF 1F80_53FF 1F80_59FF 1F80_5BFF 1F80_61FF 1F80_63FF 1F80_71FF 1F80_81FF 1F80_91FF 1F80_99FF 1F80_A1FF 1F80_F1FF 1F80_F3FF 1F80_F5FF 1F80_F7FF 1F88_1FFF 1F88_2FFF 1F88_3FFF 1F88_4FFF 1F88_61FF BF80_01FF BF80_03FF BF80_07FF BF80_09FF BF80_0BFF BF80_0DFF BF80_0FFF BF80_21FF BF80_23FF BF80_25FF BF80_27FF BF80_29FF BF80_31FF BF80_33FF BF80_35FF BF80_37FF BF80_39FF BF80_51FF BF80_53FF BF80_59FF BF80_5BFF BF80_61FF BF80_63FF BF80_71FF BF80_81FF BF80_91FF BF80_99FF BF80_A1FF BF80_F1FF BF80_F3FF BF80_F5FF BF80_F7FF BF88_1FFF BF88_2FFF BF88_3FFF BF88_4FFF BF88_61FF Comparator Voltage REF Comparator Oscillator Configuration Flash (NVM) Reset Interrupts Bus Matrix DMA Prefetch Cache GPIO (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 125 PIC32MX FAMILY NOTES: DS61143A-page 126 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 7.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The PIC32MX Family of devices contain internal program Flash memory for executing user code. There are three methods by which the user can program this memory: 1. 2. 3. Run-Time Self Programming (RTSP) In-Circuit Serial ProgrammingTM (ICSPTM) EJTAG Programming RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the "PIC32MX Programming Specification" (DS61145) document, which may be downloaded from the Microchip web site. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 127 PIC32MX FAMILY 7.1 FLASH Controller Registers FLASH CONTROLLER SFR SUMMARY Name NVMCON 31:24 23:16 15:8 7:0 BF80_F404 BF80_F408 BF80_F40C BF80_F410 NVMCONCLR NVMCONSET NVMCONINV NVMKEY 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_F420 NVMADDR 31:24 23:16 15:8 7:0 BF80_F424 BF80_F428 BF80_F42C BF80_F430 NVMADDRCLR NVMADDRSET NVMADDR INV NVMDATA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_F440 NVMSRCADDR 31:24 23:16 15:8 7:0 TABLE 7-1: Virtual Address BF80_F400 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- NVMWR -- -- -- -- -- -- -- -- -- LVDERR -- -- -- LVDSTAT -- -- -- -- -- -- Bit 24/16/8/0 -- -- -- NVMWREN NVMERR NVMOP<3:0> Write clears selected bits in NVMCON, read yields undefined value Write sets selected bits in NVMCON, read yields undefined value Write inverts selected bits in NVMCON, read yields undefined value NVMKEY<31:24> NVMKEY<23:16> NVMKEY<15:8> NVMKEY<7:0> NVMADDR<31:24> NVMADDR<23:16> NVMADDR<15:8> NVMADDR<7:0> Write clears selected bits in NVMADDR, read yields undefined value Write sets selected bits in NVMADDR, read yields undefined value Write inverts selected bits in NVMADDR, read yields undefined value NVMDATA<31:24> NVMDATA<23:16> NVMDATA<15:8> NVMDATA<7:0> NVMSRCADDR<31:24> NVMSRCADDR<23:16> NVMSRCADDR<15:8> NVMSRCADDR<7:0> TABLE 7-2: Virtual Address BF88_1050 BF88_1020 BF88_1120 FLASH CONTROLLER INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC11 31:24 31:24 7:0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- -- -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> -- -- -- -- Bit 24/16/8/0 FCEIE FCEIF FCEIS<1:0> Note: This summary table contains partial register definitions that only pertain to the FLASH memory controller peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A-page 128 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 7-1: U-0 -- bit 31 U-0 -- bit 23 S/HC-0 NVMWR bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- R/W-0 NVMOP3 R/W-0 NVMOP2 R/W-0 NVMOP1 R/W-0 NVMWREN R/HS-0 NVMERR R/HS-0 LVDERR R/HSHC-0 LVDSTAT U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- NVMCON: PROGRAMMING CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 NVMOP0 bit 0 Unimplemented: Read as `0' NVMWR: Write Control bit This bit is writeable when NVMWREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation (Hardware clears this bit when the operation completes.) 0 = Flash operation complete or inactive NVMWREN: Write Enable bit 1 = Enables writes to NVMWR 0 = Disables writes to NVMWR Note: This is the only bit in this register that is reset by a device Reset. NVMERR: Write Error bit 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled) This error is only captured for programming/erase operations 1 = Low-voltage detected 0 = Voltage level ok for programming Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled) This bit is read-only and is automatically set by hardware 1 = Low-voltage event active 0 = Low-voltage event NOT active Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10-4 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 129 PIC32MX FAMILY REGISTER 7-1: bit 15-0 NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED) NVMOP<3:0>: NVM Operation bits 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADD,R if it is not write-protected 0000 = No operation DS61143A-page 130 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 7.2 RTSP Operation 7.3 Control Registers RTSP allows the user code to modify Flash program memory contents. The device Flash memory is divided into two logical Flash partitions: the Program Flash Memory (PFM), and the Boot Flash Memory (BFM). The last page in Boot Flash Memory contains the DEBUG Page, which is reserved for use by the debugger tool while debugging. The program Flash array for the PIC32MX device is built up of a series of rows. A row contains 128 32-bit instruction words or 512 bytes. A group of 8 rows compose a page; which, therefore, contains 8 x 512 = 4096 bytes or 1024 instruction words. A page of Flash is the smallest unit of memory that can be erased at a single time. The program Flash array can be programmed in one of two ways: * Row programming, with 128 instruction words at a time. * Word programming, with 1 instruction word at a time. The CPU stalls (waits) until the programming operation is finished. The CPU will not execute any instruction, or respond to interrupts, during this time. If any interrupts occur during the programming cycle, they remain pending until the cycle completes. There are two SFRs used to erase and write the PFM: NVMCON and NVMKEY. The NVMCON register (Register 7-1) controls which blocks are to be erased, which memory block is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for writeprotection. To start a programming or erase sequence, the user must consecutively write 0xAA996655 and 0x556699AA to the NVMKEY register. Interrupts should be disabled. Refer to Section 7.4 "Programming Operations" for further details. 7.4 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 5 ms in duration and the processor stalls (WAITS) until the operation is finished. Setting the NVMWR bit (NVMCON<15>) starts the operation, and the NVMWR bit is automatically cleared when the operation is finished. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 131 PIC32MX FAMILY 7.4.1 PROGRAMMING ALGORITHM 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. 4. Read eight rows of program memory (1024 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the page (see Example 7-1): Write the first 128 words from data RAM into the program memory buffers (see Example 7-1). Repeat steps 4 and 5, using the next available 128 words from the block in data RAM by incrementing the value in NVMADDR and NVMASRCADDR, until all 1024 instructions are written back to Flash memory. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. EXAMPLE 7-1: ERASING FLASH PAGE unsigned int NVMUnlock (unsigned int nvmop) { unsigned int status; // Suspend or Disable all Interrupts asm volatile ("di %0" : "=r" (status)); // Enable Flash Write/Erase Operations and Select // Flash operation to perform NVMCON = 0x8000 \ nvmop; // Write Keys NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // Start the operation using the Set Register NVMCONSET = 0x8000; // Wait for operation to complete while (NVMCON & 0x8000); // Restore Interrupts if (status & 0x00000001 asm volatile ("ei"); else asm volatile ("di"); // Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } unsigned int NVMErasePage(void* address) { unsigned int res; // Set NVMADDR to the Start Address of page to erase NVMADDR = (unsigned int) address; // Unlock and Erase Page res = NVMUnlock(0x4004); // Return Result return res; } DS61143A-page 132 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 7-2: ROW PROGRAMMING SEQUENCE unsigned int NVMUnlock (unsigned int nvmop) { unsigned int status; // Suspend or Disable all Interrupts asm volatile ("di %0" : "=r" (status)); // Enable Flash Write/Erase Operations and Select // Flash operation to perform NVMCON = 0x8000 \ nvmop; // Write Keys NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // Start the operation using the Set Register NVMCONSET = 0x8000; // Wait for operation to complete while (NVMCON & 0x8000); // Restore Interrupts if (status & 0x00000001 asm volatile ("ei"); else asm volatile ("di"); // Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } unsigned int NVMWriteRow (void* address, void* data) { unsigned int res; // Set NVMADDR to Start Address of row to program NVMADDR = (unsigned int) address; // Set NVMSRCADDR to the SRAM data buffer Address NVMSRCADDR = (unsigned int) data; // Unlock and Write Row res = NVMUnlock(0x4003); // Return Result return res; } (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 133 PIC32MX FAMILY EXAMPLE 7-3: WORD PROGRAMMING SEQUENCE unsigned int NVMUnlock (unsigned int nvmop) { unsigned int status; // Suspend or Disable all Interrupts asm volatile ("di %0" : "=r" (status)); // Enable Flash Write/Erase Operations and Select // Flash operation to perform NVMCON = 0x8000 \ nvmop; // Write Keys NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // Start the operation using the Set Register NVMCONSET = 0x8000; // Wait for operation to complete while (NVMCON & 0x8000); // Restore Interrupts if (status & 0x00000001 asm volatile ("ei"); else asm volatile ("di"); // Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } unsigned int NVMWriteWord (void* address, unsigned int data) { unsigned int res; // Load data into NVMDATA register NVMDATA = data; // Load address to program into NVMADDR register NVMADDR = (unsigned int) address; // Unlock and Write Word res = NVMUnlock (0x4001); // Return Result return res; } DS61143A-page 134 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 7-4: PROGRAM FLASH ERASE SEQUENCE unsigned int NVMUnlock (unsigned int nvmop) { unsigned int status; // Suspend or Disable all Interrupts asm volatile ("di %0" : "=r" (status)); // Enable Flash Write/Erase Operations and Select // Flash operation to perform NVMCON = 0x8000 \ nvmop; // Write Keys NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // Start the operation using the Set Register NVMCONSET = 0x8000; // Wait for operation to complete while (NVMCON & 0x8000); // Restore Interrupts if (status & 0x00000001 asm volatile ("ei"); else asm volatile ("di"); // Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } unsigned int NVMErasePFM(void) { unsigned int res; // Unlock and Erase Program Flash res = NVMUnlock(0x4005); // Return Result return res; } (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 135 PIC32MX FAMILY NOTES: DS61143A-page 136 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 8.0 Note: RESETS This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * POR: Power-on Reset MCLR: Master Clear Reset Pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is shown in Figure 8-1. FIGURE 8-1: SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter SLEEP or IDLE Voltage Regulator Enabled VDD WDT Time-out Power-up Timer VDD Rise Detect Brown-out Reset BOR CMR SWR POR SYSRST MCLR WDTR Configuration Mismatch Reset Software Reset (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 137 PIC32MX FAMILY 8.1 Reset Registers RESET SFR SUMMARY Name RCON 31:24 23:16 15:8 7:0 BF80_F604 BF80_F608 BF80_F60C BF80_F610 RCONCLR RCONSET RCONINV RSWRST 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_F614 RSWRSTCLR BF80_F618 RSWRSTSET BF80_F61C RSWRSTINV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- Bit 31/23/15/7 -- -- -- EXTR Bit 30/22/14/6 -- -- -- SWR Bit 29/21/13/5 -- -- -- -- Bit 28/20/12/4 -- -- -- WDTO Bit 27/19/11/3 -- -- -- SLEEP Bit 26/18/10/2 -- -- -- IDLE Bit 25/17/9/1 -- -- CMR BOR Bit 24/16/8/0 -- -- VREGS POR TABLE 8-1: Virtual Address BF80_F600 Write clears selected bits in RCON, read yields undefined value Write sets selected bits in RCON, read yields undefined value Write inverts selected bits in RCON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SWRST Write clears selected bits in RSWRST, read yields undefined value Write sets selected bits in RSWRST, read yields undefined value Write inverts selected bits in RSWRST, read yields undefined value DS61143A-page 138 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 8-1: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-10 bit 9 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SWR U-0 -- R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CMR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- RCON: RESET CONTROL REGISTER(3) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 VREGS bit 8 R/W-1 POR bit 0 Unimplemented: Read as `0' CMR: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. VREGS: Voltage Regulator Standby Enable bit 1 = Regulator will be active during Sleep 0 = Regulator will go to Standby mode during Sleep EXTR: External Reset (MCLR) Pin Flag bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. SWR: Software Reset Flag bit 1 = A Software Reset was executed 0 = A Software Reset was not executed Note: This bit is set in hardware, it can only be cleared (= 0) in software. Unimplemented: Read as `0' WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode Note: This bit is set in hardware, it can only be cleared (= 0) in software. IDLE: Wake-up From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode Note: This bit is set in hardware, it can only be cleared (= 0) in software. bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 139 PIC32MX FAMILY REGISTER 8-1: bit 1 RCON: RESET CONTROL REGISTER(3) (CONTINUED) BOR: Brown-out Reset Flag bit(1)(2) 1 = A Brown-out Reset has occurred. 0 = A Brown-out Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. POR: Power-on Reset Flag bit(1) 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. 2: BOR is also set after a Power-on Reset. 3: The RCON flag bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. bit 0 Note 1: User must clear this bit to view next detection. DS61143A-page 140 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 8-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-1 bit 0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- W-0 SWRST bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- RSWRST: SOFTWARE RESET REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' SWRST: Software Reset Trigger bit 1 = Enable software reset event Note: The system unlock sequence must be performed before the SWRST bit can be written. A read must follow the write of this bit to generate a Reset. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 141 PIC32MX FAMILY 8.2 Reset Modes 8.2.3 SOFTWARE RESET (SWR) The PIC32MX internal device Reset signal is SYSRST and can be generated from multiple Reset sources, such as POR (Power-on Reset), BOR (Brown-out Reset), MCLR (Master Clear Reset), WDTO (Watchdog Time-out Reset), SWR (Software Reset) and CMR (Configuration Mismatch Reset). A Reset source sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 8-1). A system Reset is active at first the POR and asserted until device configuration settings are loaded and the clock oscillator sources become stable. The system Reset is then deasserted allowing the CPU to start fetching code after 8 system clock cycles (SYSCLK) . The PIC32MX CPU core doesn't provide a specific RESET "instruction"; however, a hardware Reset can be performed in software (Software Reset) by executing a Software Reset command sequence: * * * * Write the system unlock sequence Set bit, SWRST (RSWRST<0>) = 1 Read RSWRST register - Reset occurs Follow with "while(1);" or 4 "NOP" instructions 8.2.1 POWER-ON RESET (POR) A power-on event generates an internal Power-on Reset pulse when a VDD rise is detected above VPOR. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and VDD rise rate specifications, refer to Section 29.0 "Electrical Characteristics" of this device family data sheet. Writing a `1' to the RSWRST register sets bit SWRST, arming the Software Reset. The subsequent read of the RSWRST register triggers the Software Reset, which should occur on the next clock cycle following the read operation. To ensure no other user code is executed before the Reset event occurs, it is recommended that 4 `NOP' instructions or a "while(1);" statement be placed after the READ instruction. The SWR Status bit (RCON<6>) is set to indicate the Software Reset. 8.2.2 MCLR RESET (EXTR) Whenever the MCLR pin is driven low, the device asynchronously asserts SYSRST provided the input pulse on MCLR is longer than a certain minimum width, as specified in Section 29.0 "Electrical Characteristics" of this device family data sheet. MCLR provides a filter to minimize the effects of noise and to avoid unwanted Reset conditions. The EXTR bit (RCON<7>) is set to indicate the MCLR Reset. EXAMPLE 8-1: SOFTWARE RESET COMMAND SEQUENCE /* The following code illustrates a software Reset */ // assume interrupts are disabled // assume the DMA controller is suspended // assume the device is locked /* perform a system unlock sequence */ // starting critical sequence SYSKEY = 0xaa996655; //write first unlock key to SYSKEY SYSKEY = 0x556699aa //write second unlock key to SYSKEY /* set SWRST bit to arm reset */ RSWRSTSET = 1; /* read RSWRST register to trigger reset */ unsigned int dummy; dummy = RSWRST; /* prevent any unwanted code execution until reset occurs*/ while(1); DS61143A-page 142 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 8.2.4 WATCHDOG TIMER TIME-OUT RESET (WDTR) 8.3 8.3.1 Reset States SPECIAL FUNCTION REGISTER RESET STATES A Watchdog Timer time-out causes the device Reset, SYSRST, to be asserted asynchronously. Note that a WDT time-out during SLEEP or IDLE mode will wake-up the processor and branch to the PIC32MX Reset vector, but not reset the processor. The only bits affected are WDTO and the SLEEP or IDLE bits in the RCON register. For more information, refer to Section 26.0 "Watchdog Timer". Note: In this document, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. Most of the Special Function Registers (SFRs) associated with the PIC32MX CPU and peripherals are reset to a particular value at a device Reset. Refer to the corresponding data sheet section for a peripheral's SFR details. The Reset value for each SFR will depend on the type of Reset. 8.3.2 CONFIGURATION WORD REGISTER RESET STATES All Reset conditions force the Flash Configuration Word registers to be re-loaded. However, a POR forces Flash Configuration Word registers to be reset prior to being reloaded. For all other Reset conditions, the Flash Configuration Word registers are not reset prior to being re-loaded. This difference accommodates MCLR assertions during Debug mode without affecting the state of the debug operations. 8.2.5 BROWN-OUT RESET (BOR) PIC32MX Family devices have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). Refer to Section 29.2 "AC Characteristics and Timing Parameters" for further details. 8.2.6 CONFIGURATION MISMATCH RESET To maintain the integrity of the stored configuration values, all device Configuration bits are implemented as a complementary set of register bits. For each bit, as the actual value of the register is written as `1', a complementary value, `0', is stored into its corresponding background register and vice versa. The bit pairs are compared every time, including Sleep mode. During this comparison, if the Configuration bit values are not found opposite to each other, a Configuration Mismatch event is generated which causes a device Reset. If a device Reset occurs as a result of a Configuration Mismatch, the CM bit (RCON<9>) is set. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 143 PIC32MX FAMILY 8.3.3 RCON REGISTER STATES Status bits from the RCON register are set or cleared differently in different Reset situations, as indicated in Table 8-2. The RCON bits only serve as status bits. The user may set or clear any of the bits at any time during code execution. Setting a particular Reset bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. TABLE 8-2: STATUS BITS, INITIALIZATION CONDITION FOR RCON REGISTER SLEEP WDTO EXTR SWR IDLE BOR 1 1 u u u u u u u u u u Condition Program Counter 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 Vector(1) Vector (1) Power-on Reset Brown-out Reset MCLR During Run Mode MCLR During Idle Mode MCLR During Sleep Mode Software Reset Command Configuration Word Mismatch Reset WDT Time-out Reset During Run Mode WDT Time-out Reset During Idle Mode WDT Time-out Reset During Sleep Mode Interrupt Exit from Idle Mode Interrupt Exit from Sleep Mode 0 0 1 1 1 u u u u u u u 0 0 u u u 1 u u u u u u 0 0 u u u u u 1 1 1 0 0 0 0 u u 1(2) u u u u 1(2) u 1(2) 0 0 u 1(2) u u u u 1(2) u 1(2) u 0 0 u u u u 1 u u u u u Legend: u = unchanged Note 1: Depends on Interrupt source. 2: SLEEP and IDLE bits states defined by previously executed WAIT instruction. 8.4 Using the RCON Status Bits The user can read the RCON register after any device Reset to determine the cause of the Reset. The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. DS61143A-page 144 Advance Information (c) 2007 Microchip Technology Inc. POR 1 0 u u u u u u u u u u CM PIC32MX FAMILY TABLE 8-3: POR (RCON<0>) BOR (RCON<1>) EXTR (RCON<7>) SWR (RCON<6>) CMR (RCON<9> WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) Note: RESET FLAG BIT OPERATION Flag Bit Set by: POR POR, BOR MCLR Reset Software Reset Command Configuration Mismatch WDT Time-Out WAIT Instruction WAIT Instruction Cleared by: User Software User Software User Software, POR, BOR User Software, POR, BOR User Software, POR, BOR User Software, POR, BOR User Software, POR, BOR User Software, POR, BOR All Reset flag bits may be set or cleared by the user software. 8.4.1 DEVICE RESET TO CODE EXECUTION START TIME The delay between the end of a Reset event and when the device actually begins to execute code is determined by two main factors: the type of Reset and the system clock source coming out of the Reset. The code execution start time for various types of device Resets are summarized in Table 8-4. Individual delays are characterized in Section 29.2 "AC Characteristics and Timing Parameters". TABLE 8-4: Reset Type POR CODE EXECUTION START TIME FOR VARIOUS DEVICE RESETS Clock Source EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL Code Execution Delay TPOR + TRST + TSTARTUP TPOR + TRST + TSTARTUP TPOR + TRST + TSTARTUP TPOR + TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP TRST + TSTARTUP System Clock Delay -- TLOCK TOST TOST + TLOCK -- TLOCK TOST TOST + TLOCK -- -- -- -- FSCM Delay -- TFSCM TFSCM TFSCM -- TFSCM TFSCM TFSCM -- -- -- -- Notes 1, 2, 3, 7 1, 2, 3, 5, 6, 7 1, 2, 3, 4, 6, 7 1, 2, 3, 4, 5, 6, 7 2, 3, 7 2, 3, 5, 6, 7 2, 3, 4, 6, 7 2, 3, 4, 5, 6, 7 3, 7 3, 7 3, 7 3, 7 BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL MCLR WDTO SWR CMR Note 1: 2: 3: 4: 5: 6: 7: Any Clock Any Clock Any Clock Any Clock TPOR = Power-on Reset delay. TRST = TVREG if on-chip regulator is enabled or TPWRT if on-chip regulator is disabled. TSTARTUP = Load configuration settings, and depending on the oscillator settings, may include TOST, TLOCK and TFSCM. TOST = Oscillator Start-up Timer. TLOCK = PLL lock time. TFSCM = Fail-Safe Clock Monitor delay. Included is a required delay of 8 system clock cycles before the Reset to the CPU core is deasserted. 8.5 Interrupts 8.6 I/O Pin Control There are no interrupts for this module. There are not I/O pin controls associated with this module. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 145 PIC32MX FAMILY NOTES: DS61143A-page 146 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 9.0 Note: INTERRUPTS This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The PIC32MX Family interrupts module includes the following features: * * * * * * * * * * * * Up to 96 interrupt sources Up to 64 interrupt vectors Single and Multi-Vector mode operations 5 external interrupts with edge polarity control Interrupt proximity timer Module Freeze in Debug mode 7 user-selectable priority levels for each vector 4 user-selectable subpriority levels within each priority Dedicated shadow set for highest priority level Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing PIC32MX Family generates interrupt requests in response to interrupt events from peripheral modules. The interrupts module exists external to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 9-1: INTERRUPT CONTROLLER MODULE Interrupt Requests Vector Number Interrupt Controller Priority Level CPU Core Shadow Set Number Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section 2.0. "CPU". To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only.CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 147 PIC32MX FAMILY 9.1 Note: Control Registers Each PIC32MX device variant may have one or more Interrupt channels. An `x' used in the names of control/Status bits and registers denotes the particular channel. Refer to the specific device data sheets for more details. * TPTMR: Temporal Proximity Timer Register TPTMRCLR, TPTMRSET, TPTMRNINV: Atomic Bit Manipulation, Write-Only Registers for TPTMR * IFS0, IFS1: Interrupt Flag Status Registers IFSxCLR, IFSxSET, IFSxINV: Atomic Manipulation, Write-Only Registers for IFSx * IEC0, IEC1: Interrupt Enable Control Registers IECxCLR, IECxSET, IECxINV: Atomic Manipulation, Write-Only Registers for IECx Bit Bit The interrupts module consists of the following Special Function Registers (SFRs): * INTCON: Interrupt Control Register INTCONCLR, INTCONSET, INTCONINV: Atomic Bit Manipulation, Write-Only Registers for INTCON * INTSTAT: Interrupt Status Register INTSTATCLR, INTSTATSET, INTSTATINV: Atomic Bit Manipulation, Write-Only Registers for INTSTAT * IPC0 - IPC11: Interrupt Priority Control Registers IPCxCLR, IPCxSET, IPCxINV: Atomic Bit Manipulation, Write-Only Registers for IPCx The following table provides a brief summary of interrupts module related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. TABLE 9-1: Name INTCON INTERRUPT SFR SUMMARY Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- -- -- Bit 30/22/14/6 -- -- FRZ -- Bit 29/21/13/5 -- -- -- -- Bit 28/20/12/4 -- -- MVEC INT4EP Bit 27/19/11/3 -- -- -- INT3EP INT2EP Bit 26/18/10/2 -- -- Bit 25/17/9/1 -- -- TPC<2:0> INT1EP INT0EP Bit 24/16/8/0 -- SS0 INTCONCLR INTCONSET INTCONINV INTSTAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears the selected bits in INTCON, read yields undefined value Write sets the selected bits in INTCON, read yields undefined value Write inverts the selected bits in INTCON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- VEC<5:0> -- -- -- -- RIPL<2:0> -- -- INTSTATCLR INTSTATSET INTSTATINV TPTMR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears the selected bits in INTSTAT, read yields undefined value Write sets the selected bits in INTSTAT, read yields undefined value Write inverts the selected bits in INTSTAT, read yields undefined value TPTMR<31:0> TPTMRCLR TPTMRSET TPTMRINV IFS0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 I2C1MIF SPI1EIF INT3IF INT1IF Write clears the selected bits in TPTMR, read yields undefined value Write clears the selected bits in TPTMR, read yields undefined value Write clears the selected bits in TPTMR, read yields undefined value I2C1SIF OC5IF OC3IF OC1IF I2C1BIF IC5IF IC3IF IC1IF U1TXIF T5IF T3IF T1IF U1RXIF INT4IF INT2IF INT0IF U1EIF OC4IF OC2IF CS1IF SPI1RXIF IC4IF IC2IF CS0IF SPI1TXIF T4IF T2IF CTIF IFS0CLR IFS0SET IFS0INV 31:0 31:0 31:0 Write clears the selected bits in IFS0, read yields undefined value Write sets the selected bits in IFS0, read yields undefined value Write inverts the selected bits in IFS0, read yields undefined value DS61143A-page 148 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 9-1: Name IFS1 31:24 23:16 15:8 7:0 IFS1CLR IFS1SET IFS1INV IEC0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IEC0CLR IEC0SET IEC0INV IEC1 INTERRUPT SFR SUMMARY (CONTINUED) Bit 31/23/15/7 -- -- RTCCIF SPI2RXIF Bit 30/22/14/6 -- -- FSCMIF SPI2TXIF Bit 29/21/13/5 -- -- I2C2MIF SPI2EIF Bit 28/20/12/4 -- -- I2C2SIF CMP2IF Bit 27/19/11/3 -- DMA3IF I2C2BIF CMP1IF Bit 26/18/10/2 -- DMA2IF U2TXIF PMPIF Bit 25/17/9/1 -- DMA1IF U2RXIF AD1IF Bit 24/16/8/0 FCEIF DMA0IF U2EIF CNIF Write clears the selected bits in IFS1, read yields undefined value Write sets the selected bits in IFS1, read yields undefined value Write inverts the selected bits in IFS1, read yields undefined value I2C1MIE SPI1EIE INT3IE INT1IE I2C1SIE OC5IE OC3IE OC1IE I2C1BIE IC5IE IC3IE IC1IE U1TXIE T5IE T3IE T1IE U1RXIE INT4IE INT2IE INT0IE U1EIE OC4IE OC2IE CS1IE SPI1RXIE IC4IE IC2IE CS0IE SPI1TXIE T4IE T2IE CTIE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears the selected bits in IEC0, read yields undefined value Write sets the selected bits in IEC0, read yields undefined value Write inverts the selected bits in IEC0, read yields undefined value -- -- RTCCIE SPI2RXIE -- -- FSCMIE SPI2TXIE -- -- I2C2MIE SPI2EIE -- -- I2C2SIE CMP2IE -- DMA3IE I2C2BIE CMP1IE -- DMA2IE U2TXIE PMPIE -- DMA1IE U2RXIE AD1IE FCEIE DMA0IE U2EIE CNIE IEC1CLR IEC1SET IEC1INV 31:0 31:0 31:0 Write clears the selected bits in IEC1, read yields undefined value Write sets the selected bits in IEC1, read yields undefined value Write inverts the selected bits in IEC1, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- INT0IP<2:0> CS1IP<2:0> CS0IP<2:0> CTIP<2:0> INT0IS<1:0> CS1IS<1:0> CS0IS<1:0> CTIS<1:0> IPC0 31:24 23:16 15:8 7:0 IPC0CLR IPC0SET IPC0INV IPC1 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- -- -- -- -- Write clears the selected bits in IPC0, read yields undefined value Write sets the selected bits in IPC0, read yields undefined value Write inverts the selected bits in IPC0, read yields undefined value -- -- -- -- INT1IP<2:0> OC1IP<2:0> IC1IP<2:0> T1IP<2:0> INT1IS<1:0> OC1IS<1:0> IC1IS<1:0> T1IS<1:0> IPC1CLR IPC1SET IPC1INV IPC2 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- -- -- -- -- Write clears the selected bits in IPC1, read yields undefined value Write sets the selected bits in IPC1, read yields undefined value Write inverts the selected bits in IPC1, read yields undefined value -- -- -- -- INT2IP<2:0> OC2IP<2:0> IC2IP<2:0> T2IP<2:0> INT2IS<1:0> OC2IS<1:0> IC2IS<1:0> T2IS<1:0> IPC2CLR IPC2SET IPC2INV 31:0 31:0 31:0 Write clears the selected bits in IPC2, read yields undefined value Write sets the selected bits in IPC2, read yields undefined value Write inverts the selected bits in IPC2, read yields undefined value (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 149 PIC32MX FAMILY TABLE 9-1: Name IPC3 31:24 23:16 15:8 7:0 IPC3CLR IPC3SET IPC3INV IPC4 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC4CLR IPC4SET IPC4INV IPC5 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC5CLR IPC5SET IPC5INV IPC6 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC6CLR IPC6SET IPC6INV IPC7 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC7CLR IPC7SET IPC7INV IPC8 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC8CLR IPC8SET IPC8INV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INTERRUPT SFR SUMMARY (CONTINUED) Bit 31/23/15/7 -- -- -- -- Bit 30/22/14/6 -- -- -- -- Bit 29/21/13/5 -- -- -- -- Bit 28/20/12/4 Bit 27/19/11/3 INT3IP<2:0> OC3IP<2:0> IC3IP<2:0> T3IP<2:0> Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 INT3IS<1:0> OC3IS<1:0> IC3IS<1:0> T3IS<1:0> Write clears the selected bits in IPC3, read yields undefined value Write sets the selected bits in IPC3, read yields undefined value Write inverts the selected bits in IPC3, read yields undefined value -- -- -- -- INT4IP<2:0> OC4IP<2:0> IC4IP<2:0> T4IP<2:0> INT4IS<1:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> Write clears the selected bits in IPC4, read yields undefined value Write sets the selected bits in IPC4, read yields undefined value Write inverts the selected bits in IPC4, read yields undefined value -- -- -- -- SPI1IP<2:0> OC5IP<2:0> IC5IP<2:0> T5IP<2:0> SPI1IS<1:0> OC5IS<1:0> IC5IS<1:0> T5IS<1:0> Write clears the selected bits in IPC5, read yields undefined value Write sets the selected bits in IPC5, read yields undefined value Write inverts the selected bits in IPC5, read yields undefined value -- -- -- -- AD1IP<2:0> CNIP<2:0> I2C1IP<2:0> U1IP<2:0> AD1IS<1:0> CNIS<1:0> I2C1IS<1:0> U1IS<1:0> Write clears the selected bits in IPC6, read yields undefined value Write sets the selected bits in IPC6, read yields undefined value Write inverts the selected bits in IPC6, read yields undefined value -- -- -- -- SPI2IP<2:0> CMP2IP<2:0> CMP1IP<2:0> PMPIP<2:0> SPI2IS<1:0> CMP2IS<1:0> CMP1IS<1:0> PMPIS<1:0> Write clears the selected bits in IPC7, read yields undefined value Write sets the selected bits in IPC7, read yields undefined value Write inverts the selected bits in IPC7, read yields undefined value -- -- -- -- RTCCIP<2:0> FSCMIP<2:0> I2C2IP<2:0> U2IP<2:0> RTCCIS<1:0> FSCMIS<1:0> I2C2IS<1:0> U2IS<1:0> Write clears the selected bits in IPC8, read yields undefined value Write sets the selected bits in IPC8, read yields undefined value Write inverts the selected bits in IPC8, read yields undefined value DS61143A-page 150 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 9-1: Name IPC9 31:24 23:16 15:8 7:0 IPC9CLR IPC9SET IPC9INV IPC10 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC10CLR IPC10SET IPC10INV IPC11 31:0 31:0 31:0 31:24 23:16 15:8 7:0 IPC11CLR IPC11SET IPC11INV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INTERRUPT SFR SUMMARY (CONTINUED) Bit 31/23/15/7 -- -- -- -- Bit 30/22/14/6 -- -- -- -- Bit 29/21/13/5 -- -- -- -- Bit 28/20/12/4 Bit 27/19/11/3 DMA3IP<2:0> DMA2IP<2:0> DMA1IP<2:0> DMA0IP<2:0> Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 DMA3IS<1:0> DMA2IS<1:0> DMA1IS<1:0> DMA0IS<1:0> Write clears the selected bits in IPC9, read yields undefined value Write sets the selected bits in IPC9, read yields undefined value Write inverts the selected bits in IPC9, read yields undefined value -- -- -- -- -- -- -- -- _ -- _ -- Write clears the selected bits in IPC10, read yields undefined value Write sets the selected bits in IPC10, read yields undefined value Write inverts the selected bits in IPC10, read yields undefined value -- -- -- -- -- -- -- FCEIP<2:0> _ -- -- FCEIS<1:0> Write clears the selected bits in IPC11, read yields undefined value Write sets the selected bits in IPC11, read yields undefined value Write inverts the selected bits in IPC11, read yields undefined value (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 151 PIC32MX FAMILY REGISTER 9-1: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-17 bit 16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP R/W-0 FRZ U-0 -- R/W-0 MVEC U-0 -- R/W-0 R/W-0 TPC<2:0> bit 8 R/W-0 INT0EP bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- INTCON: INTERRUPT CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-0 SS0 bit 16 R/W-0 Unimplemented: Read as `0' SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set Unimplemented: Read as `0' FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Only writable in Debug Exception mode, otherwise, read "0". Unimplemented: Read as `0' MVEC: Multi-Vector Configuration bit 1 = Interrupt controller configured for Multi-Vectored mode 0 = Interrupt controller configured for Single Vectored mode Unimplemented: Read as `0' TPC<2:0>: Temporal Proximity Control bits 111 = Interrupt of group priority 7 or lower starts the IP timer 110 = Interrupt of group priority 6 or lower starts the IP timer 101 = Interrupt of group priority 5 or lower starts the IP timer 100 = Interrupt of group priority 4 or lower starts the IP timer 011 = Interrupt of group priority 3 or lower starts the IP timer 010 = Interrupt of group priority 2 or lower starts the IP timer 001 = Interrupt of group priority 1 starts the IP timer 000 = Disables proximity timer Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-8 bit 7-5 bit 4 DS61143A-page 152 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-1: bit 3 INTCON: INTERRUPT CONTROL REGISTER (CONTINUED) INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 153 PIC32MX FAMILY REGISTER 9-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-11 bit 10-8 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) U-0 -- R-0 R-0 R-0 VEC<5:0> bit 0 R-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- R-0 R-0 RIPL<2:0> bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- INTSTAT: INTERRUPT STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 Unimplemented: Read as `0' RIPL<2:0>: Requested Priority Level bits 000 -- 111 = The priority level of the latest interrupt presented to the CPU Note: This value should only be used when the interrupt controller is configured for Single Vector mode. VEC: Interrupt Vector bits 00000 -- 11111 = The interrupt vector that is presented to the CPU Note: This value should only be used when the interrupt controller is configured for Single Vector mode. bit 5-0 DS61143A-page 154 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-3: R/W-0 bit 31 R/W-0 bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR: TEMPORAL PROXIMITY TIMER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 TPTMR<31:24> TPTMR<23:16> TPTMR<15:8> TPTMR<7:0> TPTMR: Temporal Proximity Timer Reload bits Used by the temporal proximity timer as a reload value when the temporal proximity timer is triggered by an interrupt event. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 155 PIC32MX FAMILY REGISTER 9-4: R/W-0 I2C1MIF bit 31 R/W-0 SPI1EIF bit 23 R/W-0 INT3IF bit 15 R/W-0 INT1IF bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) R/W-0 OC1IF R/W-0 IC2IF R/W-0 T1IF R/W-0 INT0IF R/W-0 CS1IF R/W-0 CS0IF R/W-0 OC3IF R/W-0 IC3IF R/W-0 T3IF R/W-0 INT2IF R/W-0 OC2IF R/W-0 IC2IF R/W-0 OC5IF R/W-0 IC5IF R/W-0 T5IF R/W-0 INT4IF R/W-0 OC4IF R/W-0 IC4IF IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0 I2CSIF R/W-0 I2CBIF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 U1EIF R/W-0 SPI1RXIF R/W-0 SPI1TXIF bit 24 R/W-0 T4IF bit 16 R/W-0 T2IF bit 8 R/W-0 CTIF bit 0 I2C1MIF: I2C1 Master Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred I2CSIF: I2C1 Slave Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred I2CBIF: I2C1 Bus Collision Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U1TXIF: UART1 Transmitter Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U1RXIF: UART1 Receiver Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U1EIF: UART1 Error Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI1RXIF: SPI1 Receive Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI1TXIF: SPI1 Transmitter Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI1EIF: SPI1 Error Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 DS61143A-page 156 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-4: bit 22 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC5IF: Output Compare 5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC5IF: Input Compare 5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred T5IF: Timer5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred INT4IF: External Interrupt 4 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC4IF: Output Compare 4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC4IF: Input Compare 4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred T4IF: Timer4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred INT3IF: External Interrupt 3 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC3IF: Output Compare 3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC3IF: Input Compare 3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred T3IF: Timer3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred INT2IF: External Interrupt 2 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC2IF: Output Compare 2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC2IF: Input Compare 2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred T2IF: Timer2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred INT1IF: External Interrupt 1 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC1IF: Output Compare 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 157 PIC32MX FAMILY REGISTER 9-4: bit 5 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) IC1IF: Input Compare 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred T1IF: Timer1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred INT0IF: External Interrupt 0 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CS1IF: Core Software Interrupt 1 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CS0IF: Core Software Interrupt 0 Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CTIF: Core Timer Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred bit 4 bit 3 bit 2 bit 1 bit 0 DS61143A-page 158 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-5: U-0 -- bit 31 U-0 -- bit 23 R/W-0 RTCCIF bit 15 R/W-0 SPI2RXIF bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-25 bit 24 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF U-0 -- U-0 -- U-0 -- R/W-0 DMA3IF R/W-0 DMA2IF R/W-0 DMA1IF IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FCEIF bit 24 R/W-0 DMA0IF bit 16 R/W-0 U2EIF bit 8 R/W-0 CNIF bit 0 Unimplemented: Read as `0' FCEIF: Flash Control Event Interrupt Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred Unimplemented: Read as `0' DMA3IF: DMA3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred DMA2IF: DMA2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred DMA1IF: DMA1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred DMA0IF: DMA0 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred RTCCIF: Real Time Clock Interrupt Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred I2C2MIF: I2C2 Master Interrupt Request bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred bit 23-20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 159 PIC32MX FAMILY REGISTER 9-5: bit 12 IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) I2C2SIF: I2C2 Slave Interrupt Request bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred I2C2BIF: I2C2 Bus Collision Interrupt Request bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U2TXIF: UART2 Transmitter Interrupt Request bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U2RXIF: UART2 Receiver Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred U2EIF: UART2 Error Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI2RXIF: SPI2 Receiver Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI2TXIF: SPI2 Transmitter Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred SPI2EIF: SPI2 Error Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CMP2IF: Comparator 2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CMP1IF: Comparator 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred PMPIF: Parallel Master Port Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred AD1IF: Analog-to-Digital 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred CNIF: Input Change Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61143A-page 160 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-6: R/W-0 I2C1MIE bit 31 R/W-0 SPI1EIE bit 23 R/W-0 INT3IE bit 15 R/W-0 INT1IE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 OC1IE R/W-0 IC1IE R/W-0 T1IE R/W-0 INT0IE R/W-0 CS1IE R/W-0 CS0IE R/W-0 OC3IE R/W-0 IC3IE R/W-0 T3IE R/W-0 INT2IE R/W-0 OC2IE R/W-0 IC2IE R/W-0 OC5IE R/W-0 IC5IE R/W-0 T5IE R/W-0 INT4IE R/W-0 OC4IE R/W-0 IC4IE IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 I2C1SIE R/W-0 I2C1BIE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 U1EIE R/W-0 SPI1RXIE R/W-0 SPI1TXIE bit 24 R/W-0 T4IE bit 16 R/W-0 T2IE bit 8 R/W-0 CTIE bit 0 I2C2MIE: I2C2 Master Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled I2C1SIE: I2C1 Slave Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled I2C1BIE: I2C1 Bus Collision Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI1RXIE: SPI1 Receive Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI1TXIE: SPI1 Transmitter Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 161 PIC32MX FAMILY REGISTER 9-6: bit 22 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) OC5IE: Output Compare 5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC5IE: Input Compare 5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled INT4IE: External Interrupt 4 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC4IE: Output Compare 4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC4IE: Input Compare 4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled INT3IE: External Interrupt 3 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC3IE: Output Compare 3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC3IE: Input Compare 3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled INT2IE: External Interrupt 2 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC2IE: Output Compare 2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC2IE: Input Compare 2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled INT1IE: External Interrupt 1 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC1IE: Output Compare 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 DS61143A-page 162 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-6: bit 5 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) IC1IE: Input Compare 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T1IE: Timer1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CS1IE: Core Software Interrupt 1 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CS0IE: Core Software Interrupt 0 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CTIE: Core Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 163 PIC32MX FAMILY REGISTER 9-7: U-0 -- bit 31 U-0 -- bit 23 R/W-0 RTCCIE bit 15 R/W-0 SPI2RXIE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-25 bit 24 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit value at POR (`0', `1', x = Unknown) R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE U-0 -- U-0 -- U-0 -- R/W-0 DMA3IE R/W-0 DMA2IE R/W-0 DMA1IE IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FCEIE bit 24 R/W-0 DMA0IE bit 16 R/W-0 U2EIE bit 8 R/W-0 CNIE bit 0 Unimplemented: Read as `0' FCEIE: Flash Control Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as `0' DMA3IE: DMA3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DMA2IE: DMA2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DMA1IE: DMA1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DMA0IE: DMA0 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled RTCCIE: Real-Time Clock Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled I2C2MIE: I2C2 Master Interrupt Request bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 23-20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 DS61143A-page 164 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-7: bit 12 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) I2C2SIE: I2C2 Slave Interrupt Request bit 1 = Interrupt is enabled 0 = Interrupt is disabled I2C2BIE: I2C2 Bus Collision Interrupt Request bit 1 = Interrupt is enabled 0 = Interrupt is disabled U2TXIE: UART2 Transmitter Interrupt Request bit 1 = Interrupt is enabled 0 = Interrupt is disabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI2RXIE: SPI2 Receiver Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI2TXIE: SPI2 Transmitter Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CMP2IE: Comparator 2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CMP1IE: Comparator 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled AD1IE: Analog-to-Digital 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CNIE: Input Change Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 165 PIC32MX FAMILY REGISTER 9-8: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 CTIP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CS0IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CS1IP<2:0> R/W-0 R/W-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 -- U-0 -- R/W-0 R/W-0 INT0IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 INT0IS<1:0> CS1IS<1:0> CS0IS<1:0> CTIS<1:0> Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled INT0IS<1:0>: External Interrupt 0 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' CS1IP<2:0>: Core Software 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CS1IS<1:0>: Core Software 1 Interrupt subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 166 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-8: bit 15-13 bit 12-10 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 (CONTINUED) Unimplemented: Read as `0' CS0IP<2:0>: Core Software 0 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CS0IS<1:0>: Core Software 0 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' CTIP<2:0>: Core Timer Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CTIS<1:0>: Core Timer Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 167 PIC32MX FAMILY REGISTER 9-9: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 T1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 IC1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 OC1IP<2:0> R/W-0 R/W-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0 R/W-0 INT1IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 INT1IS<1:0> OC1IS<1:0> IC1IS<1:0> T1IS<1:0> Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled INT1IS<1:0>: External Interrupt 1 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' OC1IP<2:0>: Output Compare 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled OC1IS<1:0>: Output Compare 1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 168 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-9: bit 15-13 bit 12-10 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 (CONTINUED) Unimplemented: Read as `0' IC1IP<2:0>: Input Compare 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IC1IS<1:0>: Input Compare 1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled T1IS<1:0>: Timer1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 169 PIC32MX FAMILY REGISTER 9-10: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 T2IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 IC2IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 OC2IP<2:0> R/W-0 R/W-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 -- U-0 -- R/W-0 R/W-0 INT2IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 INT2IS<1:0> OC2IS<1:0> IC2IS<1:0> T2IS<1:0> Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled INT2IS<1:0>: External Interrupt 2 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' OC2IP<2:0>: Output Compare 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled OC2IS<1:0>: Output Compare 2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 170 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-10: bit 15-13 bit 12-10 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 (CONTINUED) Unimplemented: Read as `0' IC2IP<2:0>: Input Compare 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IC2IS<1:0>: Input Compare 2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled T2IS<1:0>: Timer2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 171 PIC32MX FAMILY REGISTER 9-11: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 T3IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 IC3IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 OC3IP<2:0> R/W-0 R/W-0 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 -- U-0 -- R/W-0 R/W-0 INT3IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 INT3IS<1:0> OC3IS<1:0> IC3IS<1:0> T3IS<1:0> Unimplemented: Read as `0' INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled INT3IS<1:0>: External Interrupt 3 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' OC3IP<2:0>: Output Compare 3 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled OC3IS<1:0>: Output Compare 3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 172 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-11: bit 15-13 bit 12-10 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 (CONTINUED) Unimplemented: Read as `0' IC3IP<2:0>: Input Compare 3 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled IC3IS<1:0>: Input Compare 3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled T3IS<1:0>: Timer3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 173 PIC32MX FAMILY REGISTER 9-12: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- U-0 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 U-0 -- U-0 R/W-0 R/W-0 R/W-0 T4IP<2:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 IC4IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 OC4IP<2:0> R/W-0 R/W-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 -- U-0 -- R/W-0 R/W-0 INT4IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 R/W-0 INT4IS<1:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> Unimplemented: Read as `0' INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled INT4IS<1:0>: External Interrupt 4 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' OC4IP<2:0>: Output Compare 4 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled OC4IS<1:0>: Output Compare 4 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 174 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-12: bit 15-13 bit 12-10 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 (CONTINUED) Unimplemented: Read as `0' IC4IP<2:0>: Input Compare 4 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IC4IS<1:0>: Input Compare 4 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled T4IS<1:0>: Timer4 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 175 PIC32MX FAMILY REGISTER 9-13: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 T5IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 IC5IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 OC5IP<2:0> R/W-0 R/W-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 -- U-0 -- R/W-0 R/W-0 SPI1IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 SPI1IS<1:0> OC5IS<1:0> IC5IS<1:0> T5IS<1:0> Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled SPI1IS<1:0>: SPI1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' OC5IP<2:0>: Output Compare 5 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled OC5IS<1:0>: Output Compare 5 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 176 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-13: bit 15-13 bit 12-10 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 (CONTINUED) Unimplemented: Read as `0' IC5IP<2:0>: Input Compare 5 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IC5IS<1:0>: Input Compare 5 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled T5IS<1:0>: Timer5 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 177 PIC32MX FAMILY REGISTER 9-14: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 bit 31-29 bit 28-26 Unimplemented: Read as `0' AD1IP<2:0>: Analog-to-Digital 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled AD1IS<1:0>: Analog-to-Digital 1 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' CNIP<2:0>: Input Change Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CNIS<1:0>: Input Change Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' U-0 -- U-0 -- R/W-0 R/W-0 U1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 I2C1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CNIP<2:0> R/W-0 R/W-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 -- U-0 -- R/W-0 R/W-0 AD1IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 AD1IS<1:0> CNIS<1:0> I2C1IS<1:0> U1IS<1:0> bit 25-24 bit 23-21 bit 20-18 bit 17-16 bit 15-13 DS61143A-page 178 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-14: bit 12-10 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 (CONTINUED) I2C1IP<2:0>: I2C1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled I2C1IS<1:0>: I2C1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' U1IP<2:0>: UART1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled U1IS<1:0>: UART1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 179 PIC32MX FAMILY REGISTER 9-15: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 PMPIP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CMP1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CMP2IP<2:0> R/W-0 R/W-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 -- U-0 -- R/W-0 R/W-0 SPI2IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 SPI2IS<1:0> CMP2IS<1:0> CMP1IS<1:0> PMPIS<1:0> Unimplemented: Read as `0' SPI2IP<2:0>: SPI2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled SPI2IS<1:0>: SPI2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' CMP2IP<2:0>: Compare 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CMP2IS<1:0>: Compare 2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 180 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-15: bit 15-13 bit 12-10 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 (CONTINUED) Unimplemented: Read as `0' CMP1IP<2:0>: Compare 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CMP1IS<1:0>: Compare 1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled PMPIS<1:0>: Parallel Master Port Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 181 PIC32MX FAMILY REGISTER 9-16: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 U2IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 I2C2IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 FSCMIP<2:0> R/W-0 R/W-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 -- U-0 -- R/W-0 R/W-0 RTCCIP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 RTCCIS<1:0> FSCMIS<1:0> I2C2IS<1:0> U2IS<1:0> Unimplemented: Read as `0' RTCCIP<2:0>: Real-Time Clock Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled RTCCIS<1:0>: Real-Time Clock Interrupt subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 12-10 bit 9-8 DS61143A-page 182 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-16: bit 15-13 bit 12-10 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 (CONTINUED) Unimplemented: Read as `0' I2C2IP<2:0>: I2C2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled I2C2IS<1:0>: I2C2 Interrupt subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' U2IP<2:0>: UART2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled U2IS<1:0>: UART2 subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 183 PIC32MX FAMILY REGISTER 9-17: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-29 bit 28-26 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 DMA0IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 DMA1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 DMA2IP<2:0> R/W-0 R/W-0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 -- U-0 -- R/W-0 R/W-0 DMA3IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 DMA3IS<1:0> DMA2IS<1:0> DMA1IS<1:0> DMA0IS<1:0> Unimplemented: Read as `0' DMA3IP<2:0>: DMA3 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled DMA3IS<1:0>: DMA3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' DMA2IP<2:0>: DMA2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled DMA2IS<1:0>: DMA2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 25-24 bit 23-21 bit 20-18 bit 17-16 DS61143A-page 184 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-17: bit 15-13 bit 12-10 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 (CONTINUED) Unimplemented: Read as `0' DMA1IP<2:0>: DMA1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled DMA1IS<1:0>: DMA1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' DMA0IP<2:0>: DMA0 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled DMA0IS<1:0>: DMA0 Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 bit 7-5 bit 4-2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 185 PIC32MX FAMILY REGISTER 9-18: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' DS61143A-page 186 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 9-19: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-5 bit 4-2 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 FCEIP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 FCEIS<1:0> Unimplemented: Read as `0' FCEIP<2:0>: Flash Control Event Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled FCEIS<1:0>: Flash Control Event Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 187 PIC32MX FAMILY TABLE 9-2: INTERRUPT IRQ AND VECTOR LOCATION Interrupt Source IRQ(1) Highest Natural Order Priority CT - Core Timer Interrupt CS0 - Core Software Interrupt 0 CS1 - Core Software Interrupt 1 INT0 - External Interrupt 0 T1 - Timer1 IC1 - Input Capture 1 OC1 - Output Compare 1 INT1 - External Interrupt 1 T2 - Timer2 IC2 - Input Capture 2 OC2 - Output Compare 2 INT2 - External Interrupt 2 T3 - Timer3 IC3 - Input Capture 3 OC3 - Output Compare 3 INT3 - External Interrupt 3 T4 - Timer4 IC4 - Input Capture 4 OC4 - Output Compare 4 INT4 - External Interrupt 4 T5 - Timer5 IC5 - Input Capture 5 OC5 - Output Compare 5 SPI1E - SPI1 Fault SPI1TX - SPI1 Transfer Done SPI1RX - SPI1 Receive Done U1E - UART1 Error U1RX - UART1 Receiver U1TX - UART1 Transmitter I2C1B - I2C1 Bus Collision Event I2C1S - I2C1 Slave Event I2C1M - I2C1 Master Event CN - Input Change Interrupt AD1 - ADC1 convert done PMP - Parallel Master Port CMP1 - Comparator Interrupt CMP2 - Comparator Interrupt Note 1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 24 24 24 25 25 25 26 27 28 29 30 Synchronous Edge Synchronous Edge Synchronous Edge Edge Edge Synchronous Edge w/Idle Synchronous Edge Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Level Edge Synchronous Edge w/Idle Level Level Vector Number Input Type The "IRQ Number" in Table 9-2 is also the "Interrupt Number" listed in the IFSx, IECx and IPSx register definitions. DS61143A-page 188 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 9-2: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED) Interrupt Source SPI2E - SPI2 Fault SPI2TX - SPI2 Transfer Done SPI2RX - SPI2 Receive Done U2E - UART2 Error U2RX - UART2 Receiver U2TX - UART2 Transmitter I2C2B - I2C2 Bus Collision Event I2C2S - I2C2 Slave Event I2C2M - I2C2 Master Event FSCM - Fail-Safe Clock Monitor RTCC - Real-Time Clock DMA0 - DMA Channel 0 DMA1 - DMA Channel 1 DMA2 - DMA Channel 2 DMA3 - DMA Channel 3 FCE - Flash Control Event (Reserved) Lowest Natural Order Priority Note 1: The "IRQ Number" in Table 9-2 is also the "Interrupt Number" listed in the IFSx, IECx and IPSx register definitions. IRQ(1) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 56 Vector Number 31 31 31 32 32 32 33 33 33 34 35 36 37 38 39 44 Input Type Synchronous Edge Synchronous Edge Synchronous Edge w/ Idle Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Edge Edge Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Edge Edge (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 189 PIC32MX FAMILY 9.2 Operation The interrupt controller is responsible for preprocessing Interrupt Requests (IRQ) from a number of on-chip peripherals and presenting them in the appropriate order to the processor. Figure 9-2 depicts the process within the interrupt controller module. The interrupt controller is designed to receive up to 96 IRQs from the processor core and from on-chip peripherals capable of generating interrupts. All IRQs are sampled on the rising edge of the SYSCLK and latched in associated IFSx registers. A pending IRQ is indicated by the flag bit being equal to `1' in an IFSx register. The pending IRQ will not cause further processing if the corresponding bit in the Interrupt Enable (IECx) register is clear. The IECx bits act to gate the interrupt flag. If the interrupt is enabled, all IRQs are encoded into a 5-bit wide vector number. The 5-bit vector results in 0 to 63 unique interrupt vector numbers. Since there are more IRQs than available vector numbers, some IRQs share common vector numbers. Each vector number is assigned an interrupt priority level and shadow set number. The priority level is determined by the IPCx register setting of the associated vector. In Multi-Vector mode, all priority level 7 interrupts use a dedicated register set, while in Single Vector mode, all interrupts may receive a dedicated shadow set. The interrupt controller selects the highest priority IRQ among all pending IRQs and presents the associated vector number, priority level and shadow set number to the processor core. The processor core samples the presented vector information between the `E' and `M' stage of the pipeline. If the vector's priority level presented to the core is greater than the current priority indicated by the CPU Interrupt Priority bits IPLx (Status<15:10>), the interrupt is serviced; otherwise, it will remain pending until the current priority is less than the interrupt's priority. When servicing an interrupt, the processor core pushes the program counter into the Exception Program Counter (EPC) register in the CPU and sets Exception Level bit EXL (Status<1>) in the CPU. The EXL bit disables further interrupts until the application explicitly reenables them by clearing the EXL bit. Next, it branches to the vector address calculated from the presented vector number. The INTSTAT register contains the Interrupt Vector Number bits, VEC (INTSTAT<5:0>), and Requested Interrupt Priority bits, RIPLx (INTSTAT<10:8>), of the current pending interrupt. This may not be the same as the interrupt which caused the core to diverge from normal execution. The processor returns to the previous state when the ERET (Exception Return) instruction is executed. ERET clears the EXL bit, restores the program counter and reverts the current shadow set to the previous one. The PIC32MX Family interrupt controller can be configured to operate in one of two modes: * Single Vector mode - all interrupt requests will be serviced at one vector address (mode out of Reset). * Multi-Vector mode - interrupt requests will be serviced at the calculated vector address. Notes: While the user can, during run time, reconfigure the interrupt controller from Single Vector to Multi-Vector mode (or vice versa), such action is strongly discouraged. Changing interrupt controller modes after initialization may result in undefined behavior. The M4K core supports several different interrupt processing modes. The interrupt controller is designed to work in External Interrupt Controller mode. DS61143A-page 190 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 9-2: INTERRUPT PROCESS ENCODE LATCH StatusIPL COMPARE GENERATE RIPL > IPL Any Request * Interrupt Request StatusIE Interrupt Exception Vector Number Load Fields IntCtlVS Interrupt Sources Interrupt Module Offset Generator Requested IPL SRSCtlEICSS Shadow Set Number CauseRIPL Exception Vector Offset Shadow Set Number Note: SRSCtl, Cause, Status, and IntCtl registers are CPU registers and are described in Section 2. "CPU". (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 191 PIC32MX FAMILY 9.3 Single Vector Mode On any form of Reset, the interrupt controller initializes to Single Vector mode. When the MVEC (INTCON<12>) bit is `0', the interrupt controller operates in Single Vector mode. In this mode, the CPU always vectors to the same address. Note: Users familiar with MIPS32 Architecture must note that the M4K core in PIC32MX Family is still operating in External Interrupt Controller (EIC) mode. The PIC32MX Family achieves Single Vector mode by forcing all IRQs to use a vector number of 0x00. Because the M4K core in PIC32MX Family always operates in EIC mode, the single vector behavior through "Interrupt Compatibility Mode," as defined by MIPS32 Architecture, is not recommended. To configure the CPU in Single Vector mode, the following CPU registers (IntCtl, Cause, and Status) and INTCON register must be configured as follows: * * * * * * * EBase 00000 VS (IntCtl<9:5>) 00000 IV (Cause<23>) = 1 EXL (Status<1>) = 0 BEV (Status<22>) = 0 MVEC (INTCON<12>) = 0 IE (Status<0>) = 1 EXAMPLE 9-1: /* SINGLE VECTOR MODE INITIALIZATION Set the CP0 registers for multi-vector interrupt Place EBASE at 0xBD000000 This code example uses MPLAB C32 intrinsic functions to access CP0 registers. Check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm("di"); temp = _CP0_GET_STATUS(); temp |= 0x00400000; _CP0_SET_STATUS(temp); _CP0_SET_EBASE(0xBD000000); _CP0_SET_INTCTL(0x00000020); temp = _CP0_GET_CAUSE(); temp |= 0x00800000; _CP0_SET_CAUSE(temp); temp = _CP0_GET_STATUS(); temp &= 0xFFBFFFFD; _CP0_SET_STATUS(temp); INTCONCLR = 0x1000; asm("ei"); // Disable all interrupts // Get Status // Set BEV bit // Update Status // Set an EBase value of 0xBD000000 // Set the Vector Spacing to non-zero value // Get Cause // Set IV // Update Cause // Get Status // Clear BEV and EXL // Update Status // Clear MVEC bit // Enable all interrupts DS61143A-page 192 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 9.4 Multi-Vector Mode When the MVEC (INTCON<12>) bit is `1', the interrupt controller operates in Multi-Vector mode. In this mode, the CPU vectors to the unique address for each vector number. Each vector is located at a specific offset, with respect to a base address specified by the EBase register in the CPU. The individual vector address offset is determined by the vector space that is specified by the VS bits in the IntCtl register. (The IntCtl register is located in the CPU; refer to Section 2.0 of this manual for more information.) To configure the CPU in Multi-Vector mode, the following CPU registers (IntCtl, Cause, and Status) and the INTCON register must be configured as follows: * * * * * * * EBase 00000 VS (IntCtl<9:5>) 00000 IV (Cause<23>) = 1 EXL (Status<1>) = 0 BEV (Status<22>) = 0 MVEC (INTCON<12>) = 1 IE (Status<0>) = 1 EXAMPLE 9-2: /* MULTI-VECTOR MODE INITIALIZATION Set the CP0 registers for multi-vector interrupt Place EBASE at 0xBD000000 and Vector Spacing to 32 bytes This code example uses MPLAB C32 intrinsic functions to access CP0 registers. Check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm("di"); temp = _CP0_GET_STATUS(); temp |= 0x00400000; _CP0_SET_STATUS(temp); _CP0_SET_EBASE(0xBD000000); _CP0_SET_INTCTL(0x00000020); temp = _CP0_GET_CAUSE(); temp |= 0x00800000; _CP0_SET_CAUSE(temp); temp = _CP0_GET_STATUS(); temp &= 0xFFBFFFFD; _CP0_SET_STATUS(temp); INTCONSET = 0x1000; asm("ie"); // Disable all interrupts // Get Status // Set BEV bit // Update Status // Set an EBase value of 0xBD000000 // Set the Vector Spacing to non-zero value // Get Cause // Set IV // Update Cause // Get Status // Clear BEV and EXL // Update Status // Set MVEC bit // Enable all interrupts (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 193 PIC32MX FAMILY 9.5 9.5.1 Interrupt Priorities INTERRUPT GROUP PRIORITY The user is able to assign a group priority to each of the interrupt vectors. The groups' priority level bits are located in the IPCx register. Each IPCx register contains group priority bits for four interrupt vectors. The user-selectable priority levels range from 1 (the lowest priority) to 7 (the highest). If an interrupt priority is set to zero, the interrupt vector is disabled for both interrupt and wake-up purposes. Interrupt vectors with a higher priority level preempt lower priority interrupts. The user must move the Requested Interrupt Priority bit of the Cause register, RIPLx (Cause<15:10>), into the Status register's Interrupt Priority bits, IPLx (Status<15:10>), before re-enabling interrupts. (The Cause and Status registers are located in the CPU; refer to Section 2.0 of this manual for more information.) This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. Note: The Interrupt Service Routine (ISR) must clear the associated interrupt flag in the IFSx register before lowering the interrupt priority level to avoid recursive interrupts. EXAMPLE 9-3: /* SETTING GROUP PRIORITY LEVEL The following code example will set the priority to level 2. Multi-Vector initialization must be performed (See Example 9-2) */ IPC0CLR = 0x0000001C; // clear the priority level IPC0SET = 0x00000008; // set priority level to 2 9.5.2 INTERRUPT SUBPRIORITY The user can assign a subpriority level within each group priority. The subpriority will not cause preemption of an interrupt in the same priority; rather, if two interrupts with the same priority are pending, the interrupt with the highest subpriority will be handled first. The subpriority bits are located in the IPCx register. Each IPCx register contains subpriority bits for interrupt vectors. These bits define the within the priority level of the vector. selectable subpriority levels range from 0 subpriority) to 3 (the highest). four of the subpriority The user(the lowest EXAMPLE 9-4: /* SETTING SUBPRIORITY LEVEL Multi-Vector initialization The following code example will set the subpriority to level 2. must be performed (See Example 9-2) */ IPC0CLR = 0x00000003; IPC0SET = 0x00000002; // clear the subpriority level // set the subpriority to 2 DS61143A-page 194 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 9.6 Interrupt Processing EXAMPLE 9-5: When the priority of a requested interrupt is greater than the current CPU priority, the interrupt request is taken and the CPU branches to the vector address associated with the requested interrupt. Depending on the priority of the interrupt, the prologue and epilogue of the interrupt handler must perform certain tasks before executing any useful code. The following examples provide recommended prologues and epilogues. SINGLE VECTOR INTERRUPT HANDLER PROLOGUE IN ASSEMBLY CODE 9.6.1 INTERRUPT PROCESSING IN SINGLE VECTOR MODE When the interrupt controller is configured in Single Vector mode, all of the interrupt requests are serviced at the same vector address. The interrupt handler routine must generate a prologue and an epilogue to properly configure, save and restore all of the core registers, along with General Purpose Registers. At a worst case, all of the modifiable General Purpose Registers must be saved and restored by the prologue and epilogue. 9.6.1.1 Single Vector Mode Prologue When entering the interrupt handler routine, the interrupt controller must first save the current priority and exception PC counter from Interrupt Priority bits, IPLx (Status<15:10>), and the ErrorEPC register, respectively, on the stack. (Status and ErrorEPC are CPU registers.) If the routine is presented a new register set, the previous register set's stack register must be copied to the current set's stack register. Then, the requested priority may be stored in the IPLx from the Requested Interrupt Priority bits, RIPLx (Cause<15:10>), Exception Level bit, EXL, and Error Level bit, ERL, in the Status register (Status<1> and Status<2>) are cleared and the Master Interrupt Enable bit (Status<0>) is set. Finally, the General Purpose Registers will be saved on the stack. (The Cause and Status registers are located in the CPU.) rdpgpr mfc0 mfc0 srl addiu sw mfc0 sw ins ins mtc0 sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw addu sp, sp k0, Cause k1, EPC k0, k0, 0xa sp, sp, -76 k1, 0(sp) k1, Status k1, 4(sp) k1, k0, 10, 6 k1,zero, 1, 4 k1, Status s8, 8(sp) a0, 12(sp) a1, 16(sp) a2, 20(sp) a3, 24(sp) v0, 28(sp) v1, 32(sp) t0, 36(sp) t1, 40(sp) t2, 44(sp) t3, 48(sp) t4, 52(sp) t5, 56(sp) t6, 60(sp) t7, 64(sp) t8, 68(sp) t9, 72(sp) s8, sp, zero // start interrupt handler code here 9.6.1.2 Single Vector Mode Epilogue After completing all useful code of the interrupt handler routine, the original state of the Status and EPC registers, along with the General Purpose Registers saved on the stack, must be restored. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 195 PIC32MX FAMILY EXAMPLE 9-6: SINGLE VECTOR INTERRUPT HANDLER EPILOGUE IN ASSEMBLY CODE 9.6.2.1 Multi-Vector Mode Prologue // end of interrupt handler code addu lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw di lw mtc0 lw mtc0 eret sp, t9, t8, t7, t6, t5, t4, t3, t2, t1, t0, v1, v0, a3, a2, a1, a0, s8, k0, k0, k0, k0, s8, zero 72(sp) 68(sp) 64(sp) 60(sp) 56(sp) 52(sp) 48(sp) 44(sp) 40(sp) 36(sp) 32(sp) 28(sp) 24(sp) 20(sp) 16(sp) 12(sp) 8(sp) 0(sp) EPC 4(sp) Status When entering the interrupt handler routine, the Interrupt Service Routine (ISR) must first save the current priority and exception PC counter from Interrupt Priority bits, IPL (Status<15:10>), and the ErrorEPC register, respectively, on the stack. If the routine is presented a new register set, the previous register set's stack register must be copied to the current set's stack register. Then, the requested priority may be stored in the IPLx from Requested Interrupt Priority bits, RIPLx (Cause<15:10>), Exception Level bit, EXL, and Error Level bit, ERL, in the Status register (Status<1> and Status<2>) are cleared, and the Master Interrupt Enable bit (Status<0>) is set. If the interrupt handler is not presented a new General Purpose Register set, these resisters will be saved on the stack. (Cause and Status are CPU registers; refer to Section 2.0 of this manual for more information.) EXAMPLE 9-7: PROLOGUE WITHOUT A DEDICATED GENERAL PURPOSE REGISTER SET IN ASSEMBLY CODE 9.6.2 INTERRUPT PROCESSING IN MULTI-VECTOR MODE When the interrupt controller is configured in MultiVector mode, the interrupt requests are serviced at the calculated vector addresses. The interrupt handler routine must generate a prologue and an epilogue to properly configure, save and restore all of the core registers, along with General Purpose Registers. At a worst case, all of the modifiable General Purpose Registers must be saved and restored by the prologue and epilogue. If the interrupt priority is set to receive its own General Purpose Register set, the prologue and epilogue will not need to save or restore any of the modifiable General Purpose Registers, thus providing the lowest latency. rdpgpr mfc0 mfc0 srl addiu sw mfc0 sw ins ins mtc0 sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw addu sp, sp k0, Cause k1, EPC k0, k0, 0xa sp, sp, -76 k1, 0(sp) k1, Status k1, 4(sp) k1, k0, 10, 6 k1,zero, 1, 4 k1, Status s8, 8(sp) a0, 12(sp) a1, 16(sp) a2, 20(sp) a3, 24(sp) v0, 28(sp) v1, 32(sp) t0, 36(sp) t1, 40(sp) t2, 44(sp) t3, 48(sp) t4, 52(sp) t5, 56(sp) t6, 60(sp) t7, 64(sp) t8, 68(sp) t9, 72(sp) s8, sp, zero // start interrupt handler code here DS61143A-page 196 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 9-8: PROLOGUE WITH A DEDICATED GENERAL PURPOSE REGISTER SET IN ASSEMBLY CODE EXAMPLE 9-10: EPILOGUE WITH A DEDICATED GENERAL PURPOSE REGISTER SET IN ASSEMBLY CODE rdpgpr mfc0 mfc0 srl addiu sw mfc0 sw ins ins mtc0 addu sp, sp k0, Cause k1, EPC k0, k0, 0xa sp, sp, -76 k1, 0(sp) k1, Status k1, 4(sp) k1, k0, 10, 6 k1,zero, 1, 4 k1, Status s8, sp, zero // end of interrupt handler code addu di lw mtc0 lw mtc0 eret sp, s8, zero k0, k0, k0, k0, 0(sp) EPC 4(sp) Status // start interrupt handler code here 9.6.2.2 Multi-Vector Mode Epilogue After completing all useful code of the interrupt handler routine, the original state of the Status and ErrorEPC registers, along with the General Purpose Registers saved on the stack, must be restored. (The Status and ErrorEPC registers are located in the CPU; refer to Section 2.0 of this manual for more information.) EXAMPLE 9-9: EPILOGUE WITHOUT A DEDICATED GENERAL PURPOSE REGISTER SET IN ASSEMBLY CODE // end of interrupt handler code addu lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw lw di lw mtc0 lw mtc0 eret sp, s8, zero t9, 72(sp) t8, 68(sp) t7, 64(sp) t6, 60(sp) t5, 56(sp) t4, 52(sp) t3, 48(sp) t2, 44(sp) t1, 40(sp) t0, 36(sp) v1, 32(sp) v0, 28(sp) a3, 24(sp) a2, 20(sp) a1, 16(sp) a0, 12(sp) s8, 8(sp) k0, k0, k0, k0, 0(sp) EPC 4(sp) Status (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 197 PIC32MX FAMILY 9.7 External Interrupts The interrupt controller supports five external interruptrequest signals (INT4-INT0). These inputs are edge sensitive; they require a low-to-high or a high-to-low transition to create an interrupt request. The INTCON register has five bits that select the polarity of the edge detection circuitry: INT4EP (INTCON<4>), INT3EP (INTCON<3>), INT2EP (INTCON<2>), INT1EP (INTCON<1>) and INT0EP (INTCON<0>). Note: Changing the external interrupt polarity may trigger an interrupt request. It is recommended that before changing the polarity, the user disables that interrupt, changes the polarity, clears the interrupt flag and re-enables the interrupt. EXAMPLE 9-11: /* SETTING EXTERNAL INTERRUPT POLARITY The following code example will set INT3 to trigger on a high to low transition edge. The CPU must be set up for either multi or single vector interrupts to handle external interrupts */ IEC0CLR = 0x00008000; // disable INT3 INTCONCLR = 0x00000008; // clear the bit for falling edge trigger IFS0CLR = 0x00008000; // clear the interrupt flag IEC0SET = 0x00008000; // enable INT3 DS61143A-page 198 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 9.8 Temporal Proximity Interrupt Coalescing Temporal proximity interrupt uses the interrupt proximity timer, TPTMR, to create a temporal window in which a group of interrupts of the same, or lower, priority will be held off. The user can activate temporal proximity interrupt coalescing by performing the following steps: * Set the TPCx bit to the preferred priority level. (Setting TPC to zero will disable the proximity timer.) * Load the preferred 32-bit value to TPTMR. The interrupt proximity timer will trigger when an interrupt request of a priority equal, or lower, matches the TPC value. The PIC32MX Family CPU responds to interrupt events as if they are all immediately critical because the interrupt controller asserts the interrupt request to the CPU when the interrupt request occurs. The CPU immediately recognizes the interrupt if the current CPU priority is lower than the pending priority. Entering and exiting an ISR consumes clock cycles for saving and restoring context. Events are asynchronous with respect to the main program and have a limited possibility of occurring simultaneously or close together in time. This prevents the ability of a shared ISR to process multiple interrupts at one time. EXAMPLE 9-12: /* TEMPORAL PROXIMITY INTERRUPT COALESCING EXAMPLE The following code example will set the Temporal Proximity Coalescing to trigger on interrupt priority level of 3 or below and the temporal timer to be set to 0x12345678. */ INTCONCLR = 0x00000700; TPTMPCLR = 0xFFFFFFFF; NTCONSET = 0x00000300; TPTMR = 0x12345678; // // // // clear TPC clear the timer set TPC->3 set the timer to 0x12345678 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 199 PIC32MX FAMILY NOTES: DS61143A-page 200 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 10.0 Note: OSCILLATORS This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. This section describes the PIC32MX Family oscillator system and its operation. The PIC32MX Family oscillator system has the following modules and features: * A total of four external and internal oscillator options as clock sources * On-chip PLL with user-selectable input divider, multiplier, and output divider to boost operating frequency on select internal and external oscillator sources * On-chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown A simplified diagram of the oscillator system is shown in Figure 10-1. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 201 PIC32MX FAMILY FIGURE 10-1: PIC32MX FAMILY CLOCK DIAGRAM Primary Oscillator (POSC) OSCI OSCO XT, HS, EC Peripherals div x FIN PLL div y XTPLL, HSPLL, ECPLL, FRCPLL Postscaler div x PBCLK FRC Oscillator 8 MHz typical TUN<5:0> PLL Input Divider FPLLIDIV<2:0> COSC<2:0> PLL Output Divider PLLODIV<2:0> PBDIV<1:0> PLL Multiplier FPLLMULT<2:0> PLLMULT<2:0> FRC FRC /16 CPU, Peripherals div 16 Postscaler FRCDIV FRCDIV<2:0> LPRC Oscillator LPRC 32 kHz typical Secondary Oscillator SOSCO 32.768 kHz SOSCEN and FSOSCEN SOSCI Clock Control Logic Fail-Safe Clock Monitor FSCM INT FSCM Event SOSC NOSC<2:0> COSC<2:0> OSWEN FSCMEN<1:0> WDT, PWRT Timer1, RTCC DS61143A-page 202 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 10.1 Control Registers The Oscillator module consists of the following Special Function Registers (SFRs): * OSCCON: Control Register for the Oscillator module OSCCONCLR, OSCCONSET, OSCCONINV: Atomic Bit Manipulation Write-only Registers for OSCCON register * OSCTUN: FRC Tuning Register for the Oscillator module OSCTUNCLR, OSCTUNSET, OSCTUNINV: Atomic Bit Manipulation Write-only Registers for OSCTUN register The Oscillator module also has associated bits for interrupt control: the following * Interrupt Flag Status bits (IFS1<14>) for Clock Fail FSCMIF in IFS1 Interrupt register * Interrupt Enable Control bits (IEC1<14>) for Clock Fail FSCMIE in IEC1 Interrupt register * Interrupt Priority Control bits (FSCMIP<12:10>) for Clock Fail in IPC8 Interrupt register * Interrupt Subpriority Control bits (FSCMIP<9:8>) for Clock Fail in IPC8 Interrupt register The following tables provide brief summaries of Oscillator-module-related registers. Corresponding registers appear after the summaries, followed by a detailed description of each register. TABLE 10-1: Virtual Address BF80_F000 Name OSCILLATORS SFR SUMMARY Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- -- CLKLOCK -- Bit 30/22/14/6 -- SOSCRDY -- COSC<2:0> SLOCK SLPEN Bit 29/21/13/5 Bit Bit 28/20/12/ 27/19/11/ 4 3 Bit 26/18/10/2 Bit 25/17/9/1 FRCDIV<2:0> PLLMULT<2:0> NOSC<2:0> -- SOSCEN OSWEN Bit 24/16/8/0 OSCCON PLLODIV<2:0> PBDIV<1:0> -- CF BF80_F004 BF80_F008 BF80_F00C BF80_F010 OSCCONCLR OSCCONSET OSCCONINV OSCTUN 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears selected bits in OSCCON, read yields undefined value Write sets selected bits in OSCCON, read yields undefined value Write inverts selected bits in OSCCON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TUN<5:0> -- -- -- -- -- -- BF80_F014 BF80_F018 BF80_F01C BF80_0000 OSCTUNCLR OSCTUNSET OSCTUNINV WDTCON 31:0 31:0 31:0 -- -- 15:8 ON -- Write clears selected bits in OSCTUN, read yields undefined value Write sets selected bits in OSCTUN, read yields undefined value Write inverts selected bits in OSCTUN, read yields undefined value -- -- -- -- -- -- -- -- -- WDTPS<4:0> -- -- -- -- -- -- -- -- -- -- -- -- -- WDTCLR BF80_0004 BF80_0008 BF80_000C BF88_1040 BF88_1070 BF88_1110 WDTCONCLR WDTCONSET WDTCONINV IFS1 IEC1 IPC8 31:0 31:0 31:0 15:8 15:8 23:16 31:24 23:16 15:8 7:0 RTCCIF RTCCIE -- -- FWDTEN Write clears selected bits in WDTCON, read yields an undefined value Write sets selected bits in WDTCON, read yields an undefined value Write inverts selected bits in WDTCON, read yields an undefined value FSCMIF FSCMIE -- -- -- I2C2MIF I2C2MIE -- -- -- FPBDIV<1:0> FSOSCEN -- -- -- FPLLMULT<2:0> -- -- -- -- -- -- -- -- -- -- -- -- I2C2SIF I2C2SIE -- -- -- I2C2BIF I2C2BIE U2TXIF U2TXIE FSCMIP<2:0> -- FWDTPS<4:0> OSCIOFNC POSCMD<1:0> FNOSC<2:0> -- FPLLODIV<2:0> -- FPLLIDIV<2:0> -- -- -- U2RXIF U2RXIE U2EIF U2EIE FSCMIS<1:0> -- BFC0_2FF8 DEVCFG1 FCKSM<1:0> IESO -- -- -- -- -- -- -- -- BFC0_2FF4 DEVCFG2 31:24 23:16 15:8 7:0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 203 PIC32MX FAMILY REGISTER 10-1: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 CLKLOCK bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-30 bit 29-27 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) r-0 -- R-0 SLOCK R/W-0 SLPEN R/W-0 CF r-0 -- R/W-0 SOSCEN R-0 R-0 COSC<2:0> R-0 U-0 -- R/W-x R/W-x NOSC<2:0> bit 8 R/W-0 OSWEN bit 0 R-0 SOSCRDY U-0 -- R/W-x R/W-x R/W-x R/W-x PLLMULT<2:0> bit 16 R/W-x OSCCON: OSCILLATOR CONTROL REGISTER U-0 -- R/W-x R/W-x PLLODIV<2:0> R/W-x R/W-0 R/W-0 FRCDIV<2:0> bit 24 R/W-x R/W-1 PBDIV<1:0> Unimplemented: Read as `0' PLLODIV<2:0>: Output Divider for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 Note: On Reset these bits are set to the value of the FPLLODIV Configuration bits (DEVCFG2<18:16>). FRCDIV<2:0>: Fast Internal RC Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 Unimplemented: Maintain as `0' SOSCRDY: Secondary Oscillator Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary oscillator is either turned off or is still warming up Unimplemented: Read as `0' bit 26-24 bit 23 bit 22 bit 21 DS61143A-page 204 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 10-1: bit 20-19 OSCCON: OSCILLATOR CONTROL REGISTER PBDIV<1:0>: Peripheral Bus Clock Divisor bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note: Initial value is loaded from DEVCFG1<13:12>. PLLMULT<2:0>: PLL Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 Note: On Reset these bits are set to the value of the FPLLMULT Configuration bits (DEVCFG2<6:4>). Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON.FRCDIV 110 = Fast Internal RC Oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast RC Oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON.FRCDIV 110 = Fast Internal RC Oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast Internal RC Oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If FSCM is enabled (FCKSM1 =1): 1 = Clock and PLL selections are locked. 0 = Clock and PLL selections are not locked and may be modified If FSCM is disabled (FCKSM1 =0): Note: Clock and PLL selections are never locked and may be modified. Reserved: Maintain as `0' SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed bit 18-16 bit 15 bit 14-12 bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 205 PIC32MX FAMILY REGISTER 10-1: bit 3 OSCCON: OSCILLATOR CONTROL REGISTER CF: Clock Fail Detect bit 1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure 0 = No clock failure has been detected Reserved: Maintain as `0' SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete bit 2 bit 1 bit 0 DS61143A-page 206 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 10-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31:6 bit 5-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- OSCTUN: FRC TUNING REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 TUN<5:0> Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits 011111 =Maximum frequency. 011110 = * 000001 = 000000 =Center frequency. Oscillator runs at calibrated frequency. 111111 = * 100001 = 100000 =Minimum frequency. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 207 PIC32MX FAMILY REGISTER 10-3: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-x R-x R-x WDTPS<4:0> R-x R-x r-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-1 -- R-1 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 -- bit 8 R/W-0 WDTCLR bit 0 ON: Watchdog Timer Enable bit 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software Note 1: A read of this bit will result in a `1' if the WDT is enabled by the device configuration or by software. 2: The LPRC oscillator will automatically be enabled when this bit is set. Note: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. DS61143A-page 208 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 10-4: U-0 -- bit 31 r-0 -- bit 23 R/W-0 RTCCIF bit 15 R/W-0 SPI2RXIF bit 7 Legend: R = Readable bit U = Unimplemented bit bit 14 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF r-0 -- r-0 -- r-0 -- R/W-0 DMA3IF R/W-0 DMA2IF R/W-0 DMA1IF IFS1: INTERRUPT FLAG STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- r-0 -- R/W-0 FCEIF bit 24 R/W-0 DMA0IF bit 16 R/W-0 U2EIF bit 8 R/W-0 CNIF bit 0 FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit 1 = Interrupt request has occured 0 = No interrupt request has a occurred Note: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 209 PIC32MX FAMILY REGISTER 10-5: U-0 -- bit 31 r-0 -- bit 23 R/W-0 RTCCIE bit 15 R/W-0 SPI2RXIE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 14 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE r-0 -- r-0 -- r-0 -- R/W-0 DMA3IE R/W-0 DMA2IE R/W-0 DMA1IE IEC1: INTERRUPT ENABLE CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- r-0 -- R/W-0 FCEIE bit 24 R/W-0 DMA0IE bit 16 R/W-0 U2EIE bit 8 R/W-0 CNIE bit 0 FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. DS61143A-page 210 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 10-6: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 12-10 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 I2C2IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 FSCMIP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 RTCCIP<2:0> R/W-0 R/W-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 -- U-0 -- R/W-0 R/W-0 DMA0IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 DMA0IS<1:0> RTCCIS<1:0> FSCMIS<1:0> I2C2IS<1:0> FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 9-8 Note: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 211 PIC32MX FAMILY REGISTER 10-7: r-1 -- bit 31 R/P-1 FWDTEN bit 23 R/P-1 bit 15 R/P-1 IESO bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-14 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) r-1 -- R/P-1 FSOSCEN r-1 -- r-1 -- R/P-1 FNOSC2 R/P-1 FNOSC1 R/P-1 R/P-1 R/P-1 r-1 -- R/P-1 OSCIOFNC R/P-1 R/P-1 -- r-1 -- R/P-1 FWDTPS4 R/P-1 FWDTPS3 R/P-1 FWDTPS2 R/P-1 FWDTPS1 DEVCFG1 BOOT CONFIGURATION REGISTER r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 R/P-1 FWDTPS0 bit 16 R/P-1 bit 8 R/P-1 FNOSC0 bit 0 FCKSM<1:0> FPBDIV<1:0> POSCMD<1:0> Unimplemented: Maintain `1' FCKSM<1:0>: Fail-safe Clock Monitor (FSCM) and Clock Switch Configuration bits 1x = FSCM and Clock Switching are disabled 01 = Clock Switching is enabled, FSCM is disabled 00 = Clock Switching and FSCM are enabled FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Unimplemented: Maintain as `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or = 00) 0 = CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator Disabled 10 = HS mode 01 = XT Mode 00 = EC Mode IESO: Internal External Clock Switchover Select bit 1 = Internal External Clock Switchover mode enabled; Two-Speed Start-up mode 0 = Internal External Clock Switchover mode disabled; Single-Speed Start-up mode FSOSCEN: Secondary Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 13-12 bit 11 bit 10 bit 9-8 bit 7 bit 5 DS61143A-page 212 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 10-7: bit 2-0 DEVCFG1 BOOT CONFIGURATION REGISTER FNOSC<2:0>: CPU Clock Oscillator Select bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRC Divided by 16 (FRCDIV16) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, or ECPLL) 010 = Primary Oscillator without PLL (XT, HS, or EC) 001 = Fast RC Oscillator with PLL 000 = Fast RC Oscillator (FRC) (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 213 PIC32MX FAMILY REGISTER 10-8: r-1 -- bit 31 r-1 -- bit 23 r-1 -- bit 15 U-1 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 18-16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/P-1 R/P-1 FPLLMULT<2:0> R/P-1 U-1 -- R/P-1 R/P-1 FPLLIDIV<2:0> bit 0 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FPLLODIV<2:0> bit 16 r-1 -- bit 8 R/P-1 DEVCFG2 BOOT CONFIGURATION REGISTER r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 R/P-1 FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 (default setting) FPLLMULT<2:0>: Default PLL Multiplier Value bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier FPLLIDIV<2:0>: Default PLL Input Divider Value bits 111 = Divide by 12 110 = Divide by 10 101 = Divide by 6 100 = Divide by 5 011 = Divide by 4 010 = Divide by 3 001 = Divide by 2 000 = Divide by 1 bit 6-4 bit 2-0 DS61143A-page 214 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 10.2 Operation: Clock Generation and Clock Sources Each of the clock sources has unique configurable options, such as a PLL, input divider, and/or output divider, that are detailed in their respective sections. There are up to four internal clocks depending on the specific device. The clocks are derived from the currently selected oscillator source. Note: Clock sources for peripherals that use external clocks, such as the RTC and Timer1, are covered in their respective sections. The PIC32MX device has two internal clocks: CPU clock and PB clock. They are derived from the currently selected clock source. The clock source can be chosen from the 4 available internal or external clock sources. Some of these clock sources have Phase Locked Loops (PLLs), programmable output dividers, or input divider to scale the input frequency to suit the application. The clock source can be changed on the fly by software. The oscillator control register is locked by hardware, it must be unlocked by a series of writes before software can perform a clock switch. There are two main clocks in the PIC32MX Family device * The System clock (SYSCLK) used by CPU and some peripherals * The Peripheral Bus Clock (PBCLK) used by most peripherals The PIC32MX Family clocks are derived from one of the following sources: * Primary Oscillator (POSC) on the OSCI and OSCO pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins * Internal Fast RC Oscillator (FRC) * Internal Low-Power RC Oscillator (LPRC) 10.2.1 SYSTEM CLOCK (SYSCLK) GENERATION The SYSCLK is the primary clock used by the CPU and select peripherals such as DMA, Interrupt Controller, and Prefetch Cache. The SYSCLK is derived from one of the four clock sources: POSC, SOSC, FRC, and LPRC. Some of the clock sources have specific clock multipliers and/or divider options. No clock scaling is applied other than the user specified values. The SYSCLK source is selected by the device configuration and can be changed by software during operation. The ability to switch clock sources during operation allows the application to reduce power consumption by reducing the clock speed. Refer to Table 10-2 for a list of SYSCLK sources. TABLE 10-2: CLOCK SELECTION CONFIGURATION BIT VALUES Oscillator Mode Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Primary Internal Internal POSCMD<1:0> xx xx xx xx 10 01 00 10 01 00 10 xx FNOSC2: FNOSC0 111 110 101 100 011 011 011 010 010 010 001 000 1 1 Notes 1, 2 1 1 1 3 3 3 Fast RC Oscillator with Postscaler (FRCDIV) Fast RC Oscillator divided by 16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary (Timer1/RTCC) Oscillator (SOSC) Primary Oscillator (HS) with PLL Module (HSPLL) Primary Oscillator (XT) with PLL Module (XTPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL Module (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: 3: OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When the pin is not required by the Oscillator mode it may be configured for one of these options. Default Oscillator mode for an unprogrammed (erased) device. When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 215 PIC32MX FAMILY 10.2.1.1 Primary Oscillator (POSC) The POSC has six operating modes, as summarized in Table 10-3. The first three modes can each be combined with a PLL module to form the last three modes. Figures 10-2 through 10-4 show various POSC configurations. The primary oscillator is connected to the OSCI and OSCO pins of the device family. The primary oscillator can be configured for an external clock input or an external crystal or resonator. The XT, XTPLL, HS, and HSPLL modes are External Crystal or Resonator Controller Oscillator modes. The XT and HS modes are functionally very similar. The primary difference is the gain of the internal inverter of the oscillator circuit (see Figure 10-2). The XT mode is a medium power, medium frequency mode and has medium inverter gain. HS mode is higher power and provides the highest oscillator frequencies and has the highest inverter gain. OSCO provides crystal/resonator feedback in both XT and HS Oscillator modes and hence is not available for use as a input or output in these modes. The XTPLL and HSPLL modes have a Phase Locked Loop (PLL) with user selectable input divider, multiplier, and output divider to provide a wide range of output frequencies. The oscillator circuit will consume more current when the PLL is enabled. The External Clock modes, EC and ECPLL, allow the system clock to be derived from an external clock source. These modes configure the OSCI pin as a high-impedance input that can be driven by a CMOS driver. The external clock can be used to drive the system clock directly (EC) or the ECPLL module with prescale and postscaler can be used to change the input clock frequency (ECPLL). The External Clock modes also disables the internal feedback buffer allowing the OSCO pin to be used for other functions. In the External Clock mode the OSCO pin can be used as an additional device I/O pin (see Figure 10-4) or a PBCLK output pin (see Figure 10-3). Note: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. TABLE 10-3: HS XT EC HSPLL XTPLL ECPLL PRIMARY OSCILLATOR OPERATING MODES Description 10 MHz-40 MHz crystal 3.5 MHz-10 MHz resonator External clock input (0-72 MHz) 10 MHz-40 MHz crystal, PLL enabled 4 MHz-10 MHz resonator, PLL enabled External clock input (5-72 MHz), PLL enabled Oscillator Mode Note: The clock applied to the CPU after applicable prescalers, postscalers, and PLL multipliers must not exceed the maximum allowable processor frequency. FIGURE 10-2: CRYSTAL OR CERAMIC RESONATOR OPERATION (XT, XTPLL, HS, OR HSPLL OSCILLATOR MODE) To Internal Logic OSCI C1(3) XTAL OSCO C2(3) RS(1) RF(2) Enable PIC32MX Note 1: 2: 3: A series resistor, Rs, may be required for AT strip cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 M. Refer to the "PIC32MX Family Reference Manual" (DS61132) for help determining the best oscillator components. DS61143A-page 216 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 10-3: EXTERNAL CLOCK INPUT OPERATION WITH CLOCK-OUT (EC, ECPLL MODE) 10.2.1.2 Primary Oscillator (POSC) Configuration To configure the POSC the following steps should be performed: 1. Select POSC as the default oscillator in the device Configuration register, DEVCFG1, by setting FNOSC<2:0> = `010' without PLL or `011' with PLL. Select the desired mode HS, XT, or EC, using POSCMD<1:0> in DEVCFG1. If the PLL is to be used: a)Select the appropriate Configuration bits for the PLL input divider to scale the input frequency to be between 4 MHz and 5 MHz using FPLLIDIV<2:0> in DEVCFG2. b)Select the desired PLL multiplier ratio using FPLLMULT<2:0>) in DEVCFG2. c)At runtime, select the desired PLL output divider using PLLODIV (OSCCON<29:27>) to provide the desired clock frequency. The default value is set by DEVCFG1. Clock from Ext. System PBCLK OSCI PIC32MX OSCO (Clock Out) 2. 3. FIGURE 10-4: EXTERNAL CLOCK INPUT OPERATION WITH NO CLOCK-OUT (EC, ECPLL MODE) OSCI PIC32MX I/O I/O (OSCO) Clock from Ext. System (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 217 PIC32MX FAMILY 10.2.1.3 Oscillator Start-up Timer 10.2.1.4 In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer (OST) is provided. The OST is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. This time-out period is designated as TOST. The amplitude of the oscillator signal must reach the VIL and VIH thresholds for the oscillator pins before the OST can begin to count cycles. The TOST interval is required every time the oscillator has to restart (i.e., on POR, BOR and wake-up from Sleep mode). The Oscillator Start-up Timer is applied to the MS and HS modes for the primary oscillator, as well as the secondary oscillator, see Section 10.2.1.5 "Secondary Oscillator (SOSC)". System Clock Phase Locked Loop (PLL) The system clock PLL provides a user configurable input divider, multiplier, and output divider which can be used with the XT, HS and EC Primary Oscillator modes and with the Internal Fast RC Oscillator (FRC) mode to create a variety of clock frequencies from a single clock source. The Input divider, multiplier, and output divider control initial value bits are contained in the in the DEVCFG2 device Configuration register. The multiplier and output divider bits are also contained in the OSCCON register. As part of a device Reset, values from the device Configuration register, DEVCFG2, are copied to the OSCCON register. This allows the user to preset the input divider to provide the appropriate input frequency to the PLL and set an initial PLL multiplier when programming the device. At runtime the multiplier, divider and output divider can be changed by software to scale the clock frequency to suit the application. The PLL input divider cannot be changed at run time. This is to prevent applying an input frequency outside the specified limits to the PLL. To configure the PLL the following steps are required: 1. 2. Calculate the PLL input divider, PLL multiplier, and PLL output divider values. Set the PLL input divider and the initial PLL multiplier value in the DEVCFG2 register when programming the part. At runtime the PLL multiplier and PLL output divider can be changed to suit the application. 3. Combinations of PLL input divider, multiplier and output divider provide a combined multiplier of approximately 0.006 to 24 times the input frequency. For reliable operation the output of the PLL module must not exceed the maximum clock frequency of the device. The PLL input divider value should be chosen to limit the input frequency to the PLL to the range of 4 MHz to 5 MHz. Due to the time required for the PLL to provide a stable output, a Status bit SLOCK (OSCCON<5>) is provided. When the clock input to the PLL is changed, this bit is driven low (`0'). After the PLL has achieved a lock or the PLL start-up timer has expired, the bit is set. The bit will be set upon the expiration of the timer even if the PLL has not achieved a lock. DS61143A-page 218 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 10-4: NET MULTIPLIER OUTPUT FOR SELECTED PLL AND OUTPUT DIVIDER VALUES Net PLLODIV Multiplier Postscaler Multiplication <2:0> factor PLLMUL T <2:0> Net PLLODIV PLLMULT Multiplier Postscaler Multiplication <2:0> <2:0> factor 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 15 16 17 18 19 20 21 24 7.5 8 8.5 9 9.5 10 10.5 12 3.75 4 4.25 4.5 4.75 5 5.25 6 1.875 2 2.125 2.250 2.375 2.5 2.625 3 `000' `000' `000' `000' `000' `000' `000' `000' `001' `001' `001' `001' `001' `001' `001' `001' `010' `010' `010' `010' `010' `010' `010' `010' `011' `011' `011' `011' `011' `011' `011' `011' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 15 16 17 18 19 20 21 24 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 64 64 64 64 64 64 64 64 256 256 256 256 256 256 256 256 .938 1 1.063 1.125 1.188 1.250 1.313 1.5 .4688 .5 .5313 .5625 .5938 .6250 .6563 .7500 .234 .250 .266 .281 .297 .313 .328 .375 .05859 .06250 .06641 .07031 .07422 .07813 .08203 .09375 `100' `100' `100' `100' `100' `100' `100' `100' `101' `101' `101' `101' `101' `101' `101' `101' `110' `110' `110' `110' `110' `110' `110' `110' `111' `111' `111' `111' `111' `111' `111' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 219 PIC32MX FAMILY 10.2.1.4.1 PLL Lock Status The SLOCK bit (OSCCON<5>) is a read-only Status bit that indicates the lock status of the PLL. It is automatically set after the typical time delay for the PLL to achieve lock, also designated as TLOCK. If the PLL does not stabilize properly during start-up, SLOCK may not reflect the actual status of PLL lock, nor does it detect when the PLL loses lock during normal operation. The SLOCK bit is cleared at a Power-on Reset and on clock switches when the PLL is selected as a destination clock source. It remains clear when any clock source not using the PLL is selected. Refer to the Electrical Characteristics section in the specific device data sheet for further information on the PLL lock interval. 10.2.1.4.2 Primary Oscillator Start-up from Sleep Mode To ensure reliable wake-up from Sleep, care must be taken to properly design the primary oscillator circuit. This is because the load capacitors have both partially charged to some quiescent value and phase differential at wake-up is minimal. Thus, more time is required to achieve stable oscillation. Remember also that lowvoltage, high temperatures and the lower frequency clock modes also impose limitations on loop gain, which in turn, affects start-up. Each of the following factors increases the start-up time: * Low-frequency design (with a Low Gain Clock mode) * Quiet environment (such as a battery operated device) * Operating in a shielded box (away from the noisy RF area) * Low voltage * High temperature * Wake-up from Sleep mode 10.2.1.5 Secondary Oscillator (SOSC) The Secondary Oscillator (SOSC) is designed specifically for low-power operation with a external 32.768 kHz crystal. The oscillator is located on the SOSCO and SOSCI device pins and serves as a secondary crystal clock source for low-power operation. It can also drive Timer1 and/or the Real-Time Clock/Calendar module for Real-Time Clock applications. 10.2.1.5.1 Enabling the SOSC Oscillator The SOSC is hardware enabled by the FSOSCEN Configuration bit (DEVCFG1<5>). Once SOSC is enabled, software can control it by modifying SOSCEN bit (OSCCON<1>). Setting SOSCEN enables the oscillator; the SOSCO and SOSCI pins are controlled by the oscillator and cannot be used for port I/O or other functions. Note: An unlock sequence is required before a write to OSCCON can occur. Refer to Section 10.2.5.2 "Oscillator Switching Sequence" for more information. The Secondary Oscillator requires a warm-up period before it can be used as a clock source. When the oscillator is enabled, a warm-up counter increments to 1024. When the counter expires the SOSCRDY (OSCCON<22>) is set to `1'. 10.2.1.5.2 SOSC Continuous Operation The SOSC is always enabled when SOSCEN (OSCCON<1>) is set. Leaving the oscillator running at all times allows a fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still require an oscillator start-up time if it is a crystal type source and/or uses the PLL. In addition, the oscillator will need to remain running at all times for Real-Time Clock applications and may be required for Timer1. EXAMPLE 10-1: ENABLING THE SOSC // // // // ensure OSCCON Write Key1 to Write Key2 to OSCCON is now is locked SYSKEY SYSKEY unlocked SYSKEY = 0x12345678; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONSET = 2; // make the desired change // request clock switch // Relock the SYSKEY // Write any value other than Key1 or Key2 SYSKEY = 0x12345678; DS61143A-page 220 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 10.2.1.6 Internal Fast RC Oscillator (FRC) 10.2.1.7.1 Enabling the LPRC Oscillator Since it serves the PWRT clock source, the LPRC oscillator is disabled at Power-on Reset whenever the on-board voltage regulator is enabled. After the PWRT expires, the LPRC oscillator will remain on if any one of the following is true: * The Fail-Safe Clock Monitor is enabled. * The WDT is enabled. * The LPRC oscillator is selected as the system clock (COSC2:COSC0 = 100). If none of the above is true, the LPRC will shut off after the PWRT expires. The FRC oscillator is a fast (8 MHz nominal), user trimmable, internal RC oscillator with user selectable input divider, PLL multiplier, and output divider. 10.2.1.6.1 FRC Postscaler Mode (FRCDIV) Users are not limited to the nominal 8 MHz FRC output if they wish to use the fast internal oscillator as a clock source. An additional FRC mode, FRCDIV, implements a selectable output divider that allows the choice of a lower clock frequency from 7 different options, plus the direct 8 MHz output. The output divider is configured using the FRCDIV<2:0> bits (OSCCON<26:24>). Assuming a nominal 8 MHz output, available lower frequency options range from 4 MHz (divide-by-2) to 31 kHz (divide-by-256). The range of frequencies allows users the ability to save power at any time in an application by simply changing the FRCDIV bits. The FRCDIV mode is selected whenever the COSC bits (OSCCON<14:12>) are `111'. 10.2.1.6.2 FRC Oscillator with PLL Mode (FRCPLL) The output of the FRC may also be combined with a user selectable PLL multiplier and output divider to produce a SYSCLK across a wide range of frequencies. The FRC PLL mode is selected whenever the COSC bits (OSCCON<14:12>) are `001'. In this mode, the PLL input divider is forced to `2' to provide a 4 MHz input to the PLL. The desired PLL multiplier and output divider values can be chosen to provide the desired device frequency 10.2.1.6.3 Oscillator Tune Register (OSCTUN) The FRC Oscillator Tuning register OSCTUN allows the user to fine tune the FRC oscillator over a range of approximately 12% (typical). Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount. 10.2.2 PERIPHERAL BUS CLOCK (PBCLK) GENERATION The PBCLK is derived from the System Clock (SYSCLK) divided by PBDIV<1:0> (OSCCON<20:19>). The PBCLK Divisor bits PBDIV<1:0> allow postscalers of 1:1, 1:2, 1:4, and 1:8. Refer to the individual peripheral module section(s) for information regarding which bus a specific peripheral uses. Notes: When the PBDIV divisor is set to a ratio of `1:1' the SYSCLK and PBCLK are equivalent in frequency. The PBCLK frequency is never greater than the processor clock frequency. The effect of changing the PBCLK frequency on individual peripherals should be taken into account when selecting or changing the PBDIV value. Performing back-to-back operations on PBCLK peripheral registers when the PB divisor is not set at 1:1 will cause the CPU to stall for a number of cycles. This stall occurs to prevent an operation from occurring before the pervious one has completed. The length of the stall is determined by the ratio of the CPU and PBCLK and synchronizing time between the two busses. Changing the PBCLK frequency has no effect on the SYSCLK peripherals operation. 10.2.1.7 Internal Low-Power RC Oscillator (LPRC) The LPRC oscillator is separate from the FRC. It oscillates at a nominal frequency of 31.25 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail Safe Clock Monitor (FSCM) and PLL reference circuits. It may also be used to provide a low-frequency clock source option for the device in those applications where power consumption is critical, and timing accuracy is not required. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 221 PIC32MX FAMILY 10.2.3 TWO-SPEED START-UP cleared to cancel any pending clock switches. To enable FSCM the following steps should be performed: 1. Enable the FSCM in the device Configuration register, DEVCFG1, by configuring the FCKSM<1:0> bits to `00'. 01 = Clock Switching is enabled, FSCM is disabled 00 = Clock Switching and FSCM are enabled Select the desired mode HS, XT, or EC using FNOSC<2:0> in DEVCFG1. Select POSC as the default oscillator in the device Configuration register, DEVCFG1 by configuring FNOSC<2:0> = 010 without PLL or `011' with PLL. 1. Select the appropriate Configuration bits for the PLL input divider to scale the input frequency to be between 4 MHz and 5 MHz using FPLLIDIV<2:0> (DEVCFG2<2:0>). Select the desired PLL multiplier using FPLLMULT<2:0> (DEVCFG2<6:4>). Select the desired PLL output divider using FPLLODIV<2:0> (DEVCFG2<18:16>). Two-Speed Start-up mode can be used to reduce the device start-up latency when using all External Crystal POSC modes, including PLL. Two-Speed Start-up uses the FRC clock as the SYSCLK source until the Primary Oscillator (POSC) has stabilized. After the user selected oscillator has stabilized, the clock source will switch to POSC. This allows the CPU to begin running code, at a lower speed, while the oscillator is stabilizing. When the POSC has met the start-up criteria an automatic clock switch occurs to switch to POSC. This mode is enabled by the device Configuration bits FCKSM<1:0> (DEVCFG1<15:14>). Two-Speed Startup operates after a Power-on Reset (POR) or exit from SLEEP. Software can determine the oscillator source currently in use by reading the COSC<2:0> bits in the OSCCON register. Note: The Watchdog Timer (WDT), if enabled, will continue to count at the same rate regardless of the SYSCLK frequency. Care must be taken to service the WDT during Two-Speed Start-up, taking into account the change in SYSCLK. 2. 3. If the PLL is to be used: 2. 3. 10.2.4 FAIL-SAFE CLOCK MONITOR OPERATION The Fail-Safe Clock Monitor (FSCM) is designed to allow continued device operation if the current oscillator fails. It is intended for use with the Primary Oscillator (POSC) and automatically switches to the FRC oscillator if a POSC failure is detected. The switch to the Fast Internal RC Oscillator (FRC) oscillator allows continued device operation and the ability to retry the POSC or to execute code appropriate for a clock failure. The FSCM mode is controlled by the FCKSM<1:0> bits in the device Configuration register, DEVCFG1. Any of the POSC modes can be used with FSCM. When a clock failure is detected with FSCM enabled and the FSCM Interrupt Enable bit FSCMIE (IEC1<14>) set, the clock source will be switched from POSC to FRC. An Oscillator Fail interrupt will be generated, with the CF bit (OSCCON<3>) set. This interrupt has a user settable priority FSCMIP<2:0> (IPC8<12:10>) and subpriority FSCMIS<1:0> (IPC8<9:8>). The clock source will remain FRC until a device Reset or a clock switch is performed. Failure to enable the FSCM interrupt will not inhibit the actual clock switch. The FSCM module takes the following actions when switching to the FRC oscillator: 1. 2. 3. The COSC bits (OSCCON<14:12>) are loaded with `000'. The CF OSCCON<3> bit is set to indicate the clock failure The OSWEN control bit (OSCCON<0>) is If a FSCM interrupt is desired when a FSCM event occurs, the following steps should be performed during start-up code: 1. 2. Clear the FSCM interrupt (IFS1<14>). bit FSCMIF Set the Interrupt priority FSCMIP<2:0> (IPC8<12:10>) and subpriority FSCMIS<1:0> (IPC8<9:8>). Set the FSCM Interrupt Enable bit FSCMIE (IEC1<14>) The Watchdog Timer, if enabled, will continue to count at the same rate regardless of the SYSCLK frequency. Care must be taken to service the WDT after a Fail-Safe Clock Monitor event, taking into account the change in SYSCLK. 3. Note: DS61143A-page 222 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 10.2.4.1 FSCM Delay Note: On a POR, BOR or wake from Sleep mode event, a nominal delay (TFSCM) may be inserted before the FSCM begins to monitor the system clock source. Refer to Section 8.0 "Resets" for FSCM delay timing information. The TFSCM interval is applied whenever the FSCM is enabled and the HS, HSPLL, XT, XTPLL, or SOSC Oscillator modes are selected as the system clock. Note: Please refer to the Electrical Characteristics section for TFSCM specification values. The device does not prevent changing the PLL postscaler or multiplier values on the clock source that is in use. The device will not permit direct switching between PLL clock sources. The user should not change the PLL multiplier values or postscaler values when running from the affected PLL source. To perform either of the above clock switching functions, the clock switch should be performed in two steps. The clock source should first be switched to a non-PLL source, such as FRC, and then switched to the desired source. This requirement only applies to PLL-based clock sources. 10.2.4.2 FSCM and Slow Oscillator Start-up 10.2.5.1 A slow oscillator start-up will not generate a FSCM event. The FSCM does not begin monitoring until the source to be monitored is running. If the oscillator does not start-up the device will not run due to the lack of a clock source. To detect the failure and prevent this the user should use Two-Speed Start-Up to allow the device to run using the FRC oscillator while the POSC oscillator starts up. The COSC<2:0> bits can then be polled to test for the clock switch to POSC. Refer to Section 10.2.3 "Two-Speed Start-up" for further information. Enabling Clock Switching To enable clock switching, the FCKSM1 Configuration bit (DEVCFG1<15>) must be programmed to `0'. If the FCKSM1 Configuration bit is unprogrammed (= 1), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times. 10.2.4.3 FSCM and Slow Clock Sources Use of the FSCM with slow clock sources (below 100 kHz) is not recommended. Slow clock sources may cause the FSCM to incorrectly detect a clock failure event. 10.2.4.4 FSCM and WDT 10.2.5.2 Oscillator Switching Sequence The FSCM and the WDT both use the LPRC oscillator as their time base. In the event of a clock failure, the WDT is unaffected and continues to run. At a minimum, performing a clock switch requires the following sequence: 1. If desired, read the COSC<2:0> bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register. The unlock sequence has critical timing requirements and should be performed with interrupts and DMA disabled. Write the appropriate value to the NOSC<2:0> control bits (OSCCON<10:8>) for the new oscillator source. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. Optionally perform the lock sequence to lock the OSCCON. The lock sequence must be performed separately from any other operation. 10.2.5 CLOCK SWITCHING OPERATION With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC32MX Family devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD Configuration bits in DEVCFG1. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. 2. 3. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC<2:0> Status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 223 PIC32MX FAMILY 2. and the clock switch is aborted. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the Oscillator Start-up timer (OST) expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (SLOCK = 1). The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC Status bits. The old clock source is turned off at this time if the clock is not being used by any modules. Note: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 10.2.5.3 Clock Switching Considerations When incorporating clock switching into an application, users should keep certain things in mind when designing their code. * The SYSLOCK unlock sequence is timing critical. The two Key values must be written back-to-back with no in-between peripheral register access. To prevent unintended peripheral register accesses, it is recommended that all interrupts and DMA transfers are disabled. * The system will not relock automatically. The user should perform the relock sequence as soon after the clock switch as is possible. * The unlock sequence unlocks other registers such as the those related to Real-Time Clock control. * If the destination clock source is a crystal oscillator, the clock switch time will be dictated by the oscillator start-up time. * If the new clock source does not start, or is not present, the OSWEN bit will remain set. * A clock switch to a different frequency will affect the clocks to peripherals. Peripherals may require reconfiguration to continue operation at the same rate as they did before the clock switch occurred. * If the new clock source uses the PLL, a clock switch will not occur until lock has been achieved. * If the WDT is used, care must be taken to ensure it can be serviced in a timely manner at the new clock rate. Note: The application should not attempt to switch to a clock with a frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. Clock switching in these instances may generate a false oscillator fail event and result in a switch to the Internal Fast RC oscillator. The device does not prevent changing the PLL postscaler or multiplier values on the clock source that is in use. The device will not permit direct switching between PLL clock sources. The user should not change the PLL multiplier values or postscaler values when running from the affected PLL source. To perform either of the above clock switching functions, the clock switch should be performed in two steps. The clock source should first be switched to a non-PLL source, such as FRC, and then switched to the desired source. This requirement only applies to PLL-based clock sources. 3. 4. The following is a recommended code sequence for a clock switch: 1. 2. Disable interrupts and DMA prior to the system unlock sequence. Execute the system unlock sequence by writing the Key values of 0xAA996655 and 0x556699AA to the SYSKEY register in two back-to-back assembly or `C' instructions. Write the new oscillator source value to the NOSC control bits. Set the OSWEN bit in the OSCCON register to initiate the clock switch. Write a non-key value (such as 0x12345678) to the SYSKEY register to perform a lock. Continue to execute code that is not clock-sensitive (optional). Check to see if OSWEN is `0'. If it is, the switch was successful. Loop until the bit is `0'. Re-enable interrupts and DMA. Notes: There are no timing requirements for the steps other than the initial back-to-back writing of the Key values to perform the unlock sequence. The unlock sequence unlocks all registers that are secured by the lock function. It is recommended that amount to time is the system is unlock is kept to a minimum. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 10-2. 3. 4. 5. 6. 7. Note: DS61143A-page 224 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 10-2: PERFORMING A CLOCK SWITCH // // // // // // // // // write invlid key to force lock Write Key1 to SYSKEY Write Key2 to SYSKEY OSCCON is now unlocked make the desired change This can be in `C' or assembly clear the PLL multiplier bits set he new PLL multiplier value request clock switch SYSKEY = 0x12345678; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONCLR = 111 << 16; OSCCONSET = 101 << 16; OSCCONSET = 1; SYSKEY = 0x12345678; // Relock the SYSKEY // Write any value other than Key1 or Key2 // OSCCON is relocked 10.2.5.4 Entering Sleep Mode During a Clock Switch If the device enters Sleep mode during a clock switch operation, the clock switch operation is aborted. The processor keeps the old clock selection and the OSWEN bit (OSCCON<0>) is cleared. The WAIT instruction is then executed normally. used as SYSCLK, such as after a clock switch, it cannot be disabled by writing to the SOSCEN bit. If the SOSC is enabled by the SOSCEN bit, it will continue to operate when the device is in SLEEP. To prevent inadvertent clock changes the OSCCON register is locked. It must be unlocked prior to software enabling or disabling the SOSC. 10.2.5.5 SOSC Control 10.3 Input/Output Pins The SOSC can be used by modules as well as the CPU, therefore, the SOSC is controlled by a combination of software and hardware. Setting the SOSCEN bit (OSCCON<1>) to a `1' enables the SOSC. The SOSC is disabled when it is not being used by the CPU module and the SOSCEN bit is `0'. If the SOSC is being The pins used by the POSC and SOSC are shared by other peripherals modules. Table shows the function of these shared pins in the available oscillator modes. When the pins are not used by a oscillator they are available for use as general I/O pins or by use by a peripheral sharing the pin. . TABLE 10-5: Pin Name OSCI OSCO OSCI OSCO OSCO OSCO N/A N/A N/A N/A SOSCI SOSCO Note 1: CONFIGURATION OF PINS ASSOCIATED WITH THE OSCILLATOR MODULE Clock Mode HS, HSPLL, XT, XTPLL HS, HSPLL, XT, XTPLL EC, ECPLL EC, ECPLL EC, ECPLL EC, ECPLL Configuration Bit FIeld(1) COSC<2:0>, POSCMD<1:0> COSC<2:0>, POSCMD COSC<2:0>, POSCMD COSC<2:0>, POSCMD, OSCOFNC COSC<2:0>, POSCMD, OSCOFNC COSC<2:0>, POSCMD, OSCOFNC COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> TRIS X X X X INPUT OUTPUT X X X X X X Pin Type OSC OSC CLOCK IN PBCLK OUT INPUT OUTPUT GPIO GPIO GPIO GPIO OSC OSC FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC SOSC SOSC During device start-up, the device oscillator configuration data is copied from device configuration to COSC. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 225 PIC32MX FAMILY 10.3.1 OSCI AND OSCO PIN FUNCTIONS IN NON-EXTERNAL OSCILLATOR MODES When the primary oscillator (POSC) on OSCI and OSCO is not configured as a clock source the OSCI pin is automatically reconfigured as a digital I/O. In this configuration, as well as when the primary oscillator is configured for EC mode (POSCMD1:POSCMD0 = 00), the OSCO pin can also be configured as a digital I/O by programming the OSCIOFCN Configuration bit. When OSCIOFCN is unprogrammed (`1'), a PBCLK is available on OSCO for testing or synchronization purposes. With OSCIOFCN programmed (`0'), the OSCO pin becomes a general purpose I/O pin. In both of these configurations, the feedback device between OSCI and OSCO is turned off to save current. 10.3.2 SOSCI AND SOCI PIN FUNCTIONS IN NON-EXTERNAL OSCILLATOR MODES When the secondary oscillator (SOSC) on SOSCI and SOSCO pin is not configured as a clock source the pins are automatically reconfigured as a digital I/O. DS61143A-page 226 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 11.0 Note: POWER SAVING This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 11.2 CPU Halted Methods The device supports two power-saving modes, SLEEP and IDLE, both of which halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC IDLE Mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC IDLE Mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC IDLE Mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. * LPRC IDLE Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * SLEEP Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in SLEEP using specific clock sources. This is the lowest power mode for the device. This section describes power saving for the PIC32MX family. The PIC32MX family devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power saving is controlled by software. 11.1 Power Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules. These methods are grouped into the following categories: * FRC RUN mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC RUN mode: the CPU is clocked from the LPRC clock source. * SOSC RUN mode: the CPU is clocked from the SOSC clock source. * Peripheral Bus Scaling mode: Peripherals are clocked at programmable fraction of the CPU clock (SYSCLK). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 227 PIC32MX FAMILY 11.3 Power-Saving Modes Control Registers Power-Saving modes control consists of the following Special Function Registers (SFRs): * OSCCON: Control Register for the Oscillators Module OSCCONCLR, OSCCONSET, OSCCONINV: Atomic Bit Manipulation Write-only Registers for OSCCON * WDTCON: Control Register for the Watchdog Timer Module WDTCONCLR, WDTCONSET, WDTCONINV: Atomic Bit Manipulation Write-only Registers for WDTCON * RCON: Control Register for the Resets Module RCONCLR, RCONSET, RCONINV: Atomic Bit Manipulation Write-only Registers for RCON The following table summarizes Power-Saving modes registers. Corresponding registers appear after the summary, followed by a detailed description of each register. TABLE 11-1: Virtual Address POWER-SAVING MODES SFR SUMMARY Name 31:24 23:16 15:8 7:0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- -- CLKLOCK -- -- SOSCRDY -- COSC<2:0> SLOCK SLPEN PLLODIV<2:0> PBDIV<1:0> -- CF -- RCDIV<2:0> PLLMULT<2:0> NOSC<2:0> SOSCEN OSWEN Bit 24/16/8/0 BF80_F000 OSCCON BF80_F004 OSCCONCLR 31:0 BF80_F008 OSCCONSET 31:0 BF80_F00C OSCCONINV BF80_0000 WDTCON 31:0 31:24 23:16 15:8 7:0 BF80_0004 WDTCONCLR 31:0 BF80_0008 WDTCONSET 31:0 BF80_000C WDTCONINV BF80_F600 RCON 31:0 31:24 23:16 15:8 7:0 BF80_F604 RCONCLR BF80_F608 RCONSET BF80_F60C RCONINV 31:0 31:0 31:0 -- -- -- EXTR -- -- ON -- Write clears selected bits in OSCCON, read yields undefined value Write sets selected bits in OSCCON, read yields undefined value Write inverts selected bits in OSCCON, read yields undefined value -- -- -- -- -- -- -- -- -- SWDTPS<4:0> -- -- -- -- -- -- -- -- -- -- -- -- -- WDTCLR Write clears selected bits in WDTCON; read yields undefined value Write sets selected bits in WDTCON; read yields undefined value Write inverts selected bits in WDTCON; read yields undefined value -- -- -- SWR -- -- -- -- -- -- -- WDTO -- -- -- SLEEP -- -- -- IDLE -- -- CM BOR -- -- VREGS POR Write clears selected bits in RCON; read yields undefined value Write sets selected bits in RCON; read yields undefined value Write inverts selected bits in RCON; read yields undefined value DS61143A-page 228 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 11-1: U-0 -- bit 31 R/W-0 DRMEN bit 23 U-0 -- bit 15 R/W-0 CLKLOCK bit 7 Legend: R = Readable bit U = Unimplemented bit bit 29-27 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- R-0 SLOCK R/W-0 SLPEN R/W-0 CF U-0 -- R/W-0 SOSCEN R-0 R-0 COSC<2:0> R-0 U-0 -- R/W-x R/W-x NOSC<2:0> bit 8 R/W-0 OSWEN bit 0 R-0 SOSCRDY U-0 -- R/W-x R/W-x R/W-x R/W-x PLLMULT<2:0> bit 16 R/W-x OSCCON: OSCILLATOR CONTROL REGISTER U-0 -- R/W-x R/W-x PLLODIV<2:0> R/W-x R/W-x R/W-x FRCDIV<2:0> bit 24 R/W-x R/W-x PBDIV<1:0> PLLODIV<2:0>: Output Divider for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 Note: On Reset these bits are set to the value of the FPLLODIV Configuration bits (DEVCFG2<18:16>) FRCDIV<2:0>: Fast Internal RC Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 DRMEN: Dream Mode Enable bit 1 = DMA transfer completion puts device back into SLEEP mode, if the DMA was triggered while device was in SLEEP mode 0 = DMA transfer completion has no effect on SLEEP mode SOSCRDY: Secondary Oscillator Ready Indicator bit 1 = Indicates that the secondary oscillator is running and is stable 0 = Secondary oscillator is either turned off or is still warming up Unimplemented: Read as `0' bit 26-24 bit 23 bit 22 bit 21 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 229 PIC32MX FAMILY REGISTER 11-1: bit 20-19 OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) PBDIV<1:0>: Peripheral Bus Clock Divisor bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note: Initial value is loaded from DEVCFG1<13:12> PLLMULT<2:0>: PLL Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 Note: On Reset these bits are set to the value of the PLLMULT Configuration bits (DEVCFG2<6:4>) Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits 111 = Fast internal RC oscillator divided by OSCCON.RCDIV 110 = Fast internal RC oscillator divided by 16 101 = Low-Power Internal RC oscillator (LPRC) 100 = Secondary oscillator (SOSC) 011 = Primary oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary oscillator (XT, HS or EC) 001 = Fast RC oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast RC oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits 111 = Fast internal RC oscillator divided by OSCCON.RCDIV 110 = Fast internal RC oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary oscillator (SOSC) 011 = Primary oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary oscillator (XT, HS or EC) 001 = Fast Internal RC oscillator with PLL module via postscaler (FRCPLL) 000 = Fast internal RC oscillator (FRC) On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified Unimplemented: Read as `0' SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: SLEEP Mode Enable bit 1 = Device will enter SLEEP mode when a WAIT instruction is executed 0 = Device will enter IDLE mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure 0 = No clock failure has been detected bit 18-16 bit 15 bit 14-12 bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 DS61143A-page 230 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 11-1: bit 2 bit 1 OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) Unimplemented: Read as `0' SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 231 PIC32MX FAMILY REGISTER 11-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit U = Unimplemented bit bit 3 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SWR U-0 -- R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-0 BOR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CM U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- RCON: RESETS CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 VREGS bit 8 R/W-0 POR bit 0 SLEEP: Wake from Sleep bit 1 = The device woke up from SLEEP mode 0 = The device did not wake from SLEEP mode Note: Must clear this bit to detect future wake-ups from SLEEP. IDLE: Wake from IDLE bit 1 = The device woke up from IDLE mode 0 = The device did not wake from IDLE mode Note: Must clear this bit to detect future wake-ups from IDLE. bit 2 DS61143A-page 232 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 11-3: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 SWDTPS<4:0> R-0 R-0 r-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 WDTCLR bit 0 ON: Watchdog Peripheral On bit 1 = Watchdog peripheral is enabled. The status of other bits in the register are not affected by setting this bit. The LPRC oscillator will not be disabled when entering Sleep. 0 = Watchdog peripheral is disabled and not drawing current. SFR modifications are allowed. The status of other bits in this register are not affected by clearing this bit. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 233 PIC32MX FAMILY 11.4 Note: Power-Saving Operation In this data sheet, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 11.5 SLEEP Mode SLEEP mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in SLEEP mode and can be used to wake the device from SLEEP. See the individual peripheral module sections for descriptions of behavior in Sleep. SLEEP mode includes the following characteristics: * The CPU is halted. * The system clock source is typically shut down. See Section 11.5.1 "Oscillator Shutdown In Sleep Mode" for specific information. * There can be a wake-up delay based on the oscillator selection (refer to Table 11-2). * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit, if enabled, remains operative during SLEEP mode. * The WDT, if enabled, is not automatically cleared prior to entering SLEEP mode. * Some peripherals can continue to operate in SLEEP mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART, and peripherals that use an external clock input or the internal LPRC oscillator, e.g., RTCC and Timer 1. * I/O pins continue to sink or source current in the same manner as they do when the device is not in SLEEP. * Some modules can be individually disabled by software prior to entering SLEEP in order to further reduce consumption. The processor will exit, or `wake-up', from SLEEP on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset. * On a WDT time-out. See Section 11.10 "Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI)". If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter into IDLE mode. Refer Example 11-1 for example code. Note: There is no FRZ mode for this module. The purpose of all power saving is to reduce power consumption by reducing the device clock frequency. To achieve this, low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption. DS61143A-page 234 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 11.5.1 OSCILLATOR SHUTDOWN IN SLEEP MODE 11.5.2 CLOCK SELECTION ON WAKE-UP FROM SLEEP The criteria for the device disabling the clock source in SLEEP are: the oscillator type, peripherals using the clock source, and (for select sources) the clock enable bit. * If the CPU clock source is POSC, it is turned off in SLEEP. See Table 11-2 for applicable delays when waking from SLEEP. * If the CPU clock source is FRC, it is turned off in SLEEP. See Table 11-2 for applicable delays when waking from SLEEP. * If the CPU clock source is SOSC, it will be turned off if the SOSCEN bit is not set. See Table 11-2 for applicable delays when waking from SLEEP. * If the CPU clock source is LPRC, it will be turned off if the clock source is not being used by a peripheral that will be operating in SLEEP, such as the WDT. See Table 11-2 for applicable delays when waking from SLEEP. The processor will resume code execution and use the same clock source that was active when SLEEP mode was entered. The device is subject to a start-up delay if a crystal oscillator and/or PLL is used as a clock source when the device exits SLEEP. 11.5.3 DELAY ON WAKE-UP FROM SLEEP The oscillator start-up and Fail-Safe Clock Monitor delays (if enabled) associated with waking up from SLEEP mode are shown in Table 11-2. TABLE 11-2: DELAY TIMES FOR EXIT FROM SLEEP MODE Clock Source EC, EXTRC EC + PLL XT + PLL XT, HS, XTL LP (OFF during Sleep) LP (ON during Sleep) FRC, LPRC Oscillator Delay -- TLOCK TOST + TLOCK TOST TOST -- -- FSCM Delay -- TFSCM TFSCM TFSCM TFSCM -- -- Note: Please refer to the "Electrical Specifications" section of the PIC32MX family device data sheet for TPOR, TFSCM and TLOCK specification values. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 235 PIC32MX FAMILY 11.5.4 WAKE-UP FROM SLEEP MODE WITH CRYSTAL OSCILLATOR OR PLL 11.5.5 FAIL-SAFE CLOCK MONITOR DELAY AND SLEEP MODE The Fail-Safe Clock Monitor (FSCM) does not operate while the device is in SLEEP. If the FSCM is enabled it will resume operation when the device wakes from Sleep. If the system clock source is derived from a crystal oscillator and/or the PLL, then the Oscillator Start-up Timer (OST) and/or PLL lock times will be applied before the system clock source is made available to the device. As an exception to this rule, no oscillator delays are applied if the system clock source is the POSC oscillator and it was running while in SLEEP mode. Note: In spite of the various delays applied the crystal oscillator (and PLL) may not be up and running at the end of the TOST, or TLOCK delays. For proper operation the user must design the external oscillator circuit such that reliable oscillation will occur within the delay period. 11.5.6 SLOW OSCILLATOR START-UP When an oscillator starts slowly, the OST and PLL lock times may not have expired before FSCM times out. If the FSCM is enabled, then the device will detect this condition as a clock failure and a clock event trap will occur. The device will switch to the FRC oscillator and the user can re-enable the crystal oscillator source in the clock failure Interrupt Service Routine. If the FSCM is not enabled, then the device will simply not start executing code until the clock is stable. From the user's perspective, the device will appear to be in SLEEP until the oscillator clock has started. EXAMPLE 11-1: PUT DEVICE IN SLEEP, THEN WAKE WITH WDT // Code example to put the Device in sleep and then Wake the device // with the WDT OSCCONSET = 0x10; WDTCONCLR = 0x0002; WDTCONSET = 0x8000; // set Power-Saving mode to Sleep // Disable WDT window mode // Enable WDT // WDT timeout period is set in the device configuration while (1) { ... user code ... WDTCONSET = 0x01; asm ( "wait" ); // service the WDT // put device in selected Power-Saving mode // code execution will resume here after wake ... user code ... } // The following code fragment is at the beginning of the `C' start-up code if ( RCON & 0x18 ) { asm ( "eret" ); } // The WDT caused a wake from Sleep // return from interrupt DS61143A-page 236 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 11.6 Peripheral Bus Scaling Method 11.6.1 Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. DYNAMIC PERIPHERAL BUS SCALING METHOD The PBCLK can be scaled dynamically, by software, to save additional power when the device is in a low activity mode. The following issues need to be taken into account when scaling the PBCLK: * All the peripherals clocked from PBCLK will scale at the same ratio, at the same time. This needs to be accounted in peripherals which need to maintain a constant baud rate, or pulse period even in low-power modes. * Any communication through a peripheral on the peripheral bus that is in progress when the PBCLK changes may cause a data or protocol error due to a frequency change during transmission or reception. The following steps are recommended if the user intends to scale the PBCLK divisor dynamically: * Disable all communication peripherals whose baud rate will be affected. Care should be taken to ensure that no communication is currently in progress before disabling the peripherals as it may result in protocol errors. * Update the Baud Rate Generator (BRG) settings for peripherals as required for operation at the new PBCLK frequency. * Change the peripheral bus ratio to the desired value. * Enable all communication peripherals whose baud rate were affected. Note: Modifying the peripheral baud rate is done by writing to the associated peripheral SFRs. To minimize latency, the peripherals should be modified in the mode where the PBCLK is running at its highest frequency. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 237 PIC32MX FAMILY EXAMPLE 11-2: CHANGING THE PB CLOCK DIVISOR // Code example to change the PBCLK divisor // This example is for a device running at 40 MHz // Make sure that there is no UART send/receive in progress ... user code ... U1BRG = 0x81; ... user code ... OSCCONCLR = 0x3 << 19; // set baud rate for UART1 for 9600 // set PB divisor to minimum (1:1) ... user code ... // Change Peripheral Clock value U1BRG = 0x0F; OSCCONSET = 0x3 << 19; // set baud rate for UART1 for 9600 based on // new PB clock frequency // set PB divisor to maximum (1:8) // Reset Peripheral Clock OSCCONCLR = 0x3 << 19; U1BRG = 0x81; // set PB divisor to minimum (1:1) // restore baud rate for UART1 to 9600 based // on new PB clock frequency DS61143A-page 238 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 11.7 IDLE Modes In the IDLE modes, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is halted. Peripherals can be individually configured to halt when entering IDLE by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active. Notes: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio. Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and or oscillator startup/lock delays would be applied. The device enters IDLE mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed. The processor will wake or exit from IDLE mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in IDLE mode. * On any source of device Reset. * On a WDT time-out interrupt. See Section 11.10 "Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI)" and Section 26.0 "Watchdog Timer". (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 239 PIC32MX FAMILY TABLE 11-3: PLACING DEVICE IN IDLE AND WAKING BY ADC EVENT // Code example to put the Device in Idle and then Wake the device // when the ADC completes a conversion OSCCONCLR = 0x10; asm ( "wait" ); // set Power-Saving mode to Idle // put device in selected Power-Saving mode // code execution will resume here after wake and the ISR is complete ... user code ... // interrupt handler __ADC1Interrupt: ... ISR code ... asm ( "eret" ); // return from interrupt 11.8 Interrupts There are two sources of interrupts that will wake the device from a Power-Saving mode: peripheral interrupts, and a Non-Maskable Interrupt (NMI) generated by the WDT in Power-Saving mode. Notes: A peripheral with an interrupt priority setting of zero cannot wake the device. Any applicable oscillator start-up delays are applied before the CPU resumes code execution. 11.9 Wake-Up from SLEEP or IDLE on Peripheral Interrupt Any source of interrupt that is individually enabled using the corresponding IE control bit in the IECx register and is operational in the current Power-Saving mode will be able to wake-up the processor from SLEEP or IDLE mode. When the device wakes, one of two events will occur, based on the interrupt priority: * If the assigned priority for the interrupt is less than, or equal to, the current CPU priority, the CPU will remain halted and the device enters, or remains in, IDLE mode. * If the assigned priority level for the interrupt source is greater than the current CPU priority, the device will wake-up and the CPU will jump to the corresponding interrupt vector. Upon completion of the ISR, the CPU will start executing the next instruction after WAIT. The IDLE Status bit (RCON<2>) is set upon wake-up from IDLE mode. The SLEEP Status bit (RCON<3>) is set upon wake-up from SLEEP mode. DS61143A-page 240 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 11.10 Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI) When the WDT times out in SLEEP or IDLE mode, an NMI is generated. The NMI causes the CPU code execution to jump to the device Reset vector. Although the CPU executes the Reset vector, it is not a device Reset, peripherals and most CPU registers do not change their states. Note: Any applicable oscillator start-up delays are applied before the CPU resumes code execution. 11.11 Interrupts Coincident with Power-Saving Instruction Any peripheral interrupt that coincides with the execution of a WAIT instruction will be held off until entry into SLEEP or IDLE mode has completed. The device will then wake-up from SLEEP or IDLE mode. 11.12 I/O Pins Associated with Power-Saving Modes No device pins are associated with Power-Saving modes. To detect a wake from a Power-Saving mode caused by WDT expiration, the WDTO (RCON<4>), SLEEP (RCON<3>), and IDLE (RCON<2>) bits must be tested. If the WDTO bit is `1' the event was due to a WDT time-out. The SLEEP and IDLE bits can then be tested to determine if the WDT event occurred in Sleep or Idle. To use a WDT time-out during SLEEP mode as a wake-up interrupt, a return from interrupt (ERET) instruction must be used in the start-up code after the event was determined to be a WDT wake-up. This will cause code execution to continue from the instruction following the WAIT instruction that put the device in Power-Saving mode. Note: If a peripheral interrupt and WDT event occur simultaneously, or in close proximity, the NMI may not occur, due to the device being awakened by the peripheral interrupt. To avoid unexpected WDT Reset in this scenario, the WDT is automatically cleared when the device awakens. See Section 26.0 "Watchdog Timer" for detailed information on the WDT operation. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 241 PIC32MX FAMILY NOTES: DS61143A-page 242 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 12.0 Note: I/O PORTS This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. Following are some of the key features of this module: * Individual output pin open-drain enable/disable * Individual input pin weak pull-up enable/disable * Monitor selective inputs and generate interrupt when change in pin state is detected * Operation during CPU Sleep and Idle modes * Fast bit manipulation using CLR, SET and INV registers Figure 12-1 shows a block diagram of a typical I/O port, whereas Figure 12-2 shows a block diagram of a typical multiplexed I/O port. The general purpose I/O pins can be considered the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL PORT STRUCTURE Dedicated Port Module RD ODC Data Bus PBCLOCK WR ODC RD TRIS D CK EN Q Q ODC I/O Cell 0 1 D CK EN WR TRIS D CK WR LAT WR PORT RD LAT EN Q TRIS Q Q LAT Q I/O pin 1 RD PORT Sleep PBCLOCK 0 Q Q D CK Q Q D CK Synchronization (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 243 PIC32MX FAMILY FIGURE 12-2: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus PBCLOCK WR ODC RD TRIS D CK EN Q Q ODC 1 0 0 1 IO Cell D CK EN WR TRIS D CK WR LAT WR PORT RD LAT EN Q TRIS Q 1 0 Output Multiplexers Q LAT Q IO Pin 1 RD PORT Sleep PBCLOCK 0 Q Q D CK Q Q D CK Synchronization Peripheral Input R Peripheral Input Buffer Notes: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than what is shown here. Legend: R = Peripheral input buffer types may vary. Refer to the specific PIC32MX data sheet for peripheral details. DS61143A - page 244 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 12.1 Port Registers PORTA SFR SUMMARY Name TRISA 31:24 23:16 15:8 7:0 BF88_6004 BF88_6008 BF88_600C BF88_6010 TRISACLR TRISASET TRISAINV PORTA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_6014 BF88_6018 BF88_601C BF88_6020 PORTACLR PORTASET PORTAINV LATA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_6024 BF88_6028 BF88_602C BF88_6030 LATACLR LATASET LATAINV ODCA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_6034 BF88_6038 BF88_603C ODCACLR ODCFASET ODCAINV 31:0 31:0 31:0 -- -- ODCA15 -- -- LATA15 -- -- RA15 Bit 31/23/15/7 TABLE 12-1: Virtual Address BF88_6000 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- TRISA15 -- -- TRISA14 -- -- -- -- -- -- -- -- -- -- -- TRISA10 -- -- TRISA9 -- -- -- TRISA<7:0> Write clears selected bits in TRISA, read yields undefined value Write sets selected bits in TRISA, read yields undefined value Write inverts selected bits in TRISA, read yields undefined value -- -- RA14 -- -- -- -- -- -- RA<7:0> Write clears selected bits in PORTA, read yields undefined value Write sets selected bits in PORTA, read yields undefined value Write inverts selected bits in PORTA, read yields undefined value -- -- LATA14 -- -- -- -- -- -- -- -- -- -- -- LATA10 -- -- LATA9 -- -- -- -- -- -- -- -- RA10 -- -- RA9 -- -- -- LATA<7:0> Write clears selected bits in LATA, read yields undefined value Write sets selected bits in LATA, read yields undefined value Write inverts selected bits in LATA, read yields undefined value -- -- ODCA14 -- -- -- -- -- -- -- -- -- -- -- ODCA10 -- -- ODCA9 -- -- -- ODCA<7:0> Write clears selected bits in ODCA, read yields undefined value Write sets selected bits in ODCA, read yields undefined value Write inverts selected bits in ODCA, read yields undefined value Note: TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as `0'. (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 245 PIC32MX FAMILY TABLE 12-2: Virtual Address BF88_6040 PORTB SFR SUMMARY Name TRISB 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISB<15:8> TRISB<7:0> Write clears selected bits in TRISB, read yields undefined value Write sets selected bits in TRISB, read yields undefined value Write inverts selected bits in TRISB, read yields undefined value -- -- -- -- -- -- -- -- RB<7:0> Write clears selected bits in PORTB, read yields undefined value Write sets selected bits in PORTB, read yields undefined value Write inverts selected bits in PORTB, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_6044 BF88_6048 BF88_604C BF88_6050 TRISBCLR TRISBSET TRISBINV PORTB 31:0 31:0 31:0 31:24 23:16 15:8 7:0 RB<15:8> BF88_6054 BF88_6058 BF88_605C BF88_6060 PORTBCLR PORTBSET PORTBINV LATB 31:0 31:0 31:0 31:24 23:16 15:8 7:0 LATB<15:8> LATB<7:0> Write clears selected bits in LATB, read yields undefined value Write sets selected bits in LATB, read yields undefined value Write inverts selected bits in LATB, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_6064 BF88_6068 BF88_606C BF88_6070 LATBCLR LATBSET LATBINV ODCB 31:0 31:0 31:0 31:24 23:16 15:8 7:0 ODCB<15:8> ODCB<7:0> Write clears selected bits in ODCB, read yields undefined value Write sets selected bits in ODCB, read yields undefined value Write inverts selected bits in ODCB, read yields undefined value BF88_6074 BF88_6078 BF88_607C ODCBCLR ODCBSET ODCBINV 31:0 31:0 31:0 DS61143A - page 246 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 12-3: Virtual Address BF88_6080 PORTC SFR SUMMARY Name TRISC 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- TRISC15 -- -- -- TRISC14 -- -- -- TRISC13 -- -- -- TRISC12 -- -- -- -- -- -- -- -- -- -- -- -- -- TRISC4(1) TRISC3(1) TRISC2(1) TRISC1(1) BF88_6084 BF88_60088 BF88_6088C BF88_6090 TRISCCLR TRISCSET TRISCINV PORTC 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- RC15 -- Write clears selected bits in TRISC, read yields undefined value Write sets selected bits in TRISC, read yields undefined value Write inverts selected bits in TRISC, read yields undefined value -- -- RC14 -- -- -- RC13 -- -- -- RC12 RC4(1) -- -- -- RC3(1) -- -- -- RC2(1) -- -- -- RC1(1) -- -- -- -- BF88_6094 BF88_6098 BF88_609C BF88_60A0 PORTCCLR PORTCSET PORTCINV LATC 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- LATC15 -- Write clears selected bits in PORTC, read yields undefined value Write sets selected bits in PORTC, read yields undefined value Write inverts selected bits in PORTC, read yields undefined value -- -- LATC14 -- -- -- LATC13 -- -- -- LATC12 LATC4 (1) -- -- -- LATC3 (1) -- -- -- LATC2 (1) -- -- -- LATC1 (1) -- -- -- -- BF88_60A4 BF88_60A8 BF88_60AC BF88_60B0 LATCCLR LATCSET LATCINV ODCC 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- ODCC15 -- Write clears selected bits in LATC, read yields undefined value Write sets selected bits in LATC, read yields undefined value Write inverts selected bits in LATC, read yields undefined value -- -- ODCC14 -- -- -- ODCC13 -- -- -- ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- -- ODCC4(1) ODCC3(1) ODCC2(1) ODCC1(1) BF88_60B4 BF88_60B8 BF88_60BC Note 1: ODCCCLR ODCCSET ODCCINV 31:0 31:0 31:0 Write clears selected bits in ODCC, read yields undefined value Write sets selected bits in ODCC, read yields undefined value Write inverts selected bits in ODCC, read yields undefined value TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as `0'. (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 247 PIC32MX FAMILY TABLE 12-4: Virtual Address BF88_60C0 PORTD SFR SUMMARY Name TRISD 31:24 23:16 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:8 TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1) TRISD<7:0> BF88_60C4 TRISDCLR 31:0 BF88_60C8 TRISDSET 31:0 BF88_60CC TRISDINV BF88_60D0 PORTD 31:0 31:24 23:16 15:8 7:0 BF88_60D4 PORTDCLR 31:0 BF88_60D8 PORTDSET 31:0 BF88_60DC PORTDINV 31:0 BF88_60E0 LATD 31:24 23:16 15:8 7:0 BF88_60E4 BF88_60E8 BF88_60EC BF88_60F0 LATDCLR LATDSET LATDINV ODCD 31:0 31:0 31:0 31:24 23:16 7:0 BF88_60F4 ODCDCLR 31:0 BF88_60F8 ODCDSET BF88_60FC ODCDINV Note 1: 31:0 31:0 -- -- -- -- LAT15(1) -- -- RD15(1) TRISD<11:8> Write clears selected bits in TRISD, read yields undefined value Write sets selected bits in TRISD, read yields undefined value Write inverts selected bits in TRISD, read yields undefined value -- -- RD14(1) -- -- RD13(1) -- -- RD12(1) RD<7:0> Write clears selected bits in PORTD, read yields undefined value Write sets selected bits in PORTD, read yields undefined value Write inverts selected bits in PORTD, read yields undefined value -- -- LAT14(1) -- -- LAT13(1) -- -- LAT12(1) LATD<7:0> Write clears selected bits in LATD, read yields undefined value Write sets selected bits in LATD, read yields undefined value Write inverts selected bits in LATD, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RD<11:8> -- -- -- LATD<11:8> 15:8 ODCD15(1) ODCD14(1) ODCD13(1) ODCD12(1) ODCD<7:0> ODCD<11:8> Write clears selected bits in ODCD, read yields undefined value Write sets selected bits in ODCD, read yields undefined value Write inverts selected bits in ODCD, read yields undefined value TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as `0'. DS61143A - page 248 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 12-5: Virtual Address BF88_6100 PORTE SFR SUMMARY Name TRISE 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISE9(1) TRISE8(1) TRISE<7:0> Write clears selected bits in TRISE, read yields undefined value Write sets selected bits in TRISE, read yields undefined value Write inverts selected bits in TRISE, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- RE<7:0> Write clears selected bits in PORTE, read yields undefined value Write sets selected bits in PORTE, read yields undefined value Write inverts selected bits in PORTE, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATE9(1) -- -- LATE8(1) -- -- -- -- -- -- -- -- RE9 (1) BF88_6104 BF88_6108 BF88_610C BF88_6110 TRISECLR TRISESET TRISEINV PORTE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- RE8(1) BF88_6114 BF88_6118 BF88_611C BF88_6120 PORTECLR PORTESET PORTEINV LATE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 LATE<7:0> Write clears selected bits in LATE, read yields undefined value Write sets selected bits in LATE, read yields undefined value Write inverts selected bits in LATE, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF88_6124 BF88_6128 BF88_612C BF88_6130 LATECLR LATESET LATEINV ODCE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 ODCE9(1) ODCE8(1) ODCE<7:0> Write clears selected bits in ODCE, read yields undefined value Write sets selected bits in ODCE, read yields undefined value Write inverts selected bits in ODCE, read yields undefined value BF88_6134 BF88_6138 BF88_613C Note 1: ODCECLR ODCESET ODCEINV 31:0 31:0 31:0 TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as `0'. (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 249 PIC32MX FAMILY TABLE 12-6: Virtual Address BF88_6140 PORTF SFR SUMMARY Name TRISF 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- -- TRISF7(1) -- -- -- TRISF6 -- -- TRISF5 -- -- TRISF4 -- -- -- TRISF3 -- -- -- TRISF2 -- -- -- TRISF1 -- -- TRISF8(1) TRISF0 TRISF13(1) TRISF12(1) BF88_6144 BF88_6148 BF88_614C BF88_6150 TRISFCLR TRISFSET TRISFINV PORTF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- RF7(1) Write clears selected bits in TRISF, read yields undefined value Write sets selected bits in TRISF, read yields undefined value Write inverts selected bits in TRISF, read yields undefined value -- -- -- RF6 -- -- RF13 (1) -- -- RF12 (1) -- -- -- RF3 -- -- -- RF2 -- -- -- RF1 -- -- RF8(1) RF0 RF5 RF4 BF88_6154 PORTFCLR 31:0 BF88_6158 PORTFSET 31:0 BF88_615C PORTFINV BF88_6160 LATF 31:0 31:24 23:16 15:8 7:0 BF88_6164 BF88_6168 BF88_616C BF88_6170 LATFCLR LATFSET LATFINV ODCF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_6174 BF88_6178 BF88_617C Note 1: ODCFCLR ODCFSET ODCFINV 31:0 31:0 31:0 -- -- -- ODCF7(1) -- -- -- LATF7(1) Write clears selected bits in PORTF, read yields undefined value Write sets selected bits in PORTF, read yields undefined value Write inverts selected bits in PORTF, read yields undefined value -- -- -- LATF6 -- -- LATF13(1) LATF5 -- -- LATF12(1) LATF4 -- -- -- LATF3 -- -- -- LATF2 -- -- -- LATF1 -- -- LATF8(1) LATF0 Write clears selected bits in LATF, read yields undefined value Write sets selected bits in LATF, read yields undefined value Write inverts selected bits in LATF, read yields undefined value -- -- -- ODCF6 -- -- ODCF5 -- -- ODCF4 -- -- -- ODCF3 -- -- -- ODCF2 -- -- -- ODCF1 -- -- ODCF8(1) ODCF0 ODCF13(1) ODCF12(1) Write clears selected bits in ODCF, read yields undefined value Write sets selected bits in ODCF, read yields undefined value Write inverts selected bits in ODCF, read yields undefined value TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as `0'. DS61143A - page 250 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 12-7: Virtual Address BF88_6180 PORTG SFR SUMMARY Name TRISG 31:24 23:16 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 -- -- TRISG7 -- -- TRISG6 -- -- -- -- -- -- -- -- -- TRISG3 -- -- -- TRISG2 -- -- TRISG9 -- -- TRISG8 15:8 TRISG15(1) TRISG14(1) TRISG13(1) TRISG12(1) BF88_6184 TRISGCLR BF88_6188 BF88_618C BF88_6190 TRISGSET TRISGINV PORTG 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF88_6194 PORTGCLR 31:0 BF88_6198 PORTGSET 31:0 BF88_619C PORTGINV BF88_61A0 LATG 31:0 31:24 23:16 15:8 7:0 BF88_61A4 BF88_61A8 BF88_61AC BF88_61B0 LATGCLR LATGSET LATGINV ODCG 31:0 31:0 31:0 31:24 23:16 7:0 BF88_61B4 ODCGCLR BF88_61B8 ODCGSET BF88_61BC Note 1: ODCGINV 31:0 31:0 31:0 -- -- ODCG7 -- -- LATG15(1) LATG7 -- -- RG15 (1) TRISG1(1) TRISG0(1) Write clears selected bits in TRISG, read yields undefined value Write sets selected bits in TRISG, read yields undefined value Write inverts selected bits in TRISG, read yields undefined value -- -- RG14 (1) -- -- RG13 -- (1) -- -- RG12 -- (1) -- -- -- RG3 -- -- -- RG2 -- -- RG9 RG1(1) -- -- RG8 RG0(1) RG7 RG6 Write clears selected bits in PORTG, read yields undefined value Write sets selected bits in PORTG, read yields undefined value Write inverts selected bits in PORTG, read yields undefined value -- -- LATG14(1) LATG6 -- -- LATG13(1) -- -- -- LATG12(1) -- -- -- -- LATG3 -- -- -- LATG2 -- -- LATG9 LATG1(1) -- -- LATG8 LATG0(1) Write clears selected bits in LATG, read yields undefined value Write sets selected bits in LATG, read yields undefined value Write inverts selected bits in LATG, read yields undefined value -- -- ODCG6 -- -- -- -- -- -- -- -- -- ODCG3 -- -- -- ODCG2 -- -- ODCG9 -- -- ODCG8 15:8 ODCG15(1) ODCG14(1) ODCG13(1) ODCG12(1) ODCG1(1) ODCG0(1) Write clears selected bits in ODCG, read yields undefined value Write sets selected bits in ODCG, read yields undefined value Write inverts selected bits in ODCG, read yields undefined value TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as `0'. (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 251 PIC32MX FAMILY TABLE 12-8: Virtual Address BF88_61C0 CHANGE NOTICE AND PULL UP SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- ON -- Bit 30/22/14/6 -- -- FRZ -- Bit 29/21/13/5 -- -- SIDL -- Bit 28/20/12/4 -- -- -- -- Bit 27/19/11/3 -- -- -- -- Bit 26/18/10/2 -- -- -- -- Bit 25/17/9/1 -- -- -- -- Bit 24/16/8/0 -- -- -- -- CNCON BF88_61C4 BF88_61C8 BF88_61CC BF88_61D0 CNCONCLR CNCONSET CNCONINV CNEN 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears selected bits in CNCON, read yields undefined value Write sets selected bits in CNCON, read yields undefined value Write inverts selected bits in CNCON, read yields undefined value -- CNEN21(1) -- CNEN20(1) -- CNEN19(1) -- CNEN18 -- CNEN17 -- CNEN16 CNEN<15:8> CNEN<7:0> Write clears selected bits in CNEN, read yields undefined value Write sets selected bits in CNEN, read yields undefined value Write inverts selected bits in CNEN, read yields undefined value -- -- -- -- -- CNPUE21 (1) BF88_61D4 BF88_61D8 BF88_61DC BF88_61E0 CNENCLR CNENSET CNENINV CNPUE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- CNPUE20 (1) -- CNPUE9 (1) -- CNPUE18 -- CNPUE17 -- CNPUE16 CNPUE<15:8> CNPUE<7:0> Write clears selected bits in CNPUE, read yields undefined value Write sets selected bits in CNPUE, read yields undefined value Write inverts selected bits in CNPUE, read yields undefined value BF88_61E4 BF88_61E8 BF88_61EC CNPUECLR CNPUESET CNPUEINV 31:0 31:0 31:0 Note 1: CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as `0'. TABLE 12-9: Virtual Address CHANGE NOTICE INTERRUPT REGISTER SUMMARY Name Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 BF88_1050 BF88_1020 BF88_10D0 IEC1 IFS1 IPC6 7:0 7:0 23:16 SPI2RXIE SPI2TXIE SPI2RXIF SPI2TXIF -- -- SPI2EIE SPI2EIF -- CMP2IE CMP2IF CMP1IE CMP1IF CNIP<2:0> PMPIE PMPIF AD1IE AD1IF CNIE CNIF CNIS<1:0> Note: This summary table contains partial register definitions that only pertain to the GPIO peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A - page 252 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 12-1: U-0 -- bit 31 U-0 -- bit 23 R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- TRISx: TRIS REGISTERS(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-1 bit 8 R/W-1 bit 0 TRISx<15:8> TRISx<7:0> Unimplemented: Read as `0' TRISx<15:0>: TRISx Register bits 1 = Corresponding port pin `Input' 0 = Corresponding port pin `Output' Depending on the device, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 253 PIC32MX FAMILY REGISTER 12-2: U-0 -- bit 31 U-0 -- bit 23 R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 R/W-1 R/W-1 Rx<7:0> bit 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Rx<15:8> bit 8 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PORTx: PORT REGISTERS(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-1 Unimplemented: Read as `0' PORTx<15:0>: PORTx Register bits Read = Value on port pins Write = Value written to the LATx register, port latch and I/O pins Depending on the device family variant, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. Note 1: DS61143A - page 254 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 12-3: U-0 -- bit 31 U-0 -- bit 23 R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- LATx: LAT REGISTERS(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-1 bit 8 R/W-1 bit 0 LATx<15:8> LATx<7:0> Unimplemented: Read as `0' LATx<15:0>: LATx Register bits Read = Value on port latch, not I/O pins Write = Value written to port latch and I/O pins Depending on the device, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 255 PIC32MX FAMILY REGISTER 12-4: U-0 -- bit 31 U-0 -- bit 23 R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit W = Writable bit P = Programmable r = Reserved bit U = Unimplemented bit, read as `0' bit 31-16 bit 15-0 Unimplemented: Read as `0' ODCx<15:0>: ODCx Register bits If a port pin is configured as an output (corresponding TRISx bit = 0). 1 = Port pin open-drain output enabled 0 = Port pin open-drain output disabled If a port pin is configured as an input, ODCx bits have no effect. Depending on the device, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. -n = Bit value at POR: (`0', `1', x = unknown) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- ODCx: OPEN DRAIN CONFIGURATION REGISTERS(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-1 bit 8 R/W-1 bit 0 ODCx<15:8> ODCx<7:0> Note 1: DS61143A - page 256 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 12-5: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CNCON: CHANGE NOTICE CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' ON: Change Notice Module On bit 1 = CN module is enabled 0 = CN module is disabled FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode Unimplemented: Read as `0' bit 14 bit 13 bit 12-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 257 PIC32MX FAMILY REGISTER 12-6: U-0 -- bit 31 U-0 -- bit 23 R/W-0 CNEN15 bit 15 R/W-0 CNEN7 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-22 bit 21-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CNEN6 R/W-0 CNEN5 R/W-0 CNEN4 R/W-0 CNEN3 R/W-0 CNEN2 R/W-0 CNEN1 R/W-0 CNEN14 R/W-0 CNEN13 R/W-0 CNEN12 R/W-0 CNEN11 R/W-0 CNEN10 R/W-0 CNEN9 U-0 -- R/W-0 CNEN21 R/W-0 CNEN20 R/W-0 CNEN19 R/W-0 CNEN18 R/W-0 CNEN17 CNEN: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-0 CNEN16 bit 16 R/W-0 CNEN8 bit 8 R/W-0 CNEN0 bit 0 Unimplemented: Read as `0' CNEN<21:0>: CNEN Register If a port pin is configured as an input (corresponding TRISx bit = 1) 1 = Port pin input change notice enabled 0 = Port pin input change notice disabled If a port pin is configured as an output, CNENx bits have no effect Depending on the device, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. Note 1: DS61143A - page 258 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 12-7: U-0 -- bit 31 U-0 -- bit 23 R/W-0 CNPUE15 bit 15 R/W-0 CNPUE7 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-22 bit 21-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CNPUE6 R/W-0 CNPUE5 R/W-0 CNPUE4 R/W-0 CNPUE3 R/W-0 CNPUE2 R/W-0 CNPUE1 R/W-0 CNPUE14 R/W-0 CNPUE13 R/W-0 CNPUE12 R/W-0 CNPUE11 R/W-0 CNPUE10 R/W-0 CNPUE9 U-0 -- R/W-0 CNPUE21 R/W-0 CNPUE20 R/W-0 CNPUE19 R/W-0 CNPUE18 R/W-0 CNPUE17 CNPUE: INPUT CHANGE NOTIFICATION PULL-UP ENABLE(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-0 CNPUE16 bit 16 R/W-0 CNPUE8 bit 8 R/W-0 CNPUE0 bit 0 Unimplemented: Read as `0' CNPUE<21:0>: CNPUE Register bits If a port pin is configured as an input (corresponding TRISx bit = 1). 1 = Port pin pull-up enabled 0 = Port pin pull-up disabled If a port pin is configured as an output, it is recommended to disable the corresponding CNPUEx bit. Depending on the device, certain register bits or the entire register may not be implemented. Refer to Table 12.1 for specific register and bit assignments. Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 259 PIC32MX FAMILY 12.2 Parallel I/O (PIO) Ports 12.2.2 DIGITAL INPUTS All port pins have three registers (TRIS, LAT, and PORT) that are directly associated with their operation. TRIS is a data direction or tri-state control register that determines whether a pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a Power-On Reset (POR). PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx latch register holds the data written to either the LATx or PORTx registers. Reading the LATx latch register reads the last value written to the corresponding port or latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. See Section 12.1 "Port Registers". Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the ADP1CFG register = 1 enables the pin as a digital pin. Digital only pins are capable of input voltages up to 5.5v. Any pin that shares digital and analog functionality is limited to voltages up to VDD + 0.3V. . TABLE 12-10: MAXIMUM INPUT PIN VOLTAGES Input Pin Mode(s) Digital Only Digital + Analog Analog VIH (max) VIH = 5.5v VIH = VDD + 0.03v VIH = VDD + 0.03v Note: Refer to Section 29.0 "Electrical Characteristics" regarding the VIH specification. Note: Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 12.2.1 CLR, SET AND INV REGISTERS Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read instead. To set PORTC bit 0, use the LATSET register as follows: LATCSET = 0x0001; To clear PORTC bit 0, use the LATCLR register as follows: LATCCLR = 0x0001; To toggle PORTC bit 0, use the LATINV register as follows: LATCINV = 0x0001; Note: Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001; 12.2.3 ANALOG INPUTS Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the corresponding bits in the ADP1CFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. 12.2.4 DIGITAL OUTPUTS Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register. Digital output pin voltage is limited to VDD. 12.2.5 ANALOG OUTPUTS Certain pins can be configured as analog outputs, such as the CVREF output voltage used in the comparator module. Configuring the Comparator module to provide this output will present the analog output voltage on the pin independent of the TRIS register setting for the corresponding pin. DS61143A - page 260 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 12.2.6 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin configured as a digital output can also select between an active drive output and open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. From POR, when an IO pin is configured as a digital output, its output is active drive by default. Setting a bit in the ODCx register = 1 configures the corresponding pin as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD, e.g., 5V, on any desired digital-only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification, typically 5.5v. Most serial communication peripherals, when enabled, take full control of the I/O pin so that the input pins associated with the peripheral cannot be affected through the corresponding PORT registers. These peripherals include the following modules: * * * SPI I2CTM UART 12.2.9 INPUT CHANGE NOTIFICATION 12.2.7 PERIPHERAL MULTIPLEXING A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 12-2 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. Certain PIC32MX I/O port pins provide Input Change notification that can generate interrupt requests to the processor in response to a Change-Of-State (COS) on those selected input pins. The initial state of any enabled Change Notice (CN) pin must be established by reading the corresponding PORT register. This feature is capable of detecting input COS even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 22 external signals (CN0 through CN21) that may be selected (enabled) for generating an interrupt request on a COS. The following control registers are associated with the change notice module: * CNCON * CNEN * CNPUE The CNCON control register ON bit enables or disables the CN module and its ability to generate interrupts or respond to mismatch conditions. The CNEN (change notice enable) register control bits enable each CN input. Setting any of these bits enables a CN for the corresponding pins. The CNPUE (change notice pull-up enable) register control bits enable a weak pull-up to a corresponding CN input pin. The pull-ups act as a current source that is connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. Note: Pull-up resistors on change notification pins should always be disabled whenever the port pin is configured as a digital output. 12.2.8 SOFTWARE INPUT PIN CONTROL Some peripheral inputs assigned to an I/O pin may not take control of the I/O pin output driver. If the I/O pin associated with the peripheral is configured as an output, using the appropriate TRIS control bit, the user can manually affect the state of the peripheral's input pin through its corresponding LAT register. This behavior can be useful in some situations, especially for testing purposes, when no external signal is connected to the input pin. In general, the following peripherals allow their input pins to be controlled manually through the LAT registers: * * * * External Interrupt pins Timer Clock Input pins Input Capture pins PWM Fault pins (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 261 PIC32MX FAMILY TABLE 12-11: CHANGE NOTICE PIN AND PULL-UP TABLE Change Notice CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 Weak Pull-Up CNPUE0 CNPUE1 CNPUE2 CNPUE3 CNPUE4 CNPUE5 CNPUE6 CNPUE7 CNPUE8 CNPUE9 CNPUE10 CNPUE11 CNPUE12 CNPUE13 CNPUE14 CNPUE15 CNPUE16 CNPUE17 CNPUE18 CNPUE19 CNPUE20 CNPUE21 Port Pin RC14 RC13 RB0 RB1 RB2 RB3 RB4 RB5 RG6 RG7 RG8 RG9 RB15 RD4 RD5 RD6 RD7 RF4 RF5 RD13 RD14 RD15 64-Pin Device 100-Pin Device To prevent possible spurious interrupts when configuring change notice interrupts, the following steps are recommended: 1. 2. Disable CPU interrupts. Set desired CN I/O pin as input by setting corresponding TRISx register bits = 1. Note: If the I/O pin is shared with an analog peripheral, it may be necessary to set the corresponding AD1PCFG bit = 1 to ensure that the I/O pin is a digital input. Enable change notice module ON (CNCON<15>) = 1. Enable individual CN input pin(s); enable optional pull-up(s). Read corresponding PORT registers to clear mismatch condition on CN input pins. Configure the CN interrupt priority, CNIP<2:0>, and subpriority CNIS<1:0>. Clear CN interrupt flag, CNIF = 0. Enable CN interrupt enable, CNIE = 1. Enable CPU interrupts. Pin# 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 7. 8. 9. 4. 5. 6. 3. The port must be read to clear the mismatch condition and, then CN interrupt flag, CNIF (IFS1<0>), can be cleared in software. Failing to read the port before attempting to clear the CNIF bit may not allow the CNIF bit to be cleared. In addition to enabling the CN interrupt, an Interrupt Service Routine (ISR), is required. Example 12-1 and Example 12-2 show a partial code example of an ISR. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. 12.2.10 CHANGE NOTICE INTERRUPTS The Change Notice module is enabled as a source of interrupts via the respective CN interrupt enable bits: * CNIE (IEC1<0>) * CNIF (IFS1<0>) The interrupt priority level bits and interrupt subpriority level bits must also be configured: * CNIP<2:0> (IPC6<20:18>) * CNIS<1:0> (IPC6<17:16>) To enable CN interrupts, the ON bit (CNCON<15>) must = 1, one or more CN input pins must be enabled and the Change Notice Interrupt Enable bit, CNIE, must = 1. DS61143A - page 262 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 12-1: /* The following code example illustrates a Change Notice interrupt configuration for pins CN1(PORTC), CN4(PORTB) and CN18(PORTF). */ unsigned int value; /* NOTE: disable vector interrupts prior to configuration */ CNCON = 0x8000; CNEN= 0x00040012; CNPUE= 0x00040012; /* read value = value = value = // Enable Change Notice module // Enable CN1, CN4 and CN18 pins // Enable weak pull ups for CN1, CN4 and CN18 pins CN CONFIGURATION AND INTERRUPT INITIALIZATION EXAMPLE CODE port(s) to clear mismatch on change notice pins */ PORTB; PORTC; PORTF; IPS6SET = 0x00140000; // Set priority level=5 IPS6SET = 0x00030000; // Set subpriority level=3 // Could have also done this in single // operation by assigning IPS6SET = 0x00170000 IFS1CLR IEC1SET = 0x0001; = 0x0001; // Clear the interrupt flag status bit // Enable Change Notice interrupts /* re-enable vector interrupts after configuration */ EXAMPLE 12-2: /* CN ISR EXAMPLE CODE The following code example demonstrates a simple interrupt service routine for CN interrupts. The user's code at this vector should perform any application specific operations and must read the CN corresponding PORT registers to clear the mismatch conditions. Finally, the CN interrupt status flag must be cleared before exiting. */ void __ISR(_CHANGE_NOTICE_VECTOR, ipl3) CN_Interrupt_ISR(void) { unsigned int value; value = PORTB value = PORTC // Read PORTB to clear CN4 mismatch condition // Read PORTC to clear CN1,CN0 mismatch condition ... perform application specific operations in response to the interrupt IFS1CLR } = 0x0001; // Be sure to clear the CN interrupt status // flag before exiting the service routine. Note: The CN ISR code example shows MPLAB(R) C32 C compiler-specific syntax. Refer to your compiler manual regarding support for ISRs. (c) 2007 Microchip Technology Inc. Advance Information DS61143A - page 263 PIC32MX FAMILY NOTES: DS61143A - page 264 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 13.0 Note: TIMER1 This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 13.1 Additional Supported Features This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator, SOSC, for real-time clock applications. The following modes are supported: * * * * Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer * Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the Low-Power Secondary Oscillator to function as a Real-Time Clock (RTC). TABLE 13-1: Timer Timer 1 TIMER1 FEATURES Low-Power Oscillator Yes Asynchronous External Clock Yes 16-Bit Synchronous Timer/Counter Yes 32-Bit Synchronous Timer/Counter No Gated Timer Yes Special Event Trigger No (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 265 PIC32MX FAMILY FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-Bit Comparator TSYNC (T1CON<2>) 1 Sync TMR1 Reset T1IF Event Flag 0 1 TGATE (T1CON<7>) Q Q D TGATE (T1CON<7>) TCS (T1CON<1>) ON (T1CON<15>) 0 SOSCO/T1CK SOSCEN SOSCI Gate Sync PBCLK x1 10 00 Prescaler 1, 8, 64, 256 2 TCKPS<1:0> (T1CON<5:4>) Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. DS61143A-page 266 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 13.2 Timer Registers TIMER1 SFR SUMMARY Name Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 TABLE 13-2: Virtual Address BF80_0600 T1CON 31:24 23:16 15:8 7:0 -- -- ON TGATE -- -- FRZ -- -- -- SIDL -- -- TMWDIS -- -- TMWIP -- -- -- -- TSYNC -- -- -- TCS -- -- -- -- TCKPS<1:0> BF80_0604 BF80_0608 BF80_060C BF80_0610 T1CONCLR T1CONSET T1CONINV TMR1 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in T1CON, read yields undefined value Write sets selected bits in T1CON, read yields undefined value Write inverts selected bits in T1CON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMR1<15:8> TMR1<7:0> Write clears selected bits in TMR1, read yields undefined value Write sets selected bits in TMR1, read yields undefined value Write inverts selected bits in TMR1, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF80_0614 BF80_0618 BF80_061C BF80_0620 TMR1CLR TMR1SET TMR1INV PR1 31:0 31:0 31:0 31:24 23:16 15:8 7:0 PR1<15:8> PR1<7:0> Write clears selected bits in PR1, read yields undefined value Write sets selected bits in PR1, read yields undefined value Write inverts selected bits in PR1, read yields undefined value BF80_0624 BF80_0628 BF80_062C PR1CLR PR1SET PR1INV 31:0 31:0 31:0 TABLE 13-3: Virtual Address TIMER1 INTERRUPT REGISTER SUMMARY(1) Name Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 BF88_1000 BF88_1010 BF88_1080 IEC0 IFS0 IPC1 7:0 7:0 7:0 INT1IE INT1IF -- OC1IE OC1IF -- IC2IE IC2IF -- T1IE T1IF INT0IE INT0IF T1IP<2:0> CS1IE CS1IF CS0IE CS0IF CTIE CTIF T1IS<1:0> Note 1: This summary table contains partial register definitions that only pertain to the Timer1 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 267 PIC32MX FAMILY REGISTER 13-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 TGATE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- R/W-0 R/W-0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0 R/W-0 FRZ R/W-0 SIDL R/W-0 TMWDIS R-0 TMWIP U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- T1CON: TIMER1 CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 TCKPS<1:0> Unimplemented: Read as `0' ON: Timer On bit 1 = Timer is enabled 0 = Timer is disabled FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode TMWDIS: Asynchronous Timer Write Disable bit In Asynchronous Timer mode: 1 = Writes to asynchronous TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (legacy asynchronous timer functionality) In Synchronous Timer mode: This bit has no effect. TMWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as `0'. Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10-8 DS61143A-page 268 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 13-1: bit 7 T1CON: TIMER1 CONTROL REGISTER (CONTINUED) TGATE: Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and read `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled Unimplemented: Read as `0' TCKPS<1:0>: Timer Input Clock prescaler Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Unimplemented: Read as `0' TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored and read `0'. TCS: Timer Clock Source Select bit 1 = External clock from T1CKI pin 0 = Internal peripheral clock Unimplemented: Read as `0' bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 269 PIC32MX FAMILY 13.3 Modes of Operation 13.3.2 SYNCHRONOUS INTERNAL TIMER In this mode, the timer clock source is the internal PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0. Clock synchronization is not required, therefore the Timer1 Synchronization bit, TSYNC (T1CON<2>), is ignored. The TMR1 Count register increments on every PBCLK clock cycle when the timer clock prescale 13.3.1 CONSIDERATIONS FOR ALL TIMER 1 MODES * Timer1 module is disabled and powered off when the ON bit (T1CON<15>) = 0, thus providing maximum power savings. All other TxCON bits remain unchanged. * Updates to the T1CON register should only be performed when the timer module is disabled, ON bit (T1CON<15>) = 0. * Timer1 continues operating when the CPU goes into Idle mode if the "Stop In Idle mode" control bit is disabled, SIDL (TxCON<13>) bit = 0. If enabled, SIDL = 1, the timer module stops operation while the CPU is in Idle mode. * Setting or clearing the ON bit (T1CON<15>) and any other bits in T1CON in the same instruction may cause undefined behavior. The user is advised to program the T1CON register with the desired settings with one instruction, and then set the ON bit in a subsequent instruction. 7. EXAMPLE 13-1: SYNCHRONOUS INTERNAL TIMER INITIALIZATION // Stop and Init Timer // Clear timer register // Load period register T1CON = 0x0 TMR1 = 0x0; PR1 = 0xFFFF; T1CONSET = 0x8000;// Start Timer DS61143A-page 270 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 13.3.3 SYNCHRONOUS EXTERNAL TIMER EXAMPLE 13-2: In this mode, the timer clock source is an external clock source or pulse applied to the T1CK pin, TCS (T1CON<1>) = 1. To provide synchronization, Timer1 synchronization bit TSYNC (T1CON<2>) must be set (= 1). The 16-bit TMR1 Count register increments on every synchronized rising edge of an external clock when the timer clock prescale SYNCHRONOUS EXTERNAL TIMER INITIALIZATION // // // // Stop Timer and reset Set prescaler=1:256, external clock, synchronous mode T1CON = 0x0; T1CON = 0x0036 TMR1 = 0x0; PR1 = 0x3FFF; // Clear timer register // Load period register T1CONSET = 0x8000; // Start Timer 13.3.4 ASYNCHRONOUS EXTERNAL TIMER In this mode, the timer clock source is an external clock source or pulse applied to the T1CK pin, TCS (T1CON<1>) = 1. Clock synchronization is not required, therefore, the Timer1 clock synchronization bit should be cleared, TSYNC (T1CON<2>) = 0. The 16-bit TMR1 Count register increments on every rising edge of an external clock when the timer clock prescale 13.3.3.1 Considerations * When using an external clock source, regardless of the Timer1 prescale value, 2-3 external clock cycles are required, after the ON bit = 1, before the TMR1 register begins incrementing. * Timer1 will not operate from a synchronized external clock source while the CPU is in SLEEP mode, since the synchronizing PB clock is disabled during Sleep mode. The following steps should be performed to properly configure the Timer1 peripheral for Synchronous Counter mode operation. 1. 2. 3. 4. 5. 6. 7. Clear control bit, ON (T1CON<15>) = 0, to disable Timer1. Select the desired timer prescaler using bits, TCKPS<1:0> (T1CON<5:4). Set control bit, TCS (T1CON<1>) = 1, to select an external clock source. Set control bit, TSYNC (T1CON<2>) = 1, to enable synchronization. Clear Timer register TMR1. Load Period register PR1 with desired 16-bit match value. If timer interrupts are used, refer to Section 13.5 "Timer Interrupts" for interrupt configuration steps. Set control bit, ON (T1CON<15>) = 1, to enable Timer1. 13.3.4.1 Considerations * Regardless of the Timer1 prescale setting, 2-3 external clocks are required after the ON bit = 1, before the TMR1 register begins incrementing. * Timer1 can operate while the CPU is in Sleep mode. * The Timer1 interrupt can be used to wake the CPU from Sleep mode. * Typical use is with the Secondary Low-Power Oscillator, SOSC and RTCC Real-Time Clock Calendar peripheral. Note: The SOSC oscillator may be used by the CPU as a low-power clock source. Timer 1 does not have exclusive usage to this oscillator. Refer to the "PIC32MX Family Reference Manual" (DS61132) regarding the operation of the Secondary Low-Power Oscillator. 8. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 271 PIC32MX FAMILY 13.4 Reading and Writing TMR1 Register EXAMPLE 13-3: ASYNCHRONOUS EXTERNAL TIMER INITIALIZATION // // // // // // Stop Time and reset Set prescaler at 1:8, external clock source, asynchronous mode Clear timer register Load period register Due to the asynchronous nature of Timer1 operating in Asynchronous Clock mode, reading and writing to the TMR1 Count register requires synchronization between the asynchronous clock source and the internal PBCLK (Peripheral Bus Clock). Timer1 features a Timer Write Disable (TMWDIS) control bit (T1CON<12>) and a TMWIP (TImer Write in Progress) Status bit (T1CON<11>). These bits provide the user with 2 options for safely writing to the TMR1 Count register while Timer1 is enabled. These bits have no affect in Synchronous Clock modes. * Option 1 - Legacy Timer1 Write mode, TMWDIS bit = 0. To determine when it is safe to write to the TMR1 Count register, it is recommended to poll the TMWIP bit. When TMWIP = 0, it is safe to perform the next write operation to the TMR1 Count register. When TMWIP = 1, the previous write operation to the TMR1 Count register is still being synchronized and any additional write operations should wait until TMWIP = 0. * Option 2 - New synchronized Timer1 Write mode, TMWDIS bit = 1. A write to the TMR1 Count register can be performed at any time. However, if the previous write operation to the TMR1 Count register is still being synchronized, any additional write operations are ignored. Writing to the TMR1 Count register requires 2 to 3 asynchronous external clock cycles for the value to be synchronized into the TMR1 Count register. Reading from the TMR1 Count register requires 2 PBCLK cycle delays between the current unsynchronized value in the TMR1 Count register and the synchronized value returned by the read operation. In other words, the value read is always 2 PBCLK cycles behind the actual value in the TMR1 Count register. The following steps should be performed to properly configure the Timer1 peripheral for Asynchronous Counter mode operation. 1. 2. 3. 4. 5. 6. 7. 8. Clear control bit, ON (T1CON<15>) = 0, to disable Timer1. Select the desired timer prescaler using bits, TCKPS<1:0> (T1CON<5:4). Set control bit, TCS (T1CON<1>) = 1, to select an external clock source. Set control bit, TSYNC (T1CON<2>) = 0, to disable synchronization. Clear Timer Register, TMR1. Load Period Register, PR1, with desired 16-bit match value. If timer interrupts are used, refer to 13.5 "Timer Interrupts" for interrupt configuration steps. Set control bit, ON (T1CON<15>) = 1, to enable Timer1. T1CON = 0x0; T1CON = 0x0012; TMR1 = 0x0; PR1 = 0x7FFF; T1CONSET = 0x8000; // Start Timer DS61143A-page 272 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 13.4.1 Synchronous Internal Gated Timer EXAMPLE 13-4: In this mode, the timer clock source can only be the internal PBCLK (Peripheral Bus Cock), TCS (T1CON<1>) = 0. The T1CK pin provides the gating mechanism to enable and disable the timer counting, TGATE (T1CON<7>) = 1. Clock synchronization is not required, therefore Timer1 synchronization bit, TSYNC (T1CON<2>), is ignored. The 16-bit TMR1 Count register is enabled on the rising edge of the T1CK pin and increments on every internal PBCLK cycle when the timer clock prescale SYNCHRONOUS INTERNAL GATED TIMER INITIALIZATION // // // // // // Stop Timer and reset Enable gated mode, prescaler at 1:64, internal clock source Clear timer register Load period register T1CON = 0x0; T1CON = 0x0060; TMR1 = 0x0; PR1 = 0xFFFF; T1CONSET = 0x8000;// Start Timer 13.4.2 TIMER CLOCK PRESCALER Timer clock prescale bits, TCKPS<1:0> (T1CON<5:4>), are used to divide the timer clock source, permitting the TMR register to increment on every 1, 8, 64, or 256 (PBCLK or external) clock cycles. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. Associated with the clock prescale selection bits is a prescale counter. This prescale counter is cleared when any of the following conditions occur: * Any device Reset, except a Power-on Reset * The timer is disabled * A write to the TMR register Note: When the timer clock source is external and the timer clock prescale = N (other than 1:1), 2 to 3 external clock cycles are required to reset and synchronize the prescaler. * When the timer clock source is external and the timer clock prescale = N (other than 1:1), 2 to 3 external clock cycles are required, after the timer ON bit is set = 1, before the TMR1 Count register increments. * After a timer match event (TMR1 = PR1) and depending on the timer clock prescale setting N (other than 1:1), the timer will require N/2 additional (PBCLK or external) clock cycles before the TMR1 Counter register reset to 0x0000. Reading the TMR1 Count register just after the timer match event, but before the TMR1 Count register is rest, will return the timer match value. 8. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 273 PIC32MX FAMILY 13.5 Timer Interrupts Timer1 can generate an interrupt on a period match event or a gate event, caused by the falling edge of the external gate signal. Timer1 sets the interrupt flag bit, T1IF (IFS0<4>), whenever a Timer1 event is generated. Refer to a specific Timer mode for details regarding event conditions. When a Timer1 event is generated, the interrupt flag bit is set within 1 PBCLK + 2 SYSCLK cycles. If Timer1 Interrupt Enable bit is set, T1IE (IEC0<4>) = 1, an interrupt is generated. The Timer1 module is enabled as a source of interrupts through its respective interrupt enable bit, T1IE (IEC0<4>). The Timer1 Interrupt Flag, T1IF (IFS0<4>), must be cleared in software. The interrupt priority level bits and interrupt subpriority level bits must be also be configured: * T1IP<2:0> (IPC1<4:2>) * T1IS<1:0> (IPC1<1:0) Setting Timer1 interrupt priority level = 0 effectively disables the timer's ability to generate an interrupt. In addition to enabling the Timer1 interrupt, an Interrupt Service Routine, ISR, is generally required. Below is a partial code example of an ISR. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. EXAMPLE 13-5: T1CON = 0x0 TIMER INTERRUPT AND PRIORITIES // Stop the Timer and Reset Control register // Set prescaler at 1:1, internal clock source // Clear timer register // Load period register // // // // Set priority level=3 Set subpriority level=1 Could have also done this in single operation by assigning IPC1SET = 0x000D TMR1 = 0x0; PR1 = 0xFFFF; IPC1SET = 0x000C; IPC1SET = 0x0001; IFS0CLR = 0x0010; IEC0SET = 0x0010; T1CONSET = 0x8000; // Clear Timer interrupt status flag // Enable Timer interrupts // Start Timer EXAMPLE 13-6: TIMER ISR void __ISR(TIMER_1_VECTOR, IPL3) T1_Interrupt_ISR(void) { ... perform application specific operations in response to the interrupt IFS0CLR } = 0x0010; // Be sure to clear the Timer 1 interrupt status Note: The timer ISR code example shows MPLAB(R) C32 C Compiler specific syntax. Refer to your compiler manual regarding support for ISRs. DS61143A-page 274 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 13.6 I/O Pin Configuration Table 13-4 provides a summary of I/O pin resources associated with Timer1. The table shows the settings required to make each I/O pin work with a specific timer module. TABLE 13-4: I/O PIN CONFIGURATION FOR USE WITH THE TIMER MODULE Required Settings for Module Pin Control I/O Pin Name T1CK Required Yes(1) Module Enable(2) ON Bit Field(2) TCS, TGATE TRIS Input Pin Type I Buffer Type ST Description Timer1 External Clock/Gate Input Legend: CMOS = CMOS compatible input or output I = Input O = Output ST = Schmitt Trigger input with CMOS levels Note 1: This pin is only required for Gated Timer or External Synchronous Clock modes. Otherwise, this pin can be used for general purpose I/O and requires the user to set the corresponding TRIS control register bits. 2: This bit is located in the T1CON register. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 275 PIC32MX FAMILY NOTES: DS61143A-page 276 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 14.0 Note: TIMERS 2,3,4,5 This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 14.1 Additional Supported Features This family of PIC32MX devices feature four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-Bit Timer * Synchronous Internal 16-Bit Gated Timer * Synchronous External 16-Bit Timer Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: * Synchronous Internal 16-Bit Timer * Synchronous Internal 16-Bit Gated Timer * Synchronous External 16-Bit Timer Note: Throughout this chapter, references to registers TxCON, TMRx, and PRx use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5. * Selectable clock prescaler * Timers operational during CPU IDLE * Time base for input capture and output compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 only) * Fast bit manipulation using CLR, SET and INV registers Table 14-1 highlights the available features of these timers. TABLE 14-1: Timers 2, 4 3, 5 TIMER FEATURES Low-Power Oscillator No No Asynchronous External Clock No No 16-Bit Synchronous Timer Yes Yes 32-Bit Synchronous Timer(1) Yes Yes Gated Timer Yes Yes Special Event Trigger No Yes(2) Note 1: 32-bit mode requires combining timers 2 and 3 or timers 4 and 5. 2: ADC event trigger supported by Timer3 only. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 277 PIC32MX FAMILY FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) TMRx (Note 1) ADC Event Trigger Comparator x 16 Sync Equal PRx Reset 0 1 TGATE (TxCON<7>) Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK Gate Sync PBCLK Note 1: ADC event trigger is available on Timer3 only. TxIF Event Flag x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MSHalfWord Equal TMRx LSHalfWord Sync (Note 2) ADC Event Trigger 32-Bit Comparator PRy TyIF Event Flag 0 1 TGATE (TxCON<7>) PRx Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK Gate Sync PBCLK x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of of "x' in registers TxCON, TMRx, PRx, TxCK refers to either Timer2 or Timer4; the use of `y' in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5. 2: ADC event trigger is available only on Timer2/3 pair. DS61143A-page 278 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 14-1: Virtual Address BF80_0800 TIMER2 SFR SUMMARY Name Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 23:16 15:8 7:0 -- -- ON TGATE -- -- FRZ -- -- SIDL TCKPS<2:0> -- -- -- -- -- -- T32 -- -- -- -- Bit 25/17/9/1 -- -- -- TCS Bit 24/16/8/0 -- -- -- -- T2CON BF80_0804 T2CONCLR BF80_0808 T2CONSET BF80_080C T2CONINV BF80_0810 TMR2 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in T2CON, read yields undefined value Write sets selected bits in T2CON, read yields undefined value Write inverts selected bits in T2CON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMR2<15:8> TMR2<7:0> Write clears selected bits in TMR2, read yields undefined value Write sets selected bits in TMR2, read yields undefined value Write inverts selected bits in TMR2, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF80_0814 TMR2CLR BF80_0818 TMR2SET BF80_081C TMR2INV BF80_0820 PR2 31:0 31:0 31:0 31:24 23:16 15:8 7:0 PR2<15:8> PR2<7:0> Write clears selected bits in PR2, read yields undefined value Write sets selected bits in PR2, read yields undefined value Write inverts selected bits in PR2, read yields undefined value BF80_0824 BF80_0828 BF80_082C PR2CLR PR2SET PR2INV 31:0 31:0 31:0 TABLE 14-2: Virtual Address BF88_1040 BF88_1010 BF88_1090 TIMER2 INTERRUPT REGISTER SUMMARY(1) Name IEC0 IFS0 IPC2 15:8 15:8 7:0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 INT3IE INT3IF -- OC3IE OC3IF -- IC3IE IC3IF -- T3IE T3IF INT2IE INT2IF T2IP<2:0> OC2IE OC2IF IC2IE IC2IF Bit 24/16/8/0 T2IE T2IF T2IS<1:0> Note 1: This summary table contains partial register definitions that only pertain to the Timer2 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. TABLE 14-3: Virtual Address BF80_0A00 TIMER3 SFR SUMMARY Name Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 23:16 15:8 7:0 -- -- ON TGATE -- -- FRZ -- -- SIDL TCKPS<2:0> -- -- -- -- -- -- -- -- -- -- -- Bit 25/17/9/1 -- -- -- TCS Bit 24/16/8/0 -- -- -- -- T3CON BF80_0A04 T3CONCLR BF80_0A08 T3CONSET BF80_0A0C T3CONINV BF80_0A10 TMR3 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in T3CON, read yields undefined value Write sets selected bits in T3CON, read yields undefined value Write inverts selected bits in T3CON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMR3<15:8> TMR3<7:0> Write clears selected bits in TMR3, read yields undefined value Write sets selected bits in TMR3, read yields undefined value Write inverts selected bits in TMR3, read yields undefined value BF80_0A14 TMR3CLR BF80_0A18 TMR3SET BF80_0A1C TMR3INV 31:0 31:0 31:0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 279 PIC32MX FAMILY TABLE 14-3: Virtual Address BF80_0A20 TIMER3 SFR SUMMARY (CONTINUED) Name PR3 31:24 23:16 15:8 7:0 Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 -- -- -- -- -- -- -- -- -- -- -- -- Bit 25/17/9/1 -- -- Bit 24/16/8/0 -- -- PR3<15:8> PR3<7:0> Write clears selected bits in PR3, read yields undefined value Write sets selected bits in PR3, read yields undefined value Write inverts selected bits in PR3, read yields undefined value BF80_0A24 BF80_0A28 BF80_0A2C PR3CLR PR3SET PR3INV 31:0 31:0 31:0 TABLE 14-4: Virtual Address BF88_1040 BF88_1010 BF88_10A0 TIMER3 INTERRUPT REGISTER SUMMARY(1) Name IEC0 IFS0 IPC3 15:8 15:8 7:0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 INT3IE INT3IF -- OC3IE OC3IF -- IC3IE IC3IF -- T3IE T3IF INT2IE INT2IF T3IP<2:0> OC2IE OC2IF IC2IE IC2IF Bit 24/16/8/0 T2IE T2IF T3IS<1:0> Note 1: This summary table contains partial register definitions that only pertain to the Timer 3 peripheral. Refer to the PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers. REGISTER 14-5: Virtual Address BF80_0C00 TIMER4 SFR SUMMARY Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 31:24 23:16 15:8 7:0 -- -- ON TGATE -- -- FRZ -- -- SIDL TCKPS<2:0> -- -- -- -- -- -- T32 -- -- -- -- -- -- -- TCS Bit 24/16/8/0 -- -- -- -- Name T4CON BF80_0C04 T4CONCLR BF80_0C08 T4CONSET BF80_0C0C T4CONINV BF80_0C10 TMR4 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in T4CON, read yields undefined value Write sets selected bits in T4CON, read yields undefined value Write inverts selected bits in T4CON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMR4<15:8> TMR4<7:0> Write clears selected bits in TMR4, read yields undefined value Write sets selected bits in TMR4, read yields undefined value Write inverts selected bits in TMR4, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF80_0C14 TMR4CLR BF80_0C18 TMR4SET BF80_0C1C BF80_0C20 TMR4INV PR4 31:0 31:0 31:0 31:24 23:16 15:8 7:0 PR4<15:8> PR4<7:0> Write clears selected bits in PR4, read yields undefined value Write sets selected bits in PR4, read yields undefined value Write inverts selected bits in PR4, read yields undefined value BF80_0C24 BF80_0C28 BF80_0C2C PR4CLR PR4SET PR4INV 31:0 31:0 31:0 REGISTER 14-6: Virtual Address BF88_1040 BF88_1010 BF88_10B0 TIMER 4 INTERRUPT REGISTER SUMMARY(1) Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 23:16 23:16 7:0 SPI1EIE SPI1EIF -- OC5IE OC5IF -- IC5IE IC5IF -- T5IE T5IF INT4IE INT4IF T4IP<2:0> OC4IE OC4IF IC4IE IC4IF Bit 24/16/8/0 T4IE T4IF Name IEC0 IFS0 IPC4 T4IS<1:0> Note 1: This summary table contains partial register definitions that only pertain to the Timer4 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A-page 280 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 14-7: Virtual Address BF80_0E00 TIMER5 SFR SUMMARY Name T5CON 31:24 23:16 15:8 7:0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- ON TGATE -- -- FRZ -- -- SIDL TCKPS<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCS Bit 24/16/8/0 -- -- -- -- BF80_0E04 T5CONCLR BF80_0E08 T5CONSET BF80_0E0C T5CONINV BF80_0E10 TMR5 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- Write clears selected bits in T5CON, read yields undefined value Write sets selected bits in T5CON, read yields undefined value Write inverts selected bits in T5CON, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMR5<15:8> TMR5<7:0> Write clears selected bits in TMR5, read yields undefined value Write sets selected bits in TMR5, read yields undefined value Write inverts selected bits in TMR5, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BF80_0E14 BF80_0E18 BF80_0E1C BF80_0E20 TMR5CLR TMR5SET TMR5INV PR5 31:0 31:0 31:0 31:24 23:16 15:8 7:0 PR5<15:8> PR5<7:0> Write clears selected bits in PR5, read yields undefined value Write sets selected bits in PR5, read yields undefined value Write inverts selected bits in PR5, read yields undefined value BF80_0E24 BF80_0E28 BF80_0E2C PR5CLR PR5SET PR5INV 31:0 31:0 31:0 TABLE 14-8: Virtual Address BF88_1040 BF88_1010 BF88_10C 0 TIMER5 INTERRUPT REGISTER SUMMARY(1) Name IEC0 IFS0 IPC5 23:16 23:16 7:0 Bit 31/23/15/ 7 SPI1EIE SPI1EIF -- Bit 30/22/14/ 6 OC5IE OC5IF -- Bit 29/21/13/ 5 IC5IE IC5IF -- Bit 28/20/12/ 4 T5IE T5IF Bit 27/19/11/ 3 INT4IE INT4IF T5IP<2:0> Bit 26/18/10/ 2 OC4IE OC4IF Bit 25/17/9/1 IC4IE IC4IF Bit 24/16/8/0 T4IE T4IF T5IS<1:0> Note 1: This summary table contains partial register definitions that only pertain to the Timer5 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 281 PIC32MX FAMILY 14.2 Control Registers T2CON, T4CON: TIMER2 AND TIMER4 CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 TCKPS<2:0> R/W-0 R/W-0 T32 U-0 -- R/W-0 TCS U-0 -- bit 0 REGISTER 14-9: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 TGATE bit 7 Legend: R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit bit 31-16 bit 15 -n = Bit Value at POR: (`0', `1', x = Unknown) Unimplemented: Read as `0' ON: Timer On bit 1 = Timer is enabled 0 = Timer is disabled FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode Unimplemented: Read as `0' TGATE: Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and read `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS<2:0>: Timer Input Clock prescaler Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 14 bit 13 bit 12-8 bit 7 bit 6-4 DS61143A-page 282 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY bit 3 T32: 32-Bit Timer Mode Select bits 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timers Unimplemented: Read as `0' TCS: Timer Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal peripheral clock Unimplemented: Read as `0' bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 283 PIC32MX FAMILY REGISTER 14-10: T3CON, T5CON: TIMER3 AND TIMER5 CONTROL REGISTER U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 TGATE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 TCKPS<2:0> R/W-0 U-0 -- U-0 -- R/W-0 TCS U-0 -- bit 0 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' ON: Timer On bit 1 = Module is enabled 0 = Module is disabled FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode Unimplemented: Read as `0' TGATE: Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and read `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS<1:0>: Timer Input Clock Prescaler Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Unimplemented: Read as `0' bit 14 bit 13 bit 12-8 bit 7 bit 6-4 bit 3-2 DS61143A-page 284 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal peripheral clock Unimplemented: Read as `0' bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 285 PIC32MX FAMILY 14.3 Modes of Operation The 16-bit (default) and 32-bit mode timer peripherals can operate as synchronous timer/counters using internal or external clock sources, or as synchronous gated timers using an internal clock source and external clock/gate pins. Each mode is easily configured and described in the following sections. The following steps should be performed to properly configure the 16-bit Timer peripherals for Timer mode operation: 1. 2. 3. 4. 5. 6. Clear ON control bit, (TxCON<15>) = 0, to disable timer. Configure TCKPS control bits, (TxCON<6:4), to select desired timer clock prescale. Set TCS control bit, (TxCON<1>) = 0, to select the internal PBCLK clock source. Clear TMRx register. Load PRx register with desired 16-bit match value. If timer interrupts are to be used, refer to Section 14.4 Timer Interrupts for interrupt configuration steps. Set ON control bit = 1 to enable Timer. 14.3.1 CONSIDERATIONS FOR ALL TIMER MODES * A timer module is disabled and powered off when the ON bit (TxCON<15>) = 0, thus providing maximum power savings. All other TxCON bits remain unchanged. * Updates to the TxCON register should only be performed when the timer module is disabled, ON bit (TxCON<15>) = 0. * A timer continues operating when the CPU goes into Idle mode if the "Stop In Idle mode" control bit is disabled, SIDL (TxCON<13>) bit = 0. If enabled, SIDL = 1, the timer module stops operation while the CPU is in Idle mode. * Setting or clearing the ON bit (TxCON<15>) and any other bits in the TxCON register during a single instruction may cause undefined behavior. The user is advised to program the TxCON register with the desired settings with one instruction, and then set the ON bit in a subsequent instruction. 7. EXAMPLE 14-1: SYNCHRONOUS INTERNAL 16-BIT TIMER INITIALIZATION //Stop and Init Timer //Clear timer register //Load period register T2CON = 0x0; TMR2 = 0x0; PR2 = 0xFFFF; T2CONSET = 0x8000; // Start Timer 14.3.3 14.3.2 SYNCHRONOUS INTERNAL 16-BIT TIMER SYNCHRONOUS EXTERNAL 16-BIT TIMER In this mode, the timer clock source is the internal PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0. The 16-bit TMRx Count register increments on every internal PBCLK cycle when the timer clock prescale In this mode, the timer clock source is an external clock source or pulse applied to the TxCK pin, TCS (TxCON<1>) = 1. The 16-bit TMRx Count register increments on every rising edge of an external clock when the timer clock prescale DS61143A-page 286 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY The following steps should be performed to properly configure the timer peripheral for Synchronous Counter mode operation: 1. 2. 3. 4. 5. 6. Clear control bit, ON (TxCON<15>) = 0, to disable timer. Select the desired timer prescaler using bits, TCKPS<2:0> (TxCON<6:4). Set control bit, TCS (TxCON<1>) = 1, to select an external clock source. Clear Timer register, TMRx. Load Period register, PRx, with desired 16-bit match value. If timer interrupts are used, refer to Section 14.4 Timer Interrupts for interrupt configuration steps. Set control bit, ON (TxCON<15>) = 1, to enable timer. For clock prescale = N (other than 1:1), the timer operates at a clock rate = (PBCLK/N); therefore, the TMRx Count register increments on every Nth PBCLK clock cycle. For further details regarding timer prescaler, refer to Section 14.3.9 Timer Clock Prescaler. The following steps should be performed to properly configure the timer peripheral for Gated Timer mode operation: 1. 2. 3. 4. 5. 6. 7. Clear control bit, ON (TxCON<15>) = 0, to disable Timer. Select the desired timer prescaler using bits, TCKPS<2:0> (TxCON<6:4>). Set control bit, TCS (TxCON<1>) = 0, to select the internal clock source. Set control bit, TGATE (TxCON<7>) = 1. Clear Timer register, TMRx. Load Period register, PRx, with desired 16-bit match value. If timer interrupts are to be used, refer to Section 14.4 Timer Interrupts for interrupt configuration steps. Set control bit, ON (TxCON<15>) = 1, to enable timer. 7. EXAMPLE 14-2: SYNCHRONOUS EXTERNAL 16-BIT TIMER INITIALIZATION //Stop and Init Timer T3CON = 0x0; 8. T3CONSET = 0x0072; //Prescaler=1:256, //external clock TMR3 = 0x0; //Clear timer register PR3 = 0x3FFF; //Load period register EXAMPLE 14-3: SYNCHRONOUS INTERNAL 16-BIT GATED TIMER INITIALIZATION //Stop and Init Timer //Enable gated mode, //prescaler=1:64, //internal clock //Clear timer register //Load period register T3CONSET = 0x8000;//Start Timer T4CON = 0x0; T4CON = 0x00E0; 14.3.4 SYNCHRONOUS INTERNAL 16-BIT GATED TIMER TMR4 = 0; PR4 = 0xFFFF; In this mode, the timer clock source can only be the internal PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0. The TxCK pin provides the gating mechanism to enable and disable the timer counting, TGATE (TxCON<7>) = 1. The 16-bit TMRx Count register is enabled on the rising edge of the TxCK pin and increments on every internal PBCLK cycle when the timer clock prescale T4CONSET = 0x8000;//Start Timer 14.3.5 SYNCHRONOUS INTERNAL 32-BIT TIMER In this mode, T32 (TxCON<3>) = 1 and the timer clock source is the internal PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0. The 32-bit TMRxy Count register increments on every internal PBCLK cycle when the timer clock prescale (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 287 PIC32MX FAMILY For clock prescale = N (other than 1:1), the timer operates at a clock rate = (PBCLK/N); therefore, the TMRxy Count register increments on every Nth PBCLK clock cycle. For further details regarding the timer prescaler, refer to Section 14.3.9 Timer Clock Prescaler. EXAMPLE 14-4: SYNCHRONOUS INTERNAL 32-BIT TIMER INITIALIZATION 14.3.6 CONSIDERATIONS * 32-bit timer pairs can be created using Timer2 with Timer3, or Timer4 with Timer5. * With Timer2 or Timer4 enabled, setting the T32 bit (T2CON<3> or T4CON<3>) = 1 automatically enables the corresponding Timer3 or Timer5 module. For this reason, it is not necessary to manually enable Timer3 or Timer5. * T2CON and T4CON control registers are used for configuring the 32-bit timer operations; Writes to T3CON and T5CON are ignored. * T2CK and T4CK input pins are utilized for the 32bit gated timer or external synchronous counter operations; T3CK and T5CK are ignored. * 32-bit timer interrupts use Timer3 or Timer5 interrupt enable bits and interrupt flag bits; Timer2 and Timer4 interrupt enable and interrupt flag bits are ignored. * Load TMRxy pair by writing the 32-bit value to TMRx. * Load PRxy pair by writing the 32-bit value to PRx. The following steps should be performed to properly configure the 32-bit timer peripherals for Timer mode operation. 1. 2. 3. 4. 5. 6. 7. Clear control bit, ON (TxCON<15>) = 0, to disable timer. Set control bit, T32 (TxCON<3>). Select the desired timer prescaler using bits TCKPS<2:0> (TxCON<6:4>). Set control bit, TCS (TxCON<1>) = 0, to select the internal clock source. Clear Timer register, TMRxy. Load Period register, PRxy, with desired 32-bit match value. If timer interrupts are used, refer to Section 14.4 Timer Interrupts for interrupt configuration steps. Set control bit, ON (TxCON<15>) = 1, to enable timer. T4CON = 0x0; //Stop Timer4 and clear T5CON = 0x0; //Stop Timer5 and clear T4CONSET = 0x0038; // Enable 32-bit mode, // prescaler at 1:8, // internal clock TMR4 = 0x0; // Clear TMR4 and TMR5 // Same as TMR4 = 0x0 PR4 = 0xFFFFFFFF; // Load PR4 and PR5 // with 32-bit value // Same as PR4=0xFFFFFFFF T4CONSET = 0x8000; // Start Timer 14.3.7 SYNCHRONOUS EXTERNAL 32-BIT TIMER In this mode, T32 (TxCON<3>) = 1 and the timer clock source is an external clock source or pulse applied to the TxCK pin, TCS (TxCON<1>) = 1. The 32-bit TMRxy Count register increments on every synchronized rising edge of an external clock when the timer clock prescale 8. 8. DS61143A-page 288 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 14-5: SYNCHRONOUS EXTERNAL 32-BIT TIMER INITIALIZATION EXAMPLE 14-6: SYNCHRONOUS INTERNAL 32-BIT GATED TIMER INITIALIZATION T2CON = 0x0; //Stop Timer2 and clear T3CON = 0x0; //Stop Timer3 and clear T2CONSET = 0x006A //32-bit mode, //external clock, //prescale=1:64 TMR2 = 0x0; // Clear TMR2 and TMR3 // Same as TMR2 = 0x0 PR2 = 0xFFFFFFFF; // Load PR2 and PR3 // Same as PR2=0xFFFFFFFF T2CONSET = 0x8000; // Start timer T4CON = 0x0; //Stop Timer4 and clear T5CON = 0x0; //Stop Timer5 and clear T4CONSET = 0x00C8; //32-bit mode, //gate enable, //internal clock, //1:16 prescale TMR4 = 0x0; //Clear TMR4 and TMR5 //Same as TMR4 = 0x0 PR4 = 0xFFFFFFFF; //Load PR4 and PR5 regs //Same as PR4 =0xFFFFFFFF T4CONSET = 0x8000; //Start 32-bit timer 14.3.8 SYNCHRONOUS INTERNAL 32-BIT GATED TIMER 14.3.9 TIMER CLOCK PRESCALER In this mode, the timer clock source is the internal PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0. The TxCK pin provides the gating mechanism to enable and disable the timer counting, TGATE (TxCON<7>) = 1. The 32-bit TMRxy Count register is enabled on the rising edge of the TxCK pin and increments on every internal PBCLK cycle when the timer clock prescale Timer clock prescale bits, TCKPS<1:0> (TxCON<6:4>), are used to divide the timer clock source permitting the TMR register to increment on every 1, 2, 4, 8, 16, 32, 64, or 256 (PBCLK or external) clock cycles. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. 14.3.10 CONSIDERATIONS Associated with the clock prescale selection bits is a prescale counter. The timer prescale counter is cleared when any of the following conditions occur: 1. 2. 3. Any device Reset, except a Power-on Reset. The timer is disabled. Any write to the TMR register. Note: When the timer clock source is external and the timer clock prescale = N (other than 1:1), 2 to 3 external clock cycles are required to reset and synchronize the prescaler. * When the timer clock source is external and the timer clock prescale = N (other than 1:1), 2 to 3 external clock cycles are required, after the timer ON bit is set = 1, before the TMRx Count register increments. * After a timer match event (TMRx = PRx) and depending on the timer clock prescale setting N (other than 1:1), the timer will require N additional (PBCLK or external) clock cycles before the TMRx Counter register resets to 0x0000. Reading the TMRx Count register just after the timer match event, but before the TMRx Count register is reset, will return the timer match value. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 289 PIC32MX FAMILY 14.4 Timer Interrupts A timer can generate an interrupt on a period match event or a gate event, caused by the falling edge of the external gate signal. A timer sets its corresponding interrupt flag bit, TxIF, whenever the timer event is generated. Refer to a specific timer mode for details regarding these event conditions. When a timer event is generated, the interrupt flag bit is set within 1 PBCLK + 2 SYSCLK cycles. If the timer interrupt enable bit is set, TxIE = 1, an interrupt is generated. The timer module is enabled as a source of interrupts via the respective Timer Interrupt Enable bit, TxIE (IECx EXAMPLE 14-7: T2CON = 0x0; 16-BIT TIMER INTERRUPT AND PRIORITIES // Stop Timer and clear control register, // prescaler at 1:1,internal clock source // Clear timer register // Load period register TMR2 = 0x0; PR2 = 0xFFFF; IPC2SET = 0x0000000C; // Set priority level=3 IPC2SET = 0x00000001; // Set subpriority level=1 // Could have also done this in single // operation by assigning IPC2SET = 0x0000000D IFS0CLR = 0x00000100; // Clear Timer interrupt status flag IEC0SET = 0x00000100; // Enable Timer interrupts T2CONSET = 0x8000; // Start Timer EXAMPLE 14-8: 32-BIT TIMER INTERRUPT AND PRIORITIES // // // // // // // // Stop 16-bit Timer4 and clear control register Stop 16-bit Timer5 and clear control register Enable 32-bit mode, prescaler at 1:8, internal clock source Clear contents of the TMR4 and TMR5 registers in one 32-bit load operation Load PR4 and PR5 registers with 32-bit value 0xFFFFFFFF in one 32-bit load operation T4CON = 0x0; T5CON = 0x0; T4CONSET = 0x0038; TMR4= 0x0; PR4 = 0xFFFFFFFF; IPC5SET = 0x00000004; // Set priority level=1 and IPC5SET = 0x00000001; // Set subpriority level=1 // Could have also done this in single // operation by assigning IPC5SET = 0x00000005 IFS0CLR = 0x10000000; // Clear the Timer5 interrupt status flag IEC0SET = 0x10000000; // Enable Timer5 interrupts T4CONSET = 0x8000; // Start Timer DS61143A-page 290 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 14-9: TIMER ISR void __ISR(TIMER_2_VECTOR, ipl3) T2_Interrupt_ISR(void) { ... perform application specific operations in response to the interrupt IFS0CLR } = 0x00000100; // Be sure to clear the Timer2 interrupt status Note: The timer ISR code example shows MPLAB(R) C32 Compiler specific syntax. Refer to your compiler manual regarding support for ISRs. 14.4.1 I/O Pin Configuration The table below provides a summary of I/O pin resources associated with the timer modules. The table shows the settings required to make an I/O pin available for a specific Timer module. TABLE 14-2: I/O PIN CONFIGURATION FOR USE WITH TIMER MODULES Required Settings for Module Pin Control I/O Pin Name T2CK T3CK T4CK T5CK Required Yes(1) Yes1) Yes(1) Yes(1) Module Enable(2) ON ON ON ON Bit Field(2) TCS, TGATE TCS, TGATE TCS, TGATE TCS, TGATE TRIS Input Input Input Input Pin Type I I I I Buffer Type ST ST ST ST Description Timer2 External Clock/Gate Input Timer3 External Clock/Gate Input Timer4 External Clock/Gate Input Timer5 External Clock/Gate Input Legend: CMOS = CMOS compatible input or output I = Input O = Output ST = Schmitt Trigger input with CMOS levels Note 1: These pins are only required for modes using gated timer or external clock inputs. Otherwise, these pins can be used for general purpose I/O and require the user to set the corresponding TRIS register bits. 2: These bits are located in the TxCON register. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 291 PIC32MX FAMILY NOTES: DS61143A-page 292 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 15.0 Note: INPUT CAPTURE This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 4. Prescaler Capture Event modes -Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin The input capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC32MX Family devices support up to five input capture channels. The input capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin Capture timer value on every edge (rising and falling) Capture timer value on every edge (rising and falling), specified edge first. Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts 2. 3. FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM IC x Input Timer3 T imer2 ICxTMR 0 ICxC32 FIF O Control ICxBUF <31:16> Prescaler 1, 4, 16 Edge Detect ICxBUF<15:0> 1 ICxM<2:0> ICxFEDGE ICxM<2:0> ICxCON ICxBNE ICxOV Interrupt Event Generation Data Space Interface ICxI< 1:0> Interrupt Peripheral Data Bus (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 293 PIC32MX FAMILY TABLE 15-1: Virtual Address BF80_2000 INPUT CAPTURE REGISTER SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- ON ICTMR Bit 30/22/14/6 -- -- FRZ ICI<1:0> Bit 29/21/13/5 -- -- SIDL Bit 28/20/12/4 -- -- -- ICOV Bit 27/19/11/3 -- -- -- ICBNE Bit 26/18/10/2 -- -- -- Bit 25/17/9/1 -- -- ICFEDGE ICM<2:0> Bit 24/16/8/0 -- -- ICC32 IC1CON BF80_2004 BF80_2008 BF80_200C BF80_2010 IC1CONCLR IC1CONSET IC1CONINV IC1BUF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in IC1CON, read yields an undefined value Write sets selected bits in IC1CON, read yields an undefined value Write inverts selected bits in IC1CON, read yields an undefined value IC1BUF<31:24> IC1BUF<23:16> IC1BUF<15:8> IC1BUF<7:0> -- -- ON ICTMR -- -- FRZ ICI<1:0> -- -- SIDL -- -- -- ICOV -- -- -- ICBNE -- -- -- -- -- ICFEDGE ICM<2:0> -- -- ICC32 BF80_2200 IC2CON 31:24 23:16 15:8 7:0 BF80_2204 BF80_2208 BF80_220C BF80_2210 IC2CONCLR IC2CONSET IC2CONINV IC2BUF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in IC2CON, read yields an undefined value Write sets selected bits in IC2CON, read yields an undefined value Write inverts selected bits in IC2CON, read yields an undefined value IC2BUF<31:24> IC2BUF<23:16> IC2BUF<15:8> IC2BUF<7:0> -- -- ON ICTMR -- -- FRZ ICI<1:0> -- -- SIDL -- -- -- ICOV -- -- -- ICBNE -- -- -- -- -- ICFEDGE ICM<2:0> -- -- ICC32 BF80_2400 IC3CON 31:24 23:16 15:8 7:0 BF80_2404 BF80_2408 BF80_240C BF80_2410 IC3CONCLR IC3CONSET IC3CONINV IC3BUF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in IC3CON, read yields an undefined value Write sets selected bits in IC3CON, read yields an undefined value Write inverts selected bits in IC3CON, read yields an undefined value IC3BUF<31:24> IC3BUF<23:16> IC3BUF<15:8> IC3BUF<7:0> -- -- ON ICTMR -- -- FRZ ICI<1:0> -- -- SIDL -- -- -- ICOV -- -- -- ICBNE -- -- -- -- -- ICFEDGE ICM<2:0> -- -- ICC32 BF80_2600 IC4CON 31:24 23:16 15:8 7:0 BF80_2604 BF80_2608 BF80_260C BF80_2610 IC4CONCLR IC4CONSET IC4CONINV IC4BUF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in IC4CON, read yields an undefined value Write sets selected bits in IC4CON, read yields an undefined value Write inverts selected bits in IC4CON, read yields an undefined value IC4BUF<31:24> IC4BUF<23:16> IC4BUF<15:8> IC4BUF<7:0> -- -- ON ICTMR -- -- FRZ ICI<1:0> -- -- SIDL -- -- -- ICOV -- -- -- ICBNE -- -- -- -- -- ICFEDGE ICM<2:0> -- -- ICC32 BF80_2800 IC5CON 31:24 23:16 15:8 7:0 BF80_2804 BF80_2808 BF80_280C BF80_2810 IC5CONCLR IC5CONSET IC5CONINV IC5BUF 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in IC5CON, read yields an undefined value Write sets selected bits in IC5CON, read yields an undefined value Write inverts selected bits in IC5CON, read yields an undefined value IC5BUF<31:24> IC5BUF<23:16> IC5BUF<15:8> IC5BUF<7:0> DS61143A-page 294 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 15-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 ICxTMR bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R-0 ICxOV R-0 ICxBNE R/W-0 R/W-0 ICxM<2:0> bit 0 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- R/W-0 ICxFEDGE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- ICXCON: INPUT CAPTURE X CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 ICxC32 bit 8 R/W-0 ICxI<1:0> Unimplemented: Read as `0' ON: ON bit 1 = Module enabled 0 = Disable and Reset module, disable clocks, disable interrupt generation, and allow SFR modifications FRZ: Freeze in Debug Mode Control bit (read/write only in Debug mode; otherwise read as `0') 1 = Freeze module operation when in Debug mode 0 = Do not freeze module operation when in Debug mode SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode Unimplemented: Read as `0' ICxFEDGE: First Capture Edge Select bit (only used in mode 6, ICxM = 110) 1 = Capture rising edge first 0 = Capture falling edge first ICxC32: 32-Bit Capture Select bit 1 = 32-Bit timer resource capture 0 = 16-Bit timer resource capture ICxTMR: Timer Select bit (Does not affect timer selection when ICxC32 (ICxCON<8>) is `1') 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture ICxI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 295 PIC32MX FAMILY REGISTER 15-1: bit 4 ICXCON: INPUT CAPTURE X CONTROL REGISTER (CONTINUED) ICxOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICxBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty ICxM<2:0>: Input Capture Mode Select bits 111 = Interrupt Only mode 110 = Simple Capture Event mode - every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode - every 16th rising edge 100 = Prescaled Capture Event mode - every 4th rising edge 011 = Simple Capture Event mode - every rising edge 010 = Simple Capture Event mode - every falling edge 001 = Edge Detect mode - every edge (rising and falling) 000 = Capture Disable mode bit 3 bit 2-0 DS61143A-page 296 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 15-2: R-0 bit 31 R-0 bit 23 R-0 bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ICXBUF: INPUT CAPTURE X BUFFER REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 24 R-0 bit 16 R-0 bit 8 ICxBUF<31:24> ICxBUF<23:16> ICxBUF<15:8> ICxBUF<7:0> ICxBUF<31:0>: Buffer Register bits Value of the current captured input timer count (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 297 PIC32MX FAMILY 15.1 Timer Selection 15.2 Simple Capture Event Modes The input capture module can select between one of two 16-bit timers for the time base, or two 16-bit timers together to form a 32-bit timer. Setting ICTMR (ICxCON<7>) to `0' selects the Timer3 for capture. Setting ICTMR (ICxCON<7>) to 1 selects the Timer2 for capture. An input capture channel configured to support 32-bit capture, may use a 32-bit timer resource for capture. By setting ICC32 (ICxCON<8>) to `1', a 32-bit timer resource is captured. The 32-bit timer resource is routed into the module using the existing 16-bit timer inputs. The timers clock can be setup using the internal peripheral clock source, or using a synchronized external clock source applied at the TxCK pin. These modes are specified by setting the ICM (ICxCON<2:0>) bits to `010', `011', or `110'. Setting ICM = `011' configures the module to capture the timer value on any rising edge of the capture input. ICM = `010' configures the module to capture the timer on any falling edge of the capture input. Setting ICM = `110' configures the channel to capture the timer on every transition of the capture input, beginning with the edge specified by ICFEDGE (ICxCON<9>). In Simple Capture Event mode, the prescaler is not used. See Figure 15-2 for simplified timing diagrams of a simple capture event. Note: Since the capture input must be synchronized to the peripheral clock, the module captures the timer count value, which is valid 2-3 peripheral clock cycles (TPB) after the capture event. An input capture interrupt event is generated after one, two, three or four timer count captures, as configured by ICI (ICxCON<6:5>). FIGURE 15-2: SIMPLE CAPTURE EVENT TIMING DIAGRAM CAPTURE EVERY RISING EDGE Peripheral Clock Timer Count n n+1 n+2 m m+1 m+2 m+3 m+4 m+5 ICx Input Synchronized Capture Capture Data Capture Interrupt n+2 m+3 15.3 Prescaled Capture Event Modes Note: Since the capture input must be synchronized to the peripheral clock, the timer count value is captured, which is valid 2-3 peripheral clock periods after the capture event. In Prescaled Capture Event mode, the input capture module triggers a capture event on either every fourth or every sixteenth rising edge. These modes are selected by setting the ICM (ICxCON<2:0>) bits to `100' or `101', respectively. DS61143A-page 298 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY Note: It is recommended that the user disable (i.e., clear ON bit, ICxCON<15>) the capture module before switching to Prescaler Capture Event mode. Simply switching to Prescaler Capture Event mode from another active mode does not reset the prescaler and may cause an inadvertent capture event. Figure 15-3 depicts a capture event when the input capture module is in Prescaler Capture Event mode. FIGURE 15-3: PRESCALER CAPTURE EVENT TIMING DIAGRAM TPB Peripheral Clock Timer Count TICX_IN_L TICX_IN_H Capture Input Prescaler Count Prescaler Output Synchronized Capture Capture Data Capture Interrupt n+2 1 2 3 4 n n+1 n+2 n+3 n+4 15.4 Edge Detect (Hall Sensor) Mode 15.5 Interrupt Only Mode In Edge Detect mode, the input capture module captures a timer count value on every edge of the capture input. Edge Detect mode is selected by setting the ICM bit to `001'. In this mode, the capture prescaler is not used and the capture overflow bit, ICOV (ICxCON<4>) is not updated. In this mode, the Interrupt Control bits (ICI, ICxCON<6:5>) are ignored and an interrupt event is generated for every timer count capture When the Input Capture module is set for Interrupt Only mode (ICM = `111') and the device is in Sleep or Idle mode, the capture input functions as an interrupt pin. Any rising edge on the capture input triggers an interrupt. No timer values are captured and the FIFO buffer is not updated. When the device leaves Sleep or Idle mode, the interrupt signal is deasserted. In this mode, since no timer values are captured, the Timer Select bit ICTMR (ICxCON<7>) is ignored and there is no need to configure the timer source. A wakeup interrupt is generated on the first rising edge, therefore the Interrupt Control bits ICI (ICxCON<6:5>) are also ignored. The prescaler is not used in this mode. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 299 PIC32MX FAMILY EXAMPLE 15-1: INPUT CAPTURE EXAMPLE CODE /* The following code segment initialized the timer and setup the input capture module. */ ... //Initialize timer 2 T2CON = 0x0 // Stop and Init Timer TMR2 = 0x0; // Clear timer register PR2 = 0x7000; // Load period register T2CONSET = 0x8000;// Start Timer // Init IC1 module IC1CON = 0x8081;//Enable Module, use timer 2, //Capture mode 1 (capture every edge) ... //Read the capture data if available int cap_data; while( IC1CONbits.ICBNE ) // while data available in capture FIFO { cap_data = IC1BUF; ... //process data } ... DS61143A-page 300 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 16.0 Note: OUTPUT COMPARE This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The following are some of the key features: * Multiple output compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Programmable selection of 16-bit or 32-bit time bases. * Can operate from either of two available 16-bit time bases or a single 32-bit time base. The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output Logic 3 OCM<2:0> Mode Select S R Q OCx(1) Output Enable OCFA or OCFB (see Note 2) Comparator 0 1 OCTSEL 0 1 16 16 TMR register inputs from time bases (see Note 3). Period match signals from time bases (see Note 3). Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC3 channels. The OCFB pin controls the OC4-OC5 channels. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 301 PIC32MX FAMILY TABLE 16-1: Virtual Address BF80_3000 OUTPUT COMPARE SFR SUMMARY Name OC1CON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- ON -- Bit 30/22/14/6 -- -- FRZ -- Bit 29/21/13/5 -- -- SIDL OC32 Bit 28/20/12/4 -- -- -- OCFLT Bit 27/19/11/3 -- -- -- OCTSEL Bit 26/18/10/2 -- -- -- Bit 25/17/9/1 -- -- -- OCM<2:0> Bit 24/16/8/0 -- -- -- BF80_3004 BF80_3008 BF80_300C BF80_3010 OC1CONCLR OC1CONSET OC1CONINV OC1R 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in OC1CON, Read yields an undefined value. Write sets selected bits in OC1CON, Read yields an undefined value. Write inverts selected bits in OC1CON, Read yields an undefined value. OC1R<31:24> OC1R<23:16> OC1R<15:8> OC1R<7:0> Write clears selected bits in OC1R, Read yields an undefined value. Write sets selected bits in OC1R, Read yields an undefined value. Write inverts selected bits in OC1R, Read yields an undefined value. OC1RS<31:24> OC1RS<23:16> OC1RS<15:8> OC1RS<7:0> Write clears selected bits in OC1RS, Read yields an undefined value. Write sets selected bits in OC1RS, Read yields an undefined value. Write inverts selected bits in OC1RS, Read yields an undefined value. -- -- ON -- -- -- FRZ -- -- -- SIDL OC32 -- -- -- OCFLT -- -- -- OCTSEL -- -- -- -- -- -- OCM<2:0> -- -- -- BF80_3014 BF80_3018 BF80_301C BF80_3020 OC1RCLR OC1RSET OC1RINV OC1RS 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3024 BF80_3028 BF80_302C BF80_3200 OC1RSCLR OC1RSSET OC1RSINV OC2CON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3204 BF80_3208 BF80_320C BF80_3210 OC2CONCLR OC2CONSET OC2CONINV OC2R 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in OC2CON, Read yields an undefined value. Write sets selected bits in OC2CON, Read yields an undefined value. Write inverts selected bits in OC2CON, Read yields an undefined value. OC2R<31:24> OC2R<23:16> OC2R<15:8> OC2R<7:0> Write clears selected bits in OC2R, Read yields an undefined value. Write sets selected bits in OC2R, Read yields an undefined value. Write inverts selected bits in OC2R, Read yields an undefined value. OC2RS<31:24> OC2RS<23:16> OC2RS<15:8> OC2RS<7:0> Write clears selected bits in OC2RS, Read yields an undefined value. Write sets selected bits in OC2RS, Read yields an undefined value. Write inverts selected bits in OC2RS, Read yields an undefined value. -- -- ON -- -- -- FRZ -- -- -- SIDL OC32 -- -- -- OCFLT -- -- -- OCTSEL -- -- -- -- -- -- OCM<2:0> -- -- -- BF80_3214 BF80_3218 BF80_321C BF80_3220 OC2RCLR OC2RSET OC2RINV OC2RS 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3224 BF80_3228 BF80_322C BF80_3400 OC2RSCLR OC2RSSET OC2RSINV OC3CON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3404 BF80_3408 BF80_340C BF80_3410 OC3CONCLR OC3CONSET OC3CONINV OC3R 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in OC3CON, Read yields an undefined value. Write sets selected bits in OC3CON, Read yields an undefined value. Write inverts selected bits in OC3CON, Read yields an undefined value. OC3R<31:24> OC3R<23:16> OC3R<15:8> OC3R<7:0> Write clears selected bits in OC3R, Read yields an undefined value. Write sets selected bits in OC3R, Read yields an undefined value. Write inverts selected bits in OC3R, Read yields an undefined value. BF80_3414 BF80_3418 BF80_341C OC3RCLR OC3RSET OC3RINV 31:0 31:0 31:0 DS61143A-page 302 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 16-1: Virtual Address BF80_3420 OUTPUT COMPARE SFR SUMMARY (CONTINUED) Name OC3RS 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 OC3RS<31:24> OC3RS<23:16> OC3RS<15:8> OC3RS<7:0> Write clears selected bits in OC3RS, Read yields an undefined value Write sets selected bits in OC3RS, Read yields an undefined value Write inverts selected bits in OC3RS, Read yields an undefined value -- -- ON -- -- -- FRZ -- -- -- SIDL OC32 -- -- -- OCFLT -- -- -- OCTSEL -- -- -- -- -- -- OCM<2:0> -- -- -- BF80_3424 BF80_3428 BF80_342C BF80_3600 OC3RSCLR OC3RSSET OC3RSINV OC4CON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3604 BF80_3608 BF80_360C BF80_3610 OC4CONCLR OC4CONSET OC4CONINV OC4R 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in OC4CON, read yields an undefined value Write sets selected bits in OC4CON, read yields an undefined value Write inverts selected bits in OC4CON, read yields an undefined value OC4R<31:24> OC4R<23:16> OC4R<15:8> OC4R<7:0> Write clears selected bits in OC4R, read yields an undefined value Write sets selected bits in OC4R, read yields an undefined value Write inverts selected bits in OC4R, read yields an undefined value OC4RS<31:24> OC4RS<23:16> OC4RS<15:8> OC4RS<7:0> Write clears selected bits in OC4RS, read yields an undefined value Write sets selected bits in OC4RS, read yields an undefined value Write inverts selected bits in OC4RS, read yields an undefined value -- -- ON -- -- -- FRZ -- -- -- SIDL OC32 -- -- -- OCFLT -- -- -- OCTSEL -- -- -- -- -- -- OCM<2:0> -- -- -- BF80_3614 BF80_3618 BF80_361C BF80_3620 OC4RCLR OC4RSET OC4RINV OC4RS 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3624 BF80_3628 BF80_362C BF80_3800 OC4RSCLR OC4RSSET OC4RSINV OC5CON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3804 BF80_3808 BF80_380C BF80_3810 OC5CONCLR OC5CONSET OC5CONINV OC5R 31:0 31:0 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in OC5CON, read yields an undefined value Write sets selected bits in OC5CON, read yields an undefined value Write inverts selected bits in OC5CON, read yields an undefined value OC5R<31:24> OC5R<23:16> OC5R<15:8> OC5R<7:0> Write clears selected bits in OC5R, read yields an undefined value Write sets selected bits in OC5R, read yields an undefined value Write inverts selected bits in OC5R, read yields an undefined value OC5RS<31:24> OC5RS<23:16> OC5RS<15:8> OC5RS<7:0> Write clears selected bits in OC5RS, read yields an undefined value Write sets selected bits in OC5RS, read yields an undefined value Write inverts selected bits in OC5RS, read yields an undefined value IPTMR<31:24> IPTMR<23:16> -- -- I2CMIF CNIF INT3IF INT1IF FRZ -- I2CSIF OC5IF OC3IF OC1IF -- -- U1EIF IC5IF IC3IF IC1IF -- INT4EP U1TXIF T5IF T3IF T1IF IPRST INT3EP U1RXIF INT4IF INT2IF INT0IF INT2EP SPI1RXIF OC4IF OC2IF CS1IF TPC[2:0> INT1EP SPI1TXIF IC4IF IC3IF CS0IF INT0EP SPI1EIF T4IF T2IF CTIF BF80_3814 BF80_3818 BF80_381C BF80_3820 OC5RCLR OC5RSET OC5RINV OC5RS 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_3824 BF80_3828 BF80_382C 0xBF881000 OC5RSCLR OC5RSSET OC5RSINV INTCON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 0xBF881010 IFS0 31:24 23:16 15:8 7:0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 303 PIC32MX FAMILY TABLE 16-1: Virtual Address 0xBF881040 OUTPUT COMPARE SFR SUMMARY (CONTINUED) Name IEC0 31:24 23:16 15:8 7:0 Bit 31/23/15/7 I2CMIE CNIE INT3IE INT1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON TGATE -- -- ON TGATE -- -- FRZ Bit 30/22/14/6 I2CSIE OC5IE OC3IE OC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FRZ Bit 29/21/13/5 U1EIE IC5IE IC3IE IC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL TCKPS<2:0> -- -- SIDL TCKPS<2:0> -- -- -- -- -- -- Bit 28/20/12/4 U1TXIE T5IE T3IE T1IE Bit 27/19/11/3 U1RXIE INT4IE INT2IE INT0IE INT1IP<2:0> OC1IP<2:0> IC1IP<2:0> T1IP<2:0> INT2IP<2:0> OC2IP<2:0> IC2IP<2:0> T2IP<2:0> INT3IP<2:0> OC3IP<2:0> IC3IP<2:0> T3IP<2:0> INT4IP<2:0> OC4IP<2:0> IC4IP<2:0> T4IP<2:0> CNIP<2:0> OC5IP<2:0> IC5IP<2:0> T5IP<2:0> -- -- -- T32 -- -- -- -- PR2<31:24> PR2<23:16> PR2<15:8> PR2<7:0> PR3<31:24> PR3<23:16> PR3<15:8> PR3<7:0> -- -- -- -- -- -- -- -- -- -- -- TCS -- -- -- TCS Bit 26/18/10/2 SPI1RXIE OC4IE OC2IE CS1IE Bit 25/17/9/1 SPI1TXIE IC4IE IC3IE CSOIE Bit 24/16/8/0 SPI1EIE T4IE T2IE CTIE 0xBF881080 IPC1 31:24 23:16 15:8 7:0 INT1IS<1:0> OC1IS<1:0> IC1IS<1:0> T1IS<1:0> INT2IS<1:0> OC2IS<1:0> IC2IS<1:0> T2IS<1:0> INT3IS<1:0> OC3IS<1:0> IC3IS<1:0> T3IS<1:0> INT4IS<1:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> CNIS<1:0> OC5IS<1:0> IC5IS<1:0> T5IS<1:0> -- -- -- -- -- -- -- -- 0xBF881090 IPC2 31:24 23:16 15:8 7:0 0xBF8810A0 IPC3 31:24 23:16 15:8 7:0 0xBF8810B0 IPC4 31:24 23:16 15:8 7:0 0xBF8810C0 IPC5 31:24 23:16 15:8 7:0 BF80_0800 T2CON 31:24 23:16 15:8 7:0 BF80_0A00 T3CON 31:24 23:16 15:8 7:0 BF80_0820 PR2 31:24 23:16 15:8 7:0 BF80_0A20 PR3 31:24 23:16 15:8 7:0 DS61143A-page 304 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 16-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- R/W-0 OC32 R-0 OCFLT R/W-0 OCTSEL R/W-0 R/W-0 OCM<2:0> bit 0 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' ON: Output Compare Peripheral On bit 1 = Output compare peripheral is enabled. The status of other bits in the register are not affected by setting this bit 0 = Output compare peripheral is disabled and not drawing current. SFR modifications are allowed. The status of other bits in this register are not affected by clearing this bit FRZ: Freeze in Debug Exception Mode bit(1) 1 = Freeze operation when CPU enters in Debug Exception mode 0 = Continue operation when CPU enters in Debug Exception mode SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode Unimplemented: Read as `0' OC32: 32-Bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred Note: (This bit is only used when OCM<2:0> = 111. OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for compare x 0 = Timer2 is the clock source for compare x Note: OCTSEL must be set to `1' when using 32-bit mode (OC32 = 1) bit 14 bit 13 bit 12-6 bit 5 bit 4 bit 3 Note 1: 2: FRZ is writable in Debug Exception mode only, it is forced to read `0' in Normal mode. Reads as `0' in modes other than PWM mode. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 305 PIC32MX FAMILY bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare peripheral is disabled FRZ is writable in Debug Exception mode only, it is forced to read `0' in Normal mode. Reads as `0' in modes other than PWM mode. Note 1: 2: DS61143A-page 306 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY Register 16-1: OCxR: OUTPUT COMPARE x COMPARE PRIMARY REGISTER R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 OCR<31:24> OCR<23:16> OCR<15>8> OCR<7:0> OCxR<31:16>: Upper 16 bits of 32-bit compare value when OC32 (OCxCON<5>) = 1 OCxR<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 307 PIC32MX FAMILY Register 16-2: OCxRS: OUTPUT COMPARE x COMPARE SECONDARY REGISTER R/W-x bit 31 R/W-x bit 23 R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 OCRS<31:24> OCRS<23:16> OCRS<5>8> OCRS<7:0> OCxRS<31:16>: Upper 16 bits of 32-bit compare value, when OC32 (OCxCON<5>) = 1 OCxRS<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value DS61143A-page 308 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 16.1 Setup for Single Output Change There are three modes of operation that change the state of the output pin; these modes can be referred to as drive high, drive low and toggle. The configuration for these modes is identical, the mode is selected by the OCM bits. For this example, Tx will represent Timer2. Drive High: When the OCM control bits (OCxCON<2:0>) are set to `001', the selected output compare channel initializes the OCx pin to the low state and drives the output pin high when a compare event occurs. Drive Low: When the OCM control bits (OCxCON<2:0>) are set to `010', the selected output compare channel initializes the OCx pin to the high state and drives the output pin low when a compare event occurs. Toggle: When the OCM control bits (OCxCON<2:0>) are set to `011', the selected output compare channel OCx pin is not initialized. The OCx pin is driven to the opposite state when a compare event occurs. To generate a output change signal, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): Determine the timer clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). 3. Determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. 4. Configure the timer to be used as the time base for 16 or 32-bit mode by writing to the T32 bit (TxCON 16.2 Setup for Single Output Pulse Generation When the OCM control bits (OCxCON<2:0>) are set to `100', the selected output compare channel initializes the OCx pin to the low state and generates a single output pulse. To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): For this example Tx will represent Timer2. 1. Determine the timer clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. Determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. Configure the timer to be used as the time base for 16 or 32-bit mode by writing to the T32 bit (TxCON 2. 3. 4. 5. 6. 7. 8. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 309 PIC32MX FAMILY 9. Set the OCM bits to `100' and the OCTSEL (OCxCON<3>) bit to the desired timer source. The OCx pin state will now be driven low. 10. Set the ON (TxCON<15>) bit to `1' which enables the compare time base to count. 11. Upon the first match between TMRx and OCxR, the OCx pin will be driven high. 12. When the incrementing timer matches the Secondary Compare register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. No additional pulses are driven onto the OCx pin and it remains at low. As a result of the second compare match event, the OCxIF interrupt flag bit is set, which will result in an interrupt if it is enabled, by setting the OCxIE bit. For further information on peripheral interrupts, refer to Section 9.0 "Interrupts". 13. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to `100'. Disabling and re-enabling of the timer and clearing the TMRx register are not required, but may be advantageous for defining a pulse from a known event time boundary. EXAMPLE 16-1: // // // EXAMPLE CODE The following code example will set the Output Compare 1 module for interrupts on the single pulse event and select Timer 2 as the clock source for the compare time base. T2CON = 0x0010; OC1CON = 0x0000; OC1CON = 0x0004; OC1R = 0x3000; OC1RS = 0x3003; PR2 = 0x3003; // Configure Timer 2 for a prescaler of 2 // // // // // // // // // // // Turn off OC1 while doing setup. Configure for single pulse mode Initialize primary Compare Register Initialize secondary Compare Register Set period (PR2 is now 32-bits wide) configure int Clear the OC1 interrupt flag Enable OC1 interrupt Set OC1 interrupt subpriority to 3, the highest level Set subpriority to 3, maximum IF0CLR = 0x00000080; IE0SET = 0x00000080; IPC1SET = 0x0030000; IPC1SET = 0x00000003; T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable timer2 // Enable the OC1 module // Example code for Output Compare 1 ISR: #pragma interupt OC1IntHandler ipl4 vector 6 void CmpIntHandler(void) { // insert user code here IFS0CLR = 0x00000080; // Clear the OC1 interrupt flag } DS61143A-page 310 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 16.3 Setup for Continuous Output Pulse Generation 16.4 Pulse-Width Modulation Mode When the OCM control bits (OCxCON<2:0>) are set to `101', the selected output compare channel initializes the OCx pin to the low state and generates output pulses on each and every compare match event. For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation). For this example, Tx will represent Timer2. 1. Determine the timer clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. Calculate time to the rising edge of the output pulse relative to the TMRx start value (0000h). Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. Determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. Configure the timer to be used as the time base for 16 or 32-bit mode by writing to the T32 bit (TxCON 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 311 PIC32MX FAMILY 16.4.1 PWM PERIOD 16.4.2 PWM DUTY CYCLE The PWM period is specified by writing to PR, the Timer Period register. The PWM period can be calculated using Equation 16-1. The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be written to at any time, but the duty cycle value is not latched into OCxR until a match between the PR and timer occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. In the PWM mode, OCxR is a read-only register. Some important boundary parameters of the PWM duty cycle include: * If the Duty Cycle register, OCxR, is loaded with 0000h, the OCx pin will remain low (0% duty cycle). * If OCxR is greater than PR (Timer Period register), the pin will remain high (100% duty cycle). * If OCxR is equal to PR, the OCx pin will be low for one time base count value and high for all other count values. See Example 16-2 for PWM mode timing details. Table 16-2 shows example PWM frequencies and resolutions for a device peripheral bus operating at 10 MHz. EQUATION 16-1: CALCULATING THE PWM PERIOD PWM Period = [(PRy) + 1> * TPB * (TMRy Prescale Value)] PWM Frequency = 1/[PWM Period] Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. EQUATION 16-2: CALCULATION FOR MAXIMUM PWM RESOLUTION log10 Maximum PWM Resolution (bits) = FPB (FPWM * TMRy * Prescaler) bits log10(2) EXAMPLE 16-2: PWM PERIOD AND DUTY CYCLE CALCULATION Desired PWM frequency is 52.08 kHz, FPB = 10 MHz Timer 2 prescale setting: 1:1 1/52.08 kHz 19.20 s PR2 = = = (PR2 + 1) * FBP * (Timer2 prescale value) (PR2 + 1) * 0.1 s * (1) 191 Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz PWM frequency and a 10 MHz peripheral bus clock rate. 1/52.08 kHz = 19.20 s = 192 = log10(192) = PWM Resolution= 2PWM RESOLUTION * 1/10 MHz * 1 2PWM RESOLUTION * 100 ns * 1 2PWM RESOLUTION (PWM Resolution) * log10(2) 7.6 bits Note: If the PR value exceeds 16-bits the module must be used in 32-bit mode to maintain the calculated PWM resolution. If reduced resolution is acceptable the Timer prescaler may be increased and the calculation repeated until the result is a 16-bit value. Increasing the Timer prescaler to allow operation in 16-bit mode may result in reduced PWM resolution. DS61143A-page 312 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 16-3: // // // // // The for PWM the are PWM MODE PULSE SETUP AND INTERRUPT SERVICING (32-BIT MODE) following code example will set the Output Compare 1 module PWM mode with FAULT pin disabled, a 50% duty cycle and a frequency of 52.08 kHz at FPB = 40 MHz. Timer2 is selected as clock for the PWM time base and Output Compare 1 interrupts enabled. // // // // // // // // // // // Turn off OC1 while doing setup. Initialize primary Compare Register Initialize secondary Compare Register Configure for PWM mode, Fault pin Disabled Set period configure int Clear the OC1 interrupt flag Enable OC1 interrupt Set OC1 interrupt priority to 7, the highest level Set subpriority to 3, maximum OC1CON = 0x0000; OC1R = 0x00600000; OC1RS = 0x00600000; OC1CON = 0x0006; PR2 = 0x00600000; IFS0 &= ~0x00000080; IEC0 |= 0x00000080; IPC1 |= 0x001C0000; IPC1 |= 0x00000003; T2CON |= 0x8000; OC1CON |= 0x8000; // Enable timer2 // turn on OC1 module // Example code for Output Compare 1 ISR: #pragma interupt OC1IntHandler ipl4 vector 36 void OC1IntHandler(void) { // insert user code here IFS0CLR = 0x00000080; // Clear the interrupt flag } (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 313 PIC32MX FAMILY TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 10 MHZ (16-BIT MODE) 19.5 Hz 8 0xFA65 16 153 Hz 1 0xFF4E 16 305 Hz 1 0x8011 15 2.44 kHz 1 0x1001 12 9.77 kHz 1 0x03FE 10 78.1 kHz 1 0x007F 7 313 kHz 1 0x001E 5 PWM Frequency Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 30 MHZ (16-BIT MODE) 58 Hz 8 0xFC8E 16 458 Hz 1 0xFFDD 16 916 Hz 1 0x7FEE 15 7.32 kHz 1 0x1001 12 29.3 kHz 1 0x03FE 10 234 kHz 1 0x007F 7 938 kHz 1 0x001E 5 PWM Frequency Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 50 MHZ (16-BIT MODE) 58 Hz 64 0x349C 13.7 458 Hz 8 0x354D 13.7 916 Hz 1 0xD538 15.7 7.32 kHz 1 0x1AAD 12.7 29.3 kHz 1 0x06A9 10.7 234 kHz 1 0x00D4 7.7 938 kHz 1 0x0034 5.7 PWM Frequency Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) TABLE 16-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 50 MHZ (16-BIT MODE) 100 Hz 8 0xF423 15.9 200 Hz 8 0x7A11 14.9 500 Hz 8 0x30D3 13.6 1 kHz 1 0xC34F 15.6 2 kHz 8 0x0C34 11.6 5 kHz 1 0x270F 13.3 10 kHz 1 0x1387 12.3 PWM Frequency Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) TABLE 16-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 50 MHZ (16-BIT MODE) 100 Hz 8 0xF423 15.9 200 Hz 4 0xF423 15.9 500 Hz 2 0xC34F 15.6 1 kHz 1 0x0C34F 15.6 2 kHz 1 0x61A7 14.6 5 kHz 1 0x270F 13.3 10 kHz 1 0x1387 12.3 PWM Frequency Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) TABLE 16-7: PWM Frequency Period Register Value (hex) Resolution (bits) (decimal) Resolution (bits) EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS CLOCK OF 50 MHZ (32-BIT MODE) 100 Hz 1 0x0007A11F 18.9 200 Hz 1 0x0003D08F 17.9 500 Hz 1 0x0001869F 16.6 1 kHz 1 2 kHz 1 5 kHz 8 0x000004E1 10.3 10 kHz 1 0x00001387 12.3 0x0000C34F 0x000061A7 15.6 14.6 DS61143A-page 314 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 16.5 Output Compare Register I/O Pin Control When the output compare module is enabled, the I/O pin direction is controlled by the compare module. The compare module returns the I/O pin control back to the appropriate pin LAT and TRIS control bits when it is disabled. When the PWM with Fault Protection Input mode is enabled, the OCFx Fault pin must be configured as an input by setting the respective TRIS SFR bit. The OCFx Fault input pin is not automatically configured as an input when PWM with Fault Input mode is selected. TABLE 16-8: Pin Name OC1 OC2 OC3 OC4 OC5 OCFA OCFB Legend: Note 1: 2: 3: 4: PINS ASSOCIATED WITH OUTPUT COMPARE MODULES 1- 5 Module Control ON(2) ON(2) ON(2) ON(2) ON (2) Controlling Bit Field OCM<2:0>(1,3) OCM<2:0>(1,3) OCM<2:0>(1,3) OCM<2:0>(1,3) OCM<2:0>(1,3) OCM<2:0>(1,3) OCM<2:0>(1,3) Required TRIS bit Setting -- -- -- -- -- Input Input Pin Type D, O D, O D, O D, O D, O D, I D, I Buffer Type -- -- -- -- -- ST ST Description Output Compare/PWM Channel 1 Output Compare/PWM Channel 2 Output Compare/PWM Channel 3 Output Compare/PWM Channel 4 Output Compare/PWM Channel 5 PWM Fault Protection A Input (For Channels 1-3)(4) PWM Fault Protection B Input (For Channels 4 -5)(4) ON(2) ON(2) ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output, A = Analog, D = Digital All pins are subject to device pin priority control. ON (OCxCON<15>) = 1. When the module is turned off, pins controlled by the module are released. Mode select bits OCM<2:0> (CMxCON<2:0>). Use of PWM Fault input is optional and is controlled by the OCM bits. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 315 PIC32MX FAMILY NOTES: DS61143A-page 316 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 17.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. Following are some of the key features of this module: * * * * * * * * Master and Slave Modes Support Four Different Clock Formats Framed SPI Protocol Support User Configurable 8-Bit, 16-Bit and 32-Bit Data Width Separate SPI Data Registers for Receive and Transmit Programmable Interrupt Event on every 8-Bit, 16-Bit and 32-Bit Data Transfer Operation during CPU Sleep and Idle Mode Fast Bit Manipulation using CLR, SET and INV Registers The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The PIC32MX SPI module is compatible with Motorola(R) SPI and SIOP interfaces. TABLE 17-1: Available SPI Modes Normal Mode Framed Mode SPI FEATURES SPI SPI Frame Frame Master Slave Master Slave Yes Yes Yes Yes -- Yes -- Yes 8-Bit, 16-Bit and 32-Bit Modes Yes Yes Selectable Clock Pulses and Edges Yes Yes Selectable Frame Sync Pulses and Edges -- Yes Slave Select Pulse Yes No (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 317 PIC32MX FAMILY FIGURE 17-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Registers share address SPIxBUF SPIxRXB SPIxTXB Transmit Receive SPIxSR SDIx SDOx Slave Select and Frame Sync Control bit 0 Shift Control Clock Control Edge Select Baud Rate Generator SCKx Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. Enable Master Clock SSx PBCLK DS61143A-page 318 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 17.1 SPI Registers SPI1 SFR SUMMARY Name SPI1CON 31:24 23:16 15:8 7:0 BF80_5804 SPI1CONCLR BF80_5808 SPI1CONSET BF80_580C BF80_5810 SPI1CONINV SPI1STAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_5814 SPI1STATCLR BF80_5820 SPI1BUF 31:0 31:24 23:16 15:8 7:0 BF80_5830 SPI1BRG 31:24 23:16 15:8 7:0 BF80_5834 SPI1BRGCLR BF80_5838 SPI1BRGSET BF80_583C SPI1BRGINV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- -- -- -- -- BRG<7:0> Write clears selected bits in SPI1BRG, read yields an undefined value Write sets selected bits in SPI1BRG, read yields an undefined value Write inverts selected bits in SPI1BRG, read yields an undefined value -- -- -- -- -- -- -- SPIROV Bit 31/23/15/7 FRMEN -- ON SSEN Bit 30/22/14/6 FRMSYNC -- FRZ CKP Bit 29/21/13/5 FRMPOL -- SIDL MSTEN Bit 28/20/12/4 -- -- DISSDO -- Bit 27/19/11/3 -- -- MODE32 -- Bit 26/18/10/2 -- -- MODE16 -- Bit 25/17/9/1 -- SPIFE SMP -- Bit 24/16/8/0 -- -- CKE -- TABLE 17-2: Virtual Address BF80_5800 Write clears selected bits in SPI1CON, read yields an undefined value Write sets selected bits in SPI1CON, read yields an undefined value Write inverts selected bits in SPI1CON, read yields an undefined value -- -- -- -- -- -- -- -- -- -- SPIBUSY SPITBE -- -- -- -- -- -- -- -- -- -- -- SPIRBF Write clears selected bits in SPI1STAT, read yields an undefined value DATA<31:24> DATA<23:16> DATA<15:8> DATA<7:0> -- -- -- -- -- -- -- -- -- -- -- BRG<8> TABLE 17-3: Virtual Address BF88_1040 BF88_1010 BF88_10C0 Note: SPI1 INTERRUPT REGISTER SUMMARY Name IEC0 IFS0 IPC5 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 31:24 23:16 31:24 I2C1MIE SPI1EIE I2C1MIF SPI1EIF -- I2C1SIE OC5IE I2C1SIF OC5IF -- I2C1BIE IC5IE I2C1BIF IC5IF -- U1TXIE T5IE U1TXIF T5IF U1RXIE INT4IE U1RXIF INT4IF SPI1IP<2:0> U1EIE OC4IE U1EIF OC4IF SPI1RXIE IC4IE SPI1RXIF IC4IF SPI1TXIE T4IE SPI1TXIF T4IF SPI1IS<1:0> This summary table contains partial register definitions that only pertain to the SPI1 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 319 PIC32MX FAMILY TABLE 17-4: Virtual Address BF80_5A00 SPI2 SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 FRMEN -- ON SSEN Bit 30/22/14/6 FRMSYNC -- FRZ CKP Bit 29/21/13/5 FRMPOL -- SIDL MSTEN Bit 28/20/12/4 -- -- DISSDO -- Bit 27/19/11/3 -- -- MODE32 -- Bit 26/18/10/2 -- -- MODE16 -- Bit 25/17/9/1 -- SPIFE SMP -- Bit 24/16/8/0 -- -- CKE -- SPI2CON BF80_5A04 SPI2CONCLR BF80_5A08 SPI2CONSET BF80_5A0C SPI2CONINV BF80_5A10 SPI2STAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears selected bits in SPI2CON, read yields an undefined value Write sets selected bits in SPI2CON, read yields an undefined value Write inverts selected bits in SPI2CON, read yields an undefined value -- -- -- SPIROV -- -- -- -- -- -- -- -- -- -- SPIBUSY SPITBE -- -- -- -- -- -- -- -- -- -- -- SPIRBF BF80_5A14 SPI2STATCLR BF80_5A20 SPI2BUF 31:0 31:24 23:16 15:8 7:0 Write clears selected bits in SPI2STAT, read yields an undefined value DATA<31:24> DATA<23:16> DATA<15:8> DATA<7:0> -- -- -- -- -- -- -- -- -- -- -- -- BRG<7:0> Write clears selected bits in SPI2BRG, read yields an undefined value Write sets selected bits in SPI2BRG, read yields an undefined value Write inverts selected bits in SPI2BRG, read yields an undefined value -- -- -- -- -- -- -- -- -- -- -- BRG<8> BF80_5A30 SPI2BRG 31:24 23:16 15:8 7:0 BF80_5A34 SPI2BRGCLR BF80_5A38 SPI2BRGSET BF80_5A3C SPI2BRGINV 31:0 31:0 31:0 TABLE 17-5: Virtual Address BF88_1060 BF88_1030 BF88_10E0 SPI2 INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC7 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 SPI2RXIE SPI2TXIE SPI2RXIF -- SPI2EIE SPI2EIF -- CMP2IE CMP2IF CMP1IE CMP1IF SPI2IP<2:0> PMPIE PMPIF AD1IE AD1IF CNIE CNIF 7:0 23:16 SPI2TXIF -- SP2IS<1:0> Note: This summary table contains partial register definitions that only pertain to the SPI2 peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A-page 320 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 17-1: R/W-0 FRMEN bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 SSEN bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CKP R/W-0 MSTEN U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 FRZ R/W-0 SIDL R/W-0 DISSDO R/W-0 MODE32 R/W-0 MODE16 R/W-0 SMP U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPIFE SPIXCON: SPI CONTROL REGISTER R/W-0 FRMSYNC R/W-0 FRMPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 CKE bit 8 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low Unimplemented: Read as `0' SPIFE: Frame Sync Pulse Edge Select bit (framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock Unimplemented: Read as `0' ON: SPI Peripheral On bit 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled FRZ: Freeze in DEBUG Exception Mode bit 1 = Freeze operation when CPU enters Debug Exception mode 0 = Continue operation when CPU enters Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to `0' in Normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 30 bit 29 bit 28-18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 321 PIC32MX FAMILY bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits 1x = 32-bit data width 01 = 16-bit data width 00 = 8-bit data width SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN = 0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) Note: The CKE bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Unimplemented: Read as `0' bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-0 DS61143A-page 322 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 17-2: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-12 bit 11 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SPIROV U-0 -- U-0 -- R-0 SPITBE U-0 -- U-0 -- R-0 SPIRBF bit 0 U-0 -- U-0 -- U-0 -- R-0 SPIBUSY U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- SPIXSTAT: SPI STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle Unimplemented: Read as `0' SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software. Unimplemented: Read as `0' SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. Unimplemented: Read as `0' Unimplemented: Read as `0' SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIXRXB is not full Automatically set in hardware when SPI transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. bit 10-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 323 PIC32MX FAMILY 17.2 Master and Slave Modes The PIC32MX SPI module operates in normal Master or Slave modes and offers the following additional modes: * * * * Framed Master Framed Slave 8, 16, 32-Bit Data Width Transfers Slave Select (Slave mode only) Two control bits, MODE32 and MODE16 (SPIxCON<11:10>), define the mode of operation. To change the mode of operation on the fly, the SPI module must be idle, i.e., not performing any transactions. If the SPI module is switched off (SPIxCON<15> = 0), the new mode will be available when the module is again switched on. The number of clock pulses at the SCKx pin are dependent on the selected mode of operation. For 8-Bit mode, 8 clocks; for 16-Bit mode, 16 clocks; and for 32-Bit mode, 32 clocks are required. Below is a typical system Master - Slave connection diagram. 17.2.1 8, 16, 32-BIT OPERATION The PIC32MX SPI module allows three types of data widths when transmitting and receiving data over an SPI bus. The selection of data width determines the minimum length of SPI data. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION PIC32MX [SPI Master] SDOx SDIx PROCESSOR 2 [SPI Slave] Serial Receive Buffer (SPIxRXB)(2) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSB LSB SDIx SDOx Shift Register (SPIxSR) MSB LSB Serial Transmit Buffer (SPIxTXB)(2) Serial Transmit Buffer (SPIxTXB) SPI Buffer (SPIxBUF) SCKx Serial Clock SCKx SPI Buffer (SPIxBUF) GPIO/SSx . SSx(1) MSTEN (SPIxCON<5>) =1 SSEN (SPIxCON<7>) = 1 and MSTEN (SPIxCON<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to SPIxBUF and read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. DS61143A-page 324 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 17.2.2 MASTER MODE In Master mode, data from the SPIxBUF register is transmitted synchronously on the SDO (output) pin while synchronous data is received from the slave device on the SDI (input) pin. In this mode, the Master controls the synchronous data transfer with the SCK clock pin by generating 8, 16 or 32 clock pulses, depending on the selected data size. * Enable SPI module when CPU idle - SIDL (SPIxCON<13>) = 0 17.2.2.3 Master Mode Initialization The following steps should be performed to setup the SPI module for the Master mode of operation: 1. 2. 3. 4. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If interrupts are used, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register. Write the Baud Rate register, SPIxBRG. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register. Enable SPI operation by setting the ON bit (SPIxCON<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. Note 1: When using the Slave Select mode, the SSx or another GPIO pin is used to control the slave's SSx input. The pin must be controlled in software. 2: The user must turn off the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured. 3: The SPI device must be turned off prior to changing the mode from Slave to Master. 4: The SPIxSR register cannot be written to directly by the user. All writes to the SPIxSR register are performed through the SPIxBUF register. 17.2.2.1 Master Mode Operations In Master mode the SCK and SDO pins are outputs and the SDI pin is an input. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). In Master mode, the SCK clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. Refer to the timing diagram shown in Figure 17-3 to determine the appropriate settings. In Master mode, the data transfers can be 8, 16, or 32-bits and are configured using control bits, MODE<32,16> (SPIxCON<11:10>). Refer to Section 17.2.1 "8, 16, 32-Bit Operation" for details. In Master mode, the system clock is divided and then used as the serial clock. The division is based on the settings in the SPIxBRG register. Refer to Section 17.2.5 "SPI Master Mode Clock Frequency". 5. 6. 7. 8. 9. 17.2.2.2 Master SPIxCON Configuration The following bits must be configured as shown for the Master mode of operation when configuring the SPIxCON register: * Enable Master Mode MSTEN (SPIxCON<5>) = 1. * Disable Framed SPI support FRMEN (SPIxCON<31>) = 0 The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - DISSDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = 01 * Sample data input at middle - SMP (SPIxCON<9>) = 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 325 PIC32MX FAMILY FIGURE 17-3: User writes to SPIxBUF SPIxTXB to SPIxSR(3) SPITBE SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 0) SDOx (CKE = 0) SDOx (CKE = 1) SDIx(2) (SMP = 0) Input Sample(2) (SMP = 0) SDIx (SMP = 1) Input Sample (SMP = 1) SPIxRXIF Approx. 2 SYSCLK latency to set SPIxRXIF flag bit SPIxSR moved into SPIxRXB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 Clock modes (clock output at the SCKx pin in Master mode)(1) SPI MASTER MODE OPERATION IN 8-BIT MODE (MODE32 = 0, MODE16 = 0) User writes new data during transmission bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 Two modes available for SMP control bit(4) bit 7 bit 0 SPIRBF (SPIxSTAT<0>) User reads SPIxBUF Note 1: Four SPI Clock modes are shown here to demonstrate the functionality of bits CKP (SPIxCON<6>) and CKE (SPIxCON<8>). Only one of the four modes can be chosen for operation. 2: The SDI and input samples shown here for two different values of the SMP bit (SPIxCON<9>) are strictly for demonstration purposes. Only one of the two configurations of the SMP bit can be chosen during operation. 3: If there are no pending transmissions, SPIxTXB is transferred to SPIxSR as soon as the user writes to SPIxBUF. 4: The operation for 8-Bit mode is shown. The 16-Bit and 32-Bit modes are similar. DS61143A-page 326 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 17-1: /* The following code example will initialize the SPI1 in master mode. It assumes that none of the SPI1 input pins are shared with an analog input. If so, the AD1PCFG and corresponding TRIS registers have to be properly configured. */ int rData; IEC0CLR=0x03800000; SPI1CON = 0; rData=SPI1BUF; IFS0CLR=0x03800000; IPC5CLR=0x1f000000; IPC5SET=0x0d000000; IEC0SET=0x03800000; SPI1BRG=0x1; SPI1STATCLR=0x40; SPI1CON=0x8220; // // // // // // // disable all interrupts Stops and resets the SPI1. clears the receive buffer clear any existing event clear the priority Set IPL=3, subpriority 1 Enable Rx, Tx and Error interrupts INITIALIZATION FOR 16-BIT SPI MASTER MODE // use FPB/4 clock frequency // clear the Overflow // SPI ON, 8 bits transfer, SMP=1, Master Mode // from now on, the device is ready to transmit and receive data // transmit an A character SPI1BUF='A'; (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 327 PIC32MX FAMILY 17.2.3 SLAVE MODE * Enable SPI module when CPU Idle - SIDL (SPIxCON<13>) = 0 In Slave mode, data from the SPIxBUF register is transmitted synchronously on the SDO (output) pin while synchronous data is received from the Master device on the SDI (input) pin. In this mode, the Master device controls the synchronous data transfer with the SCK clock pin by generating 8, 16 or 32 clock pulses, depending on the selected data size. 17.2.3.3 Slave Mode Initialization The following steps are used to set up the SPI module for the Slave mode of operation: 1. 2. 3. 1. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If using interrupts, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register with MSTEN ( 17.2.3.1 Slave Mode Operations The SDO pin is an output and the SPI pin is an input. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). Refer to timing diagram shown in Figure 17-4 to determine the appropriate settings. Data transfers can be 8, 16, or 32-bits and are configured using control bits. MODE<32,16> (SPIxCON<11:10>). Refer to Section 17.2.1 "8, 16, 32-Bit Operation" for details. Slave Select Synchronization: The SSx pin allows a Synchronous Slave mode. If the SSEN (SPIxCON<7>) bit is set, transmission and reception is enabled in Slave mode only if the SSx pin is driven to a low state. If the SSEN bit is not set, the SSx pin does not affect the module operation in Slave mode. 2. 3. 4. 5. 17.2.3.2 Slave SPIxCON Configuration The following bits must be configured as shown for the Slave mode of operation when configuring the SPIxCON register: * Enable Slave Mode - MSTEN (SPIxCON<5>) = 0. * Disable Framed SPI support - FRMEN (SPIxCON<31>) = 0 The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - DISSDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to Idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Disable Slave Select Pin - SSEN (SPIxCON<7>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = 01 * Sample data input at middle - SMP (SPIxCON<9>) = 0 DS61143A-page 328 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 17-4: SPI SLAVE MODE OPERATION IN 8-BIT MODE WITH SLAVE SELECT PIN DISABLED (MODE32 = 0, MODE16 = 0, SSEN = 0) SCKx Input(1) (CKP = 0 CKE = 0) SCKx Input(1) (CKP = 1 CKE = 0) SDOx Output SDIx Input (SMP = 0) Input Sample (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 (3) User writes to SPIxBUF(2) SPITBE SPIxSR to SPIxRXB SPIRBF approx. 2 SYSCLK latency to set SPIxRXIF flag bit SPIxRXIF Note 1: Two SPI Clock modes shown only to demonstrate CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bit functionality. Any combination of CKP and CKE bits can be chosen for module operation. 2: If there are no pending transmissions or a transmission in progress, SPIxBUF is transferred to SPIxSR as soon as the user writes to SPIxBUF. 3: The operation for 8-Bit mode is shown. The 16-Bit and 32-Bit modes are similar. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 329 PIC32MX FAMILY EXAMPLE 17-2: /* The following code example will initialize the SPI1 in slave mode with SSEN. It assumes that the SPI1 SS input pin on RB2 is shared with the AN2 analog input. It thus properly configures the corresponding AD1PCFG and TRIS registers bits. */ int rData; // // // // // // // // // disable all interrupts Stops and resets the SPI1. Set RB2 as a digital input Analog input pin in digital mode clears the receive buffer clear any existing event clear the priority Set IPL=3, subpriority 1 Enable Rx, Tx and Error interrupts FOR 16-BIT SPI SLAVE MODE INITIALIZATION IEC0CLR=0x03800000; SPI1CON = 0; TRISBSET = 0x4; AD1PCFGSET = 0x4; rData=SPI1BUF; IFS0CLR=0x03800000; IPC5CLR=0x1f000000; IPC5SET=0x0d000000; IEC0SET=0x03800000; SPI1STATCLR=0x40; SPI1CON=0x8000; // clear the Overflow // SPI ON, 8 bits transfer, Slave Mode // from now on, the device is ready to receive and transmit data DS61143A-page 330 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 17.2.4 FRAMED SPI MODES The module supports a very basic framed SPI protocol while operating in either Master or Slave modes. The following features are provided in the SPI module to support Framed SPI modes: * The control bit, FRMEN (SPIxCON<31>), enables Framed SPI mode and causes the SSx pin to be used as a frame synchronization pulse input or output pin. The state of the SSEN (SPIxCON<7>) is ignored. * The control bit, FRMSYNC (SPIxCON<30>), determines whether the SSx pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). * The FRMPOL (SPIxCON<29>) determines the frame synchronization pulse polarity for a single SPI clock cycle. The following framed SPI modes are supported by the SPI module: * Frame Master mode: The SPI module generates the frame synchronization pulse and provides this pulse to other devices at the SSx pin. * Frame Slave mode: The SPI module uses a frame synchronization pulse received at the SSx pin. The Framed SPI modes are supported in conjunction with the Master and Slave modes. Thus, the following framed SPI configurations are available: * * * * SPI Master mode and Frame Master mode SPI Master mode and Frame Slave mode SPI Slave mode and Frame Master mode SPI Slave mode and Frame Slave mode These four modes determine whether or not the SPI module generates the serial clock and the frame synchronization pulse. FIGURE 17-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM [SPI Master, Frame Master] SDOx Serial Receive Buffer (SPIxRXB)(3) SDIx PIC32MX PROCESSOR 2 [SPI Slave, Frame Slave] Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb LSb SDIx SDOx MSb Shift Register (SPIxSR) LSb Serial Transmit Buffer (SPIxTXB)(3) Serial Transmit Buffer (SPIxTXB) SPI Buffer (SPIxBUF) SCKx Serial Clock SCKx SPI Buffer (SPIxBUF) SSx Frame Sync Pulse(1, 2) SSx Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse. 2: Framed SPI modes require the use of all four pins, i.e., using the SSx pin is not optional. 3: The SPIxTXB and SPIxRXB registers are memory mapped to the SPIxBUF register. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 331 PIC32MX FAMILY 17.2.4.1 SPI Master Mode and Frame Master Mode Operations This Framed SPI mode is enabled by setting bits MSTEN (SPIxCON<5>) and FRMEN (SPIxCON<31>) to `1', and bit FRMSYNC (SPIxCON<30>) to `0'. In this mode, the serial clock will be output continuously at the SCKx pin, regardless of whether the module is transmitting. When SPIxBUF is written, the SSx pin will be driven active, high or low depending on bit FRMPOL (SPIxCON<29>), on the next transmit edge of the SCKx clock. The SSx pin will be active for one SCKx clock cycle. The module will start transmitting data on the same or on the next transmit edge of the SCKx, depending on the SPIFE (SPIxCON<17>) setting, as shown in Figure 17-6. A connection diagram indicating signal directions for this operating mode is shown in Figure 17-5. The SCK, SDO and SSx pins are outputs, the SDI pin is an input. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). In Master mode, the SCK clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. Refer to timing diagram shown in Figure 17-3 to determine the appropriate settings. 5. 6. 7. * Sample data input at middle - SMP (SPIxCON<9>) = 0 * Enable SPI module when CPU Idle - SIDL (SPIxCON<13>) = 0 17.2.4.3 Framed Master Mode Initialization The following steps are used to set up the SPI module for the Master mode of operation: 1. 2. 3. 4. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If using interrupts, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register. Enable SPI operation by setting the ON bit (SPIxCON<15>). Note 1: The user must turn off the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured. 2: The SPIxSR register cannot be written into directly by the user. All writes to the SPIxSR register are performed through the SPIxBUF register. 17.2.4.2 Master SPIxCON Configuration The following bits must be configured as shown for the Master mode of operation when configuring the SPIxCON register: * Enable Master Mode - MSTEN (SPIxCON<5>) = 1 * Enable Framed SPI support - FRMEN (SPIxCON<31>) = 1 * Select SSx pin as Frame Master (output) - FRMSYNC(SPIxCON<30>) = 0 The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - SDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to Idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Select SSx active-low pin polarity - FRMPOL (SPIxCON<29>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = 01 DS61143A-page 332 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 17-6: SPI MASTER, FRAME MASTER MODE32 = 0, MODE16 = 1, SPIFE = 0, FRMPOL = 1)( SCKx (CKP = 1) SCKx (CKP = 0) SSx SDOx SDIx bit 15 bit 15 bit 14 bit 14 bit 13 bit 13 bit 12 bit 12 Write to SPIxBUF Pulse generated at SSx Receive Samples at SDIx (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 333 PIC32MX FAMILY 17.2.4.4 SPI Master Mode and Frame Slave Mode Operations * Enable SPI module when CPU Idle - SIDL (SPIxCON<13>) = 0 This Framed SPI mode is enabled by setting bits MSTEN (SPIxCON<5>), FRMEN (SPIxCON<31>), and FRMSYNC (SPIxCON<30>) to `1'. The SSx pin is an input, and it is sampled on the sample edge of the SPI clock. When it is sampled active, high, or low depending on bit FRMPOL (SPIxCON<29>), data will be transmitted on the subsequent transmit edge of the SPI clock, as shown in Figure 17-7. The interrupt flag SPIxIF is set when the transmission is complete. The user must make sure that the correct data is loaded into the SPIxBUF for transmission before the signal is received at the SSx pin. A connection diagram indicating signal directions for this operating mode is shown in Figure 17-8. The SCK and SDO pins are outputs, the SDI and SSx pins are inputs. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI pin must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). In Master mode, the SCK clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. Refer to timing diagram shown in Figure 17-3 to determine the appropriate settings. 5. 6. 7. 17.2.4.6 Framed Slave Mode Initialization The following steps are used to set up the SPI module for the Slave mode of operation: 1. 2. 3. 4. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If using interrupts, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register. Enable SPI operation by setting the ON bit (SPIxCON<15>). Note 1: The user must turn off the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured. 2: The SPIxSR register cannot be written into directly by the user. All writes to the SPIxSR register are performed through the SPIxBUF register. 3: Receiving a frame sync pulse will start a transmission, regardless of whether or not data was written to SPIxBUF. If a write was not performed, zeros will be transmitted. 17.2.4.5 Master SPIxCON Configuration The following bits must be configured as shown for the Master mode of operation when configuring the SPIxCON register: * Enable Master Mode - MSTEN (SPIxCON<5>) = 1 * Enable Framed SPI support - FRMEN (SPIxCON<31>) = 1 * Select SSx pin as Frame Slave (input) - FRMSYNC (SPIxCON<30>) = 1 The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - DISSDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to Idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Select SSx active low pin polarity - FRMPOL (SPIxCON<29>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = 01 * Sample data input at middle - SMP (SPIxCON<9>) = 0 DS61143A-page 334 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 17-7: SPI MASTER, FRAME SLAVE MODE32 = 0, MODE16 = 1, SPIFE = 0, FRMPOL = 1)( SCKx (CKP = 1) (CKP = 0) FSYNC SDO SDI bit 15 bit 15 bit 14 bit 14 bit 13 bit 13 bit 12 bit 12 SCK Write to SPIxBUF Sample SSx pin for Frame Sync Pulse Receive Samples at SDIx FIGURE 17-8: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC32MX [SPI Master, Frame Slave] SDOx SDIx SCKx SSx Serial Clock PROCESSOR 2 [SPI Slave, Frame Master] SDIx SDOx SCKx SSx Frame Sync Pulse(1)(2) Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 335 PIC32MX FAMILY 17.2.4.7 SPI Slave Mode and Frame Master Mode 17.2.4.9 Framed Master Mode Initialization This Framed SPI mode is enabled by setting bit MSTEN (SPIxCON<5>) to `0', bit FRMEN (SPIxCON<31>) to `1' and bit FRMSYNC (SPIxCON<30>) to `0'. The input SPI clock will be continuous in Slave mode. The SSx pin will be an output when bit FRMSYNC is low. Therefore, when SPIBUF is written, the module will drive the SSx pin active, high or low depending on bit FRMPOL (SPIxCON<29>), on the next transmit edge of the SPI clock. The SSx pin will be driven active for one SPI clock cycle. Data transmission will start on the next SPI clock transmit edge. A connection diagram indicating signal directions for this operating mode is shown in Figure 17-9. The SDO and SSx pins are outputs and the SCK and SDI pins are inputs. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI pin must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). Refer to timing diagram shown in Figure 17-6 to determine the appropriate settings. 7. 8. The following steps are used to set up the SPI module for the Slave mode of operation: 1. 2. 3. 4. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If using interrupts, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt prioity and subpriority bits in the respective IPC5/7 register. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register. Enable SPI operation by setting the ON bit (SPIxCON<15>). Transmission (and reception) will start as soon as the master provides the serial clock. Note 1: The user must turn off the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured. 2: The SPIxSR register cannot be written into directly by the user. All writes to the SPIxSR register are performed through the SPIxBUF register. 5. 6. 17.2.4.8 Slave SPIxCON Configuration The following bits must be configured as shown for the Slave mode of operation when configuring the SPIxCON register: * Enable Slave Mode - MSTEN (SPIxCON<5>) = 1 * Enable Framed SPI support - FRMEN (SPIxCON<31>) = 1 * Select SSx pin as Frame Master (output) - FRMSYNC(SPIxCON<30>) = 0 The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - DISSDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to Idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Select SSx active low pin polarity - FRMPOL (SPIxCON<29>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = 01 * Sample data input at middle - SMP (SPIxCON<9>) = 0 * Enable SPI module when CPU Idle - SIDL (SPIxCON<13>) = 0 DS61143A-page 336 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 17-9: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC32MX [SPI Slave, Frame Master] SDOx SDIx SCKx SSx Frame Sync Pulse(1)(2) Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional). Serial Clock PROCESSOR 2 [SPI Master, Frame Slave] SDIx SDOx SCKx SSx 17.2.4.10 SPI Slave Mode and Frame Slave Mode The remaining bits are shown with example configurations and may be configured as desired: * Enable module control of SDO pin - DISSDO (SPIxCON<12>) = 0 * Configure SCK clock polarity to Idle high - CKP (SPIxCON<6>) = 1 * Configure SCK clock edge transition from Idle to active - CKE (SPIxCON<8>) = 0 * Select SSx active-low pin polarity - FRMPOL (SPIxCON<29>) = 0 * Select 16-bit data width - MODE<32,16> (SPIxCON<11:10>) = `01' * Sample data input at middle - SMP (SPIxCON<9>) = 0 * Enable SPI module when CPU Idle - SIDL (SPIxCON<13>) = 0 This Framed SPI mode is enabled by setting bits MSTEN (SPIxCON<5>) to `0', FRMEN (SPIxCON<31>) to `1', and FRMSYNC (SPIxCON<30>) to `1'. Therefore, both the SCKx and SSx pins will be inputs. The SSx pin will be sampled on the sample edge of the SPI clock. When SSx is sampled active, high or low depending on bit, FRMPOL (SPIxCON<29>), data will be transmitted on the next transmit edge of SCKx. A connection diagram indicating signal directions for this operating mode is shown in Figure 17-10. The SDO pins is an output and the SCK, SDI and SSx pins are inputs. Setting the control bit, DISSDO (SPIxCON<12>), disables transmission at the SDO pin if Receive Only mode of operation is desired. Refer to Table 17-7. The SDI pin must be configured to properly sample the data received from the slave device by configuring the sample bit, SMP (SPIxCON<9>). Refer to timing diagram shown in Figure 17-7 to determine the appropriate settings. 17.2.4.11 Slave SPIxCON Configuration The following bits must be configured as shown for the Slave mode of operation when configuring the SPIxCON register: * Enable Slave Mode - MSTEN (SPIxCON<5>) = 0 * Enable Framed SPI support - FRMEN (SPIxCON<31>) = 1 * Select SSx pin as Frame Slave (input) - FRMSYNC(SPIxCON<30>) = 1 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 337 PIC32MX FAMILY 17.2.4.12 Framed Slave Mode Initialization 7. 8. The following steps are used to set up the SPI module for the Slave mode of operation: 1. 2. 3. 4. If interrupts are used, disable the SPI interrupts in the respective IEC0/1 register. Stop and reset the SPI module by clearing the ON bit. Clear the receive buffer. If using interrupts, the following additional steps are performed: * Clear the SPIx interrupt flags/events in the respective IFS0/1 register. * Set the SPIx interrupt enable bits in the respective IEC0/1 register. * Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register. Clear the SPIROV bit (SPIxSTAT<6>). Write the selected configuration settings to the SPIxCON register. Enable SPI operation by setting the ON bit (SPIxCON<15>). Transmission (and reception) will start as soon as the master provides the serial clock. Note 1: The user must turn off the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured. 2: The SPIxSR register cannot be written into directly by the user. All writes to the SPIxSR register are performed through the SPIxBUF register. 3: Receiving a frame sync pulse will start a transmission, regardless of whether or not data was written to SPIxBUF. If a write was not performed, zeros will be transmitted. 5. 6. FIGURE 17-10: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC32MX [SPI Slave, Frame Slave] SDOx SDIx SCKx SSx Serial Clock PROCESSOR 2 [SPI Master, Frame Master] SDIx SDOx SCKx SSx Frame Sync Pulse(1)(2)(3) Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional). 3: Slave Select is not available when using Frame mode as a slave device. DS61143A-page 338 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 17.2.5 SPI MASTER MODE CLOCK FREQUENCY EQUATION 17-1: FSCK = SPI CLOCK FREQUENCY FPB 2 * (SPIxBRG+1) In Master mode, the SPI module clock source is the peripheral bus clock (PBCLK) and the SCK clock baud rate is derived from the PBCLK clock and the SPIxBRG register. Equation 17-1 defines the SCKx clock frequency as a function of the SPIxBRG register settings. Note that the maximum possible baud rate is FPB/2 (SPIXBRG = 0) and the minimum possible baud rate is FPB /1024. Sample SPI clock frequencies are shown in the table Table 17-6. . Note: The SCKx signal clock is not free running for nonframed SPI modes. It will only run for 8, 16 or 32 pulses when the SPIxBUF is loaded with data. It will however, be continuous for Framed modes. TABLE 17-6: FPB = 50 MHz FPB = 40 MHz FPB = 25 MHz FPB = 20 MHz FPB = 10 MHZ SAMPLE SCKX FREQUENCIES 0 25.00 MHz 20.00 MHz 12.50 MHz 10.00 MHz 5.00 MHz 15 1.56 MHz 1.25 MHz 781.25 KHz 625.00 KHz 312.50 KHz 31 781.25 KHz 625.00 KHz 390.63 KHz 312.50 KHz 156.25 KHz 63 390.63 KHz 312.50 KHz 195.31 KHz 156.25 KHz 78.13 KHz 85 290.7 KHz 232.56 KHz 145.35 KHz 116.28 KHz 58.14 KHz 127 195.31 KHz 156.25 KHz 97.66 KHz 78.13 KHz 39.06 KHz SPIxBRG setting (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 339 PIC32MX FAMILY 17.3 SPI Interrupts The SPI module has the ability to generate interrupts reflecting the events that occur during the data communication. The following types of interrupts can be generated: * Receive data available interrupts, signalled by SPI1RXIF (IFS0<25>), SPI2RXIF (IFS1<7>). This event occurs when there is new data assembled in the SPIxBUF receive buffer. * Transmit buffer empty interrupts, signalled by SPI1TXIF (IFS0<24>), SPI2TXIF (IFS1<6>). This event occurs when there is space available in the SPIxBUF transmit buffer and new data can be written. * Receive buffer overflow interrupts, signalled by SPI1EIF (IFS0<23>), SPI2EIF(IFS1<5>). This event occurs when there is an overflow condition for the SPIxBUF receive buffer, i.e., new receive data assembled but the previous one is not read. An SPI device is enabled as a source of interrupts via the respective SPI interrupt enable bits: * SPI1RXIE (IEC0<25>) and SPI2RXIE (IEC1<7>) * SPI1TXIE (IEC0<24>) and SPI2TXIE (IEC1<6>) * SPI1EIE (IEC0<23>) and SPI2EIE (IEC1<5>) The interrupt priority level bits and interrupt subpriority level bits must be also be configured: * SPI1IP (IPC5<28:26>), SPI1IS (IPC5<25:24>) * SPI2IP (IPC7<28:26>), SPI2IS (IPC7<25:24>) In addition to enabling the SPI interrupts, an Interrupt Service Routine, ISR, is required. Example 17-3 is a partial code example of an ISR. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. EXAMPLE 17-3: /* SPI INITIALIZATION WITH INTERRUPTS ENABLED The following code example illustrates an SPI1 interrupt configuration. When the SPI1 interrupt is generated, the cpu will jump to the vector assigned to SPI1 interrupt. It assumes that none of the SPI1 input pins are shared with an analog input. If so, the AD1PCFG and corresponding TRIS registers have to be properly configured. */ int rData; IEC0CLR=0x03800000; SPI1CON = 0; rData=SPI1BUF; IFS0CLR=0x03800000; IPC5CLR=0x1f000000; IPC5SET=0x0d000000; IEC0SET=0x03800000; SPI1BRG=0x1; SPI1STATCLR=0x40; SPI1CON=0x8220; // // // // // // // disable all SPI interrupts Stops and resets the SPI1. clears the receive buffer clear any existing event clear the priority Set IPL=3, subpriority 1 Enable Rx, Tx and Error interrupts // use FPB/4 clock frequency // clear the Overflow // SPI ON, 8 bits transfer, SMP=1, Master Mode DS61143A-page 340 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 17-4: /* The following code example demonstrates a simple interrupt service routine for SPI1 interrupts. The user's code at this vector should perform any application specific operations and must clear the SPI1 interrupt flags before exiting. */ void __ISR(_SPI1_VECTOR, IPL7) __SPI1Interrupt(void) { // ... perform application specific operations in response to the interrupt IFS0CLR = 0x03800000; } Note: The SPI1 ISR code example shows MPLAB(R) C32 C Compiler specific syntax. Refer to your compiler manual regarding support for ISRs. // Be sure to clear the SPI1 interrupt flags // before exiting the service routine. SPI1 ISR 17.4 I/O Pin Control Enabling the SPI modules will configure the I/O pin direction as defined by the SPI control bits (see Table 17-7). The port TRIS and LATCH registers will be overridden. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 341 PIC32MX FAMILY TABLE 17-7: I/O PIN CONFIGURATION FOR USE WITH SPI MODULES Required Settings for Module Pin Control IO Pin Name Required Module Control(3) ON and MSTEN ON and MSTEN ON ON ON and FRMEN and MSTEN ON and FRMEN and FRMSYNC ON and FRMEN and FRMSYNC Bit Field(3) -- TRIS(4) Pin Type Buffer Type Description SPI1, SPI2 module Clock Output in Master Mode. SPI1, SPI2 module Clock Input in Slave Mode. SPI1, SPI2 module Data Receive pin. SPI1, SPI2 module Data Transmit pin. SPI1, SPI2 module Slave Select Control pin. SCK1, SCK2 Yes X O CMOS SCK1, SCK2 SDI1, SDI2 SDO1, SDO2 Yes Yes Yes(1) -- -- DISSDO X(5) X(5) X I I O CMOS CMOS CMOS SS1, SS2 Yes(2) SSEN X(5) I CMOS SS1, SS2 Yes -- X(5) I CMOS SPI1, SPI2 Frame Sync Pulse input in Frame Mode. SS1, SS2 Yes -- X O CMOS SPI1,SPI2 Frame Sync Pulse output in Frame Mode. Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input withCMOS levels; I = Input; O = Output; X = Don't Care Note 1: The SDO pins are only required when SPI data output is needed. Otherwise, these pins can be used for general purpose I/O and require the user to set the corresponding TRIS control register bits. 2: The Slave Select pins are only required when a select signal to the slave device is needed. Otherwise, these pins can be used for general purpose I/O and require the user to set the corresponding TRIS control register bits. 3: These bits are contained in the SPIxCON register. 4: The setting of the TRIS bit is irrelevant. 5: If the input pin is shared with an analog input, then the AD1PCFG and the corresponding TRIS register have to be properly set to configure this input as digital. DS61143A-page 342 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 18.0 Note: INTER-INTEGRATED CIRCUIT (I2CTM) This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. 18.2 I2C Registers The I2CxCON register allows control of the module's operation. The I2CxCON register is readable and writable. I2CxSTAT register contains status flags indicating the module's state during operation. I2CxRCV is the receive register. When the incoming data is shifted completely, it is moved to the I2CxRCV register. I2CxTRN is the transmit register to which bytes are written during a transmit operation. The I2CxADD register holds the slave address. A Status bit, ADD10, indicates 10-Bit Addressing mode. The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV and an interrupt pulse is generated. The I2CxRSR shift register is not directly accessable to the programmer. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and MultiMaster modes of the I2C serial communication standard. Figure 18-1 shows the I2C module block diagram. The PIC32MX Family devices have up to two I2C interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module `I2Cx' (x = 1 or 2) offers the following key features: * I Interface Supporting both Master and Slave Operation. * I2C Slave Mode Supports 7 and 10-Bit Address. * I2C Master Mode Supports 7 and 10-Bit Address. * I2C Port allows Bidirectional Transfers between Master and Slaves. * Serial Clock Synchronization for I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control). * I2C Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly. * Provides Support for Address Bit Masking. 2C 18.3 I2C Interrupts The I2C module generates three interrupt signals: Slave Interrupt (I2CxSIF), Master Interrupt (I2CxMIF) and Bus Collision Interrupt (I2CxBIF). 18.4 Baud Rate Generator value for the Baud Rate Generator (BRG) resides in the I2CxBRG register. When the BRG is loaded with this value, the BRG counts down to `0' and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCLx pin is sampled high. As per the I2C standard, FSCL may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz. I2CxBRG values of `0' or `1' are illegal. In I2C Master mode, the reload 18.1 Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7 and 10-bit addressing. The I C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: * * I2C Slave Operation with 7 or 10-Bit Address I2C Master Operation with 7 or 10-Bit Address 2 EQUATION 18-1: I2CxBRG = SERIAL CLOCK RATE [ PBCLK FSCL x 2 ] -2 PBCLK is the peripheral clock speed. FSCL is the desired I2C bus speed. For details about the communication sequence in each of these modes, please refer to the "PIC32MX Family Reference Manual" (DS61132). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 343 PIC32MX FAMILY FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write I2CxCON Read Collision Detect Acknowledge Generation Clock Stretching Write I2CxTRN LSB Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter PBCLK DS61143A-page 344 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 18.5 I2C Module Addresses 18.8 General Call Address Support The I2CxADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CxCON<10>) is `0', the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 Least Significant bits of the I2CxADD register. If the A10M bit is `1', the address is assumed to be a 10-bit address. When the first address byte is received, it will be compared with the binary value, `11110 A9 A8 R/W = 0 (where A9 and A8 are Most Significant bits of the 10-bit address stored in I2CxADD). If that value matches, the next address byte will be compared with the Least Significant 8 bits of I2CxADD, as specified in the 10-bit addressing protocol. The general call address is used to address all devices. When this address is used, all devices should, in theory, respond with an Acknowledgement. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CxRCV to determine if the address was device-specific or a general call address. Upon detection of general call address, GCSTAT (I2CxSTAT<9>) bit is set. This method is available in both 7-Bit and 10-Bit Addressing modes. TABLE 18-1: 7-BIT I2CTM SLAVE ADDRESSES SUPPORTED BY PIC32MX FAMILY General call address or Start byte Reserved Hs mode Master codes Valid 7-bit addresses 10-bit address upper byte Reserved 18.9 Automatic Clock Stretch 0x00 0x01-0x03 0x04-0x07 0x08-0x77 0x78-0x7b 0x7c-0x7f In Slave modes, the module can synchronize buffer reads and writes to the master device by clock stretching. 18.9.1 TRANSMIT CLOCK STRETCHING Both 10-Bit and 7-Bit Transmit modes implement clock stretching by asserting the SCLREL bit after the falling edge of the ninth clock, if the TBF bit is cleared, indicating the buffer is empty. In Slave Transmit modes, clock stretching is always performed, irrespective of the STREN bit. The user's ISR must set the SCLREL bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the I2CxTRN before the master device can initiate another transmit sequence. 18.6 Slave Address Masking The I2CxMSK register (Register 18-4) designates address bit positions as "don't care" (= 1) for both 7-bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register, causes the slave module to respond, whether the corresponding address bit value is a `0' or `1'. For example, when I2CxMSK is set to `00110000', the slave module will detect both addresses, `0000000' and `00100000'. 18.9.2 RECEIVE CLOCK STRETCHING 18.7 Strict Addressing Support The STREN bit in the I2CxCON register can be used to enable clock stretching in Slave Receive mode. When the STREN bit is set, the SCLx pin will be held low at the end of each data receive sequence. The user's ISR must set the SCLREL bit before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the I2CxRCV before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring. The control bit, STRICT, enables the module to support the strict addressing. It enables the module to enforce all reserved addresses if they fall within the reserved address table. If the user wants to enforce the reserved address space, the STRICT (I2CxCON<11>) bit must be set to `1'. Once the bit is set, the device will not acknowledge reserved addresses, regardless of the address mask settings. 18.10 Software Controlled Clock Stretching (STREN = 1) When the STREN bit is `1', the SCLREL bit may be cleared by software to allow software to control the clock stretching. If the STREN bit is `0', a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 345 PIC32MX FAMILY 18.11 Slope Control The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control if desired. It is necessary to disable the slew rate control for 1 MHz mode. 2 18.13 Multi-Master Communication, Bus Collision and Bus Arbitration Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx by letting SDAx float high while another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the I2C master events interrupt flag and reset the master portion of the I2C port to its Idle state. 18.12 Clock Arbitration Clock arbitration occurs when the master deasserts the SCLx pin (SCLx allowed to go high by external pull-up resistors) during any receive, transmit or Restart/Stop condition. When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of I2CxBRG and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device. FIGURE 18-2: TYPICAL I2CTM INTERCONNECTION BLOCK DIAGRAM VDD PIC32MX SCLX SDAX VDD 4.7 k (typical) SCL SDA 24LC256 DS61143A-page 346 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 18-2: Virtual Address 0000h 32-BIT REGISTER SUMMARY Name Bit 31/23/ 15/7 31:24 23:16 15:8 7:0 -- -- ON GCEN Bit 30/22/ 14/6 -- -- FRZ STREN Bit 29/21/ 13/5 -- -- SIDL ACKDT Bit 28/20/ 12/4 -- -- SCLREL ACKEN Bit 27/19/ 11/3 -- -- STRICT RCEN Bit 26/18/ 10/2 -- -- A10M PEN Bit 25/17/ 9/1 -- -- DISSLW RSEN Bit 24/16/ 8/0 -- -- SMEN SEN I2CxCON 0004 0008h 000Ch 0010h I2CxCONCLR 31:0 I2CxCONSET 31:0 I2CxCONINV 31:0 I2CxSTAT 31:24 23:16 15:8 7:0 -- -- ACKSTAT IWCOL Clears selected bits of I2CxCON, read yields undefined value Sets selected bits of I2CxCON, read yields undefined value Inverts selected bits of I2CxCON, read yields undefined value -- -- TRSTAT I2COV -- -- -- D/A -- -- -- P -- -- -- S -- -- BCL R/W -- -- GCSTAT RBF -- -- ADD10 TBF 0014h 0018h 001Ch 0020h I2CxSTATCLR 31:0 I2CxSTATSET 31:0 I2CxSTATINV 31:0 I2CxADD 31:24 23:16 15:8 7:0 -- -- -- Clears selected bits of I2CxSTAT, read yields undefined value Sets selected bits of I2CxSTAT, read yields undefined value Inverts selected bits of I2CxSTAT, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADD<9:8> ADD<7:0> Clears selected bits of I2CxADD, read yields undefined value Sets selected bits of I2CxADD, read yields undefined value Inverts selected bits of I2CxADD, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0024h 0028h 002Ch 0030h I2CxADDCLR 31:0 I2CxADDSET 31:0 I2CxADDINV I2CxMSK 31:0 31:24 23:16 15:8 7:0 MSK<9:8> MSK<7:0> Clears selected bits of I2CxMSK, read yields undefined value Sets selected bits of I2CxMSK, read yields undefined value Inverts selected bits of I2CxMSK, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0034h 0038h 003Ch 0040h I2CxMSKCLR 31:0 I2CxMSKSET 31:0 I2CxMSKINV I2CxBRG 31:0 31:24 23:16 15:8 7:0 I2CxBRG<11:8> I2CxBRG<7:0> Clears selected bits of I2CxBRG, read yields undefined value Sets selected bits of I2CxBRG, read yields undefined value Inverts selected bits of I2CxBRG, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0044h 0048h 004Ch 0050h I2CxBRGCLR 31:0 I2CxBRGSET 31:0 I2CxBRGINV I2CxTRN 31:0 31:24 23:16 15:8 7:0 I2CTXDATA Clears selected bits of I2CxTRN, read yields undefined value Sets selected bits of I2CxTRN, read yields undefined value Inverts selected bits of I2CxTRN, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0054h 0058h 005Ch 0060h I2CxTRNCLR 31:0 I2CxTRNSET 31:0 I2CxTRNINV I2CxRCV 31:0 31:24 23:16 15:8 7:0 I2CRXDATA (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 347 PIC32MX FAMILY REGISTER 18-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 STREN R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 FRZ R/W-0 I2CSIDL R/W-1 SCLREL R/W-0 STRICT R/W-0 A10M R/W-0 DISSLW U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXCON: I2CTM CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 SMEN bit 8 R/W-0 SEN bit 0 Unimplemented: Read as `0' ON: I2C Enable bit 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables I2C module; all I2C pins are controlled by PORT functions FRZ: Freeze in Debug Mode Control bit (read/write only in Debug mode; otherwise read as `0') 1 = Freeze module operation when in Debug mode 0 = Do not freeze module operation when in Debug mode I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SCLREL: SCL Release Control bit In I2C Slave mode only Module Reset and (ON = 0) sets SCLREL = 1 If STREN = 0: 1 = Release clock 0 = Force clock low (clock stretch) Note: Automatically cleared to `0' at beginning of slave transmission. bit 14 bit 13 bit 12 If STREN = 1: 1 = Release clock 0 = Holds clock low (clock stretch). User may program this bit to `0' to force a clock stretch at the next SCL low. Note: bit 11 Automatically cleared to `0' at beginning of slave transmission; automatically cleared to `0' at end of slave reception. STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device doesn't respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule not enabled DS61143A-page 348 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 18-1: bit 10 I2CXCON: I2CTM CONTROL REGISTER (CONTINUED) A10M: 10-bit Slave Address Flag bit 1 = I2CxADD is a 10-bit slave address 0 = I2CADD is a 7-bit slave address DISSLW: Slew Rate Control Disable bit 1 = Slew rate control disabled for Standard Speed mode (100 kHz); also disabled for 1 MHz mode 0 = Slew rate control enabled for High-Speed mode (400 kHz) SMEN: SMBus Input Levels Disable bit 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs GCEN: General Call Enable bit In I2C Slave mode only 1 = Enable interrupt when a general call address is received in I2CSR. Module is enabled for reception 0 = General call address disabled STREN: SCL Clock Stretch Enable bit In I2C Slave mode only; used in conjunction with SCLREL bit. 1 = Enable clock stretching 0 = Disable clock stretching ACKDT: Acknowledge Data bit In I2C Master mode only; applicable during master receive. Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = A NACK is sent 0 = ACK is sent ACKEN: Acknowledge Sequence Enable bit In I2C Master mode only; applicable during master receive 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit; cleared by module 0 = Acknowledge sequence idle RCEN: Receive Enable bit In I2C Master mode only. 1 = Enables Receive mode for I2C, automatically cleared by module at end of 8-bit receive data byte 0 = Receive sequence not in progress PEN: Stop Condition Enable bit In I2C Master mode only. 1 = Initiate Stop condition on SDA and SCL pins; cleared by module 0 = Stop condition idle RSEN: Restart Condition Enable bit In I2C Master mode only. 1 = Initiate Restart condition on SDA and SCL pins; cleared by module 0 = Restart condition idle SEN: Start Condition Enable bit In I2C Master mode only. 1 = Initiate Start condition on SDA and SCL pins; cleared by module 0 = Start condition idle bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 349 PIC32MX FAMILY REGISTER 18-2: U-0 -- bit 31 U-0 -- bit 23 R-0 ACKSTAT bit 15 R/W-0 IWCOL bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 I2COV R-0 D/A R/W-0 P R/W-0 S R-0 R/W R-0 RBF R-0 TBF bit 0 R-0 TRSTAT U-0 -- U-0 -- U-0 -- R/W-0 BCL R-0 GCSTAT U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXSTAT: I2C STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 ADD10 bit 8 Unimplemented: Read as `0' ACKSTAT: Acknowledge Status bit In both I2C Master and Slave modes; applicable to both transmit and receive. 1 = Acknowledge was not received 0 = Acknowledge was received TRSTAT: Transmit Status bit In I2C Master mode only; applicable to Master Transmit mode. 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit Cleared when the I2C module is disabled (ON = 0). 1 = A bus collision has been detected during a master operation 0 = No collision has been detected GCSTAT: General Call Status bit Cleared after Stop detection. 1 = General call address was received 0 = General call address was not received ADD10: 10-bit Address Status bit Cleared after Stop detection. 1 = 10-bit address was matched 0 = 10-bit address was not matched IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register collided because the I2C module is busy. Must be cleared in software. 0 = No collision bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 DS61143A-page 350 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 18-2: bit 6 I2CXSTAT: I2C STATUS REGISTER (CONTINUED) I2COV: I2C Receive Overflow Status bit 1 = A byte is received while the I2CxRCV register is still holding the previous byte. I2COV is a "don't care" in Transmit mode. Must be cleared in software. 0 = No overflow D/A: Data/Address bit Valid only for Slave mode operation. 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit Updated when Start, Reset or Stop detected; cleared when the I2C module is disabled (ON = 0). 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last S: Start bit Updated when Start, Reset or Stop detected; cleared when the I2C module is disabled (ON = 0). 1 = Indicates that a start (or restart) bit has been detected last 0 = Start bit was not detected last R/W: Read/Write Information bit Valid only for Slave mode operation. 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave RBF: Receive Buffer Full Status bit 1 = Receive complete; I2CxRCV is full 0 = Receive not complete; I2CxRCV is empty TBF: Transmit Buffer Full Status bit 1 = Transmit in progress; I2CxTRN is full (8-bits of data) 0 = Transmit complete; I2CxTRN is empty bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 351 PIC32MX FAMILY REGISTER 18-3: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-10 bit 9-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXADD: I2C SLAVE ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 ADD<9:8> ADD<7:0> Unimplemented: Read as `0' ADD<9:0>: I2C Slave Device Address bits Either Master or Slave mode. DS61143A-page 352 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 18-4: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-10 bit 9-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXMSK: I2C ADDRESS MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 MSK<9:8> MSK<7:0> Unimplemented: Read as `0' MSK<9:0>: I2C Address Mask bits 1 = Forces a "don't care" in the particular bit position on the incoming address match sequence 0 = Address bit position must match the incoming I2C address match sequence MSK<9:8> and MSK<0> are only used in I2C 10-Bit mode. Note: (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 353 PIC32MX FAMILY REGISTER 18-5: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-12 bit 11-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXBRG: I2C BAUD RATE GENERATOR REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 I2CxBRG<11:8> I2CxBRG<7:0> Unimplemented: Read as `0' I2CxBRG<11:0>: I2C Baud Rate Generator Value bits A divider function of the Peripheral Clock. DS61143A-page 354 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 18-6: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXTRN: I2C TRANSMIT DATA REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 I2CTXDATA<7:0> Unimplemented: Read as `0' I2CTXDATA<7:0>: I2C Transmit Data Buffer bits (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 355 PIC32MX FAMILY REGISTER 18-7: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- I2CXRCV: I2C RECEIVE DATA REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 I2CRXDATA<7:0> Unimplemented: Read as `0' I2CRXDATA<7:0>: I2C Receive Data Buffer bits DS61143A-page 356 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, odd or no parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 47.7 bps to 3.125 Mbps at 50 MHz 4-level-deep First-In-First-Out (FIFO) Transmit Data Buffer 4-level-deep FIFO Receive Data Buffer Parity, framing and buffer overrun error detection Support for interrupt only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support Note: The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in PIC32MX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols such as RS-232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes the IrDA encoder and decoder. * LIN 1.2 protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 shows a simplified block diagram of the UART. FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) BCLKx Hardware Flow Control UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 357 PIC32MX 19.1 UART Registers UART1 SFR SUMMARY Name U1MODE 31:24 23:16 15:8 7:0 BF80_6004 U1MODECLR BF80_6008 U1MODESET BF80_600C U1MODEINV BF80_6010 U1STA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_6014 BF80_6018 BF80_601C BF80_6020 U1STACLR U1STASET U1STAINV U1TXREG 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_6030 U1RXREG 31:24 23:16 15:8 7:0 BF80_6040 U1BRG 31:24 23:16 15:8 7:0 BF80_6044 BF80_6048 BF80_604C U1BRGCLR U1BRGSET U1BRGINV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTXISEL<1:0> URXISEL<1:0> TXINV ADDEN -- -- Bit 31/23/15/7 -- -- ON WAKE Bit 30/22/14/6 -- -- FRZ LPBACK Bit 29/21/13/5 -- -- SIDL ABAUD Bit 28/20/12/4 -- -- IREN RXINV Bit 27/19/11/3 -- -- RTSMD BRGH Bit 26/18/10/2 -- -- -- PDSEL<2:0> Bit 25/17/9/1 -- -- UEN<1:0> STSEL Bit 24/16/8/0 -- -- TABLE 19-1: Virtual Address BF80_6000 Write clears selected bits in U1MODE, read yields undefined value Write sets selected bits in U1MODE, read yields undefined value Write inverts selected bits in U1MODE, read yields undefined value -- -- RXEN RIDLE -- TXBRK PERR -- TXEN FERR -- UTXBF OERR ADM_EN TRMT RXDA ADDR<7:0> Write clears selected bits in U1STA, read yields undefined value Write sets selected bits in U1STA, read yields undefined value Write inverts selected bits in U1STA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- BRG<7:0> Write clears selected bits in U1BRG, read yields undefined value Write sets selected bits in U1BRG, read yields undefined value Write inverts selected bits in U1BRG, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX8 -- -- RX8 -- -- Transmit Register Receive Register BRG<15:8> TABLE 19-2: Virtual Address BF88_1060 BF88_1030 BF88_10F0 UART1 INTERRUPT REGISTER SUMMARY Name IEC0 IFS0 IPC6 31:24 31:24 7:0 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 U1TXIE U1TXIF Bit 27/19/11/3 U1RXIE U1RXIF U1IP[2:0] Bit 26/18/10/2 U1EIE U1EIF Bit 25/17/9/1 -- -- U1IS[1:0] Bit 24/16/8/0 -- -- Note 1: This summary table contains partial register definitions that only pertain to the UART peripheral. Refer to the PIC32MX Family Reference Manual for a detailed description of these registers. DS61143-page 358 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX TABLE 19-3: Virtual Address BF80_6200 UART2 SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- ON WAKE Bit 30/22/14/6 -- -- FRZ LPBACK Bit 29/21/13/5 -- -- SIDL ABAUD Bit 28/20/12/4 -- -- IREN RXINV Bit 27/19/11/3 -- -- RTSMD BRGH Bit 26/18/10/2 -- -- -- PDSEL<2:0> Bit 25/17/9/1 -- -- UEN<1:0> STSEL Bit 24/16/8/0 -- -- U2MODE BF80_6204 U2MODECLR BF80_6208 U2MODESET BF80_620C U2MODEINV BF80_6210 U2STA 31:0 31:0 31:0 31:24 23:16 15:8 7:0 UTXISEL<1:0> URXISEL<1:0> -- -- Write clears selected bits in U2MODE, read yields undefined value Write sets selected bits in U2MODE, read yields undefined value Write inverts selected bits in U2MODE, read yields undefined value -- TXINV ADDEN -- RXEN RIDLE -- TXBRK PERR -- TXEN FERR -- UTXBF OERR ADM_EN TRMT RXDA ADDR<7:0> BF80_6214 BF80_6218 BF80_621C BF80_6220 U2STACLR U2STASET U2STAINV U2TXREG 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Write clears selected bits in U2STA, read yields undefined value Write sets selected bits in U2STA, read yields undefined value Write inverts selected bits in U2STA, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRG<7:0> Write clears selected bits in U2BRG, read yields undefined value Write sets selected bits in U2BRG, read yields undefined value Write inverts selected bits in U2BRG, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX8 -- -- RX8 -- -- Transmit Register BF80_6230 U2RXREG 31:24 23:16 15:8 7:0 Receive Register BF80_6240 U2BRG 31:24 23:16 15:8 7:0 BRG<15:8> BF80_6244 BF80_6248 BF80_624C U2BRGCLR U2BRGSET U2BRGINV 31:0 31:0 31:0 TABLE 19-4: Virtual Address 0xBF881070 0xBF881040 0xBF881110 UART2 INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC8 15:8 15:8 7:0 Bit 31/23/15/7 -- -- -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- Bit 27/19/11/3 -- -- U2IP<2:0> Bit 26/18/10/2 U2TXIE U2TXIF Bit 25/17/9/1 U2RXIE U2RXIF Bit 24/16/8/0 U2EIE U2EIF U2IS<1:0> (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 359 PIC32MX REGISTER 19-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 WAKE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 LPBACK R/W-0 ABAUD R/W-0 RXINV R/W-0 BRGH R/W-0 R/W-0 R/W-0 FRZ R/W-0 SIDL R/W-0 IREN R/W-0 RTSMD R/W-0 -- R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- UxMODE: UARTx MODE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 STSEL bit 0 UEN<1:0> PDSEL<1:0> Unimplemented: Read as `0' ON: UARTx Enable bit 1 = UARTx is enabled; UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits 0 = UARTx is disabled, all UARTx pins are controlled by corresponding PORT TRIS and LAT bits; UARTx power consumption is minimal 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode Note: FRZ: Freeze in Debug Exception Mode bit. FRZ is writable in Debug Exception mode only, it is forced to `0' in normal mode. bit 14 bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters in Idle mode 0 = Continue operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in simplex mode 0 = UxRTS pin is in flow control mode Unimplemented: Read as `0 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX, and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS, and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by port latches WAKE: Enable Wake-up on Start bit Detect During Sleep mode bit 1 = Wake-up enabled 0 = Wake-up disabled bit 12 bit 11 bit 10 bit 9-8 bit 7 DS61143-page 360 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX REGISTER 19-1: bit 6 UxMODE: UARTx MODE REGISTER (CONTINUED) LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of SYNCH character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = UxRX idle state is `0' 0 = UxRX idle state is `1' BRGH: High Baud Rate Enable bit 1 = High speed mode - 4x baud clock enabled 0 = Standard speed mode - 16x baud clock enabled PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit bit 5 bit 4 bit 3 bit 2-1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 361 PIC32MX REGISTER 19-2: U-0 -- bit 31 R/W-0 bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-25 bit 24 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR R-0 RXDA bit 0 R/W-0 R/W-0 TXINV R/W-0 RXEN R/W-0 TXBRK R/W-0 TXEN R-0 TXBF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UxSTA: UARTx STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 ADM_EN bit 24 R/W-0 bit 16 R-1 TRMT bit 8 ADDR<7:0> UTXISEL<1:0> URXISEL<1:0> Unimplemented: Read as `0' ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect Mode is enabled 0 = Automatic Address Detect Mode is disabled ADDR<7:0>: Automatic Address Mask bits When ADM_EN bit is `1', this value defines the bits that are don't care when comparing incoming address reception UTXISEL<1:0>: Tx Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated when the Transmit buffer becomes empty 01 = Interrupt is generated when all characters are transmitted 00 = Interrupt is generated when the Transmit buffer contains at least one empty space TXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMOD<12>) is `0') 1 = UxTX idle state is `0' 0 = UxTX idle state is `1' If IrDA mode is enabled (i.e., IREN (UxMOD<12>) is `1') 1 = IrDA encoded UxTX idle state is `1' 0 = IrDA encoded UxTX idle state is `0' RXEN: Receiver Enable bit 1 = UARTx receiver is enabled, UxRX pin controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled, the UxRX pin is ignored by the UARTx module. UxRX pin controlled by PORT. TXBRK: Transmit Break bit 1 = Send BREAK on next transmission - Start bit followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = BREAK transmission is disabled or completed bit 23-16 bit 15-14 bit 13 bit 12 bit 11 DS61143-page 362 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX REGISTER 19-2: bit 10 UxSTA: UARTx STATUS REGISTER (CONTINUED) TXEN: Transmit Enable bit 1 = UARTx transmitter enabled, UxTX pin controlled by UARTx (if ON = 1) 0 = UARTx transmitter disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Interrupt flag bit is set when Receive Buffer is full (i.e., has 4 data characters) 10 = Interrupt flag bit is set when Receive Buffer is 3/4 full (i.e., has 3 data characters) 0x = Interrupt flag bit is set when a character is received ADDEN: Address Character Detect (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this control bit has no effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing Error has been detected for the current character 0 = Framing Error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit will reset the receiver buffer and Receive Shift Register (RSR) to an empty state) RXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty bit 9 bit 8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 363 PIC32MX REGISTER 19-3: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 R-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-9 bit 8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 R-0 R-0 RX<7:0> bit 0 R-0 R-0 R-0 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- UxRXREG: UART RECEIVE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 RX8 bit 8 Unimplemented: Read as `0' RX8: Data bit 8 of the Received Character (in 9-bit mode) RX<7:0>: Data bits 7-0 of the Received Character DS61143-page 364 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX REGISTER 19-4: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-9 bit 8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) W-0 W-0 W-0 TX<7:0> bit 0 W-0 W-0 W-0 W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- UxTXREG: UARTx TRANSMIT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 W-0 TX8 bit 8 Unimplemented: Read as `0' TX8: Data bit 8 of the Character to be Transmitted (in 9-bit mode) TX<7:0>: Data bits 7-0 of the Character to be Transmitted (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 365 PIC32MX 19.2 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The BRGx register controls the period of a free-running 16-bit timer. Equation 19-1 shows the formula for computation of the baud rate with BRGH = 0. Equation 19-2 shows the formula for computation of the baud rate with BRGH = 1. EQUATION 19-2: UART BAUD RATE WITH BRGH = 1(1) FPB 4 * (UxBRG + 1) -1 Baud Rate = EQUATION 19-1: UART BAUD RATE WITH BRGH = 0(1) UxBRG = FPB Baud Rate = 16 * (UxBRG + 1) UxBRG = FPB -1 16 * Baud Rate FPB 4 * Baud Rate Note 1: FPB denotes the instruction cycle clock frequency. Note 1: FPB denotes the peripheral bus clock frequency. Example 19-1 shows the calculation of the baud rate error for the following conditions: * FPB = 4 MHz * Desired Baud Rate = 9600 The maximum possible baud rate with BRGH = 0 is FPB/16. The minimum possible baud rate is FPB/(16 * 65536). The maximum possible baud rate with BRGH = 1 is FPB/4 for UxBRG = 0, and the minimum possible baud rate is FPB/(4 * 65536). Writing a new value to the UxBRG register causes the baud rate counter to be cleared. This ensures that the BRG does not wait for a timer overflow before it generates the new baud rate. EXAMPLE 19-1: BAUD RATE ERROR CALCULATION (BRGH = 0) Desired Baud Rate = Fpb/(16 (UxBRG + 1)) Solving for UxBRG value: UxBRG = ( (Fpb/Desired Baud Rate)/16) - 1 UxBRG = ((4000000/9600)/16) - 1 UxBRG = [25.042] = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 = 0.16% DS61143-page 366 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 19.3 1. Transmitting in 8-Bit Data Mode 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write data byte to UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with next rising edge of the baud clock. Alternately, the data byte may be transferred while TXEN = 0, and then the user may set TXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISEL<1:0>. EXAMPLE 19-2: EXAMPLE 8-BIT DATA MODE /* The following code example demonstrates configuring UART1 for 8-bit Data Transmit mode. */ U1BRG = #BaudRate;// Set Uart baud rate. U1MODESET= 0x8000;// Enable Uart for 8-bit Data, no Parity, and 1 Stop bit U1STASET= 0x1400;// Enable Transmitter and Receiver 19.4 1. 2. 3. 4. 5. Transmitting in 9-Bit Data Mode 6. Set up the UART (as described in Section 19.3). Enable the UART. Set the TXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISEL<1:0>. EXAMPLE 19-3: EXAMPLE 9-BIT DATA MODE /* The following code example demonstrates configuring UART1 for 9-bit Data Transmit mode. */ U1BRG = #BaudRate;// Set Uart baud rate. U1MODESET= 0x8006;// Enable Uart for 8-bit Data, no Parity, and 1 Stop bit U1STASET= 0x1211420;// Enable Address Detect, Set Address = 0x21, Enable Transmitter and Receiver (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 367 PIC32MX 19.5 Auto-Baud Support 19.8 The UART will begin an automatic baud rate measurement sequence whenever a Start bit is received when the Auto-Baud Rate Detect is enabled (ABAUD = 1). This feature is active only while the auto-wake-up is disabled (WAKE = 0). In addition, LPBACK must equal `0' for the auto-baud operation. Following the Start bit, the auto-baud expects to receive an ASCII `U' (0x55) in order to calculate the proper bit rate. On the 5th UxRX pin rising edge, an accumulated BRG counter value totaling the proper BRG period is transferred to the UxBRG register. The ABAUD bit is automatically cleared. Operation of UxCTS and UxRTS Control Pins UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE register configure these pins. 19.9 Infrared Support 19.6 Break and Sync Transmit Sequence The UART module provides two types of infrared UART support: * IrDA clock output to support external IrDA encoder and decoder device (legacy module support) * Full implementation of the IrDA encoder and decoder The following sequence is performed to send a message frame header that is composed of a Break character, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master: 1. 2. 3. 4. Configure the UART for the desired mode. Set TXEN and TXBRK to set up the Break character. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write `0x55' to UxTXREG to load the Sync character into the transmit FIFO. 19.10 External IrDA Support - IrDA Clock Output To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN<1:0> = 11, the BCLKx pin will output the 16x baud clock (if the UART module is enabled). It can be used to support the IrDA codec chip. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. 19.7 1. 2. 3. Receiving in 8-Bit or 9-Bit Data Mode 19.11 Built-in IrDA Encoder and Decoder The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter. 4. 5. Set up the UART (as described in Section 19.3). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISEL<1:0>. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values. DS61143-page 368 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 19.12 UART Interrupts The UART device has the ability to generate interrupts, reflecting the events that occur during data communication. The following types of interrupts can be generated: * Receiver-data-available interrupts, signalled by U1RXIF (IFS0<27>), U2RXIF (IFS1<9>). This event occurs when there is new data assembled in the UxRXBUF receive buffer. * Transmitter-buffer-empty interrupts, signalled by U1TXIF (IFS0<28>), U2TXIF (IFS1<10>). This event occurs when there is space available in the UxTXBUF transmit buffer and new data can be written. * Receiver-buffer-overflow interrupt, signalled by U1EIF (IFS0<26>), U2EIF (IFS1<8>). This event occurs when there is an overflow condition for the UxRXBUF receive buffer, i.e., new receive data assembled but the previous one not read. A UART device is enabled as a source of interrupts via the respective UART interrupt enable bits: * U1RXIE (IEC0<27>) and U2RXIE (IEC1<9>) * U1TXIE (IEC0<28>) and U2TXIE (IEC1<10>) * U1EIE (IEC0<26>) and U2EIE (IEC1<8>) The interrupt priority level bits and interrupt subpriority level bits must be also be configured: * U1IP (IPC6<4:2>), U1IS (IPC6<1:0>) * U2IP (IPC8<4:2>), U2IS (IPC8<1:0>). In addition to enabling the UART interrupts, an Interrupt Service Routine (ISR) is required. Below is a partial code example of an ISR. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. EXAMPLE 19-4: /* UART INITIALIZATION WITH INTERRUPTS ENABLE The following code example illustrates a UART1 interrupt configuration. When the UART1 interrupt is generated, the cpu will jump to the vector assigned to UART1 interrupt. */ IEC0CLR=0x1c000000; IFS0CLR=0x1c000000; IPC6CLR=0x0000001f; IPC6SET=0x000d; IEC0SET=0x1c000000; U1BRG = #BaudRate; U1MODESET= 0x8000; U1STASET= 0x1400; // // // // // disable all UART1 interrupts clear any existing event clear the priority Set IPL=3, subpriority 1 Enable Rx, Tx and Error interrupts // Set Uart baud rate. // Enable Uart for 8-bit Data, no Parity, and 1 Stop bit // Enable Transmitter and Receiver EXAMPLE 19-5: /* UART1 ISR The following code example demonstrates a simple interrupt service routine for UART1 interrupts. The user's code at this vector should perform any application specific operations and must clear the UART1 interrupt flags before exiting. */ #pragma interupt Uart1IntHandler ipl4 vector 25 void Uart1IntHandler(void) { ... perform application specific operations in response to the interrupt IFS0CLR = 0x1c000000; } // Be sure to clear the UART1 interrupt flags // before exiting the service routine. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 369 PIC32MX 19.13 I/O Pin Control The UART module shares pins with port input/output control and, in some cases, with other modules. To configure a pin for use by the UART, any modules sharing the pin must be disabled. After configuring the UART, the corresponding I/O pins must be configured using the TRIS bit to be an input or output as is required by the UART. TABLE 19-5: Pin Name U1TX U2RX U1CTS U1RTS BCLK1 U2TX U2RX U2CTS U2RTS BCLK2 Legend: PINS ASSOCIATED WITH A UART Module Control(2) ON ON ON ON ON ON ON ON ON ON Controlling Bit Field UTXEN(3), UEN(2) URXEN(3), UEN(2) UEN(2) RTSMD(2), UEN(2) IREN(2) UTXEN(3), UEN(2) URXEN(3), UEN(2) UEN(2) RTSMD(2), UEN(2) IREN(2) Required TRIS bit Setting Output Input Input Output Output Output Input Input Output Output Pin Type(1) D, O D, I D, I D, O D, O D, O D, I D, I D, O D, O Description UART1 Transmit pin UART1 Receive pin UART1 Clear to Send (CTS) Duplex mode UART1 Ready to Send (RTS) Duplex mode UART1 IRDA baud clock output UART2 Transmit pin UART2 Receive pin UART2 Clear to Send (CTS) Duplex mode UART2 Ready to Send (RTS) Duplex mode UART2 IRDA baud clock output ST = Schmitt Trigger input with CMOS levels O = Output Note 1: 2: 3: A = Analog I = Input D = Digital All pins are subject to the Device Pin Priority Control. Bits are contained in the UxMODE register. Bits are contained in the UxSTA register DS61143-page 370 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.0 Note: PARALLEL MASTER PORT This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. * * * * The Parallel Master Port (PMP) is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices, and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. Key features of the PMP module include: * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two chip select lines Programmable strobe options - Individual read and write strobes, or - Read/write strobe with enable strobe * * * * Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: On 64-pin devices, data pins PMD<15:8> are not available. FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Control Lines PIC32MX Parallel Master Port PMA0 PMALL PMA1 PMALH Up to 16-Bit Address PMA<13:2> PMA14 PMCS1 PMA15 PMCS2 FLASH EEPROM SRAM PMRD PMRD/PMWR PMWR PMENB Microcontroller LCD FIFO buffer PMD<7:0> PMD<15:8>(1) 16/8-Bit Data (with or without multiplexed addressing) Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-Bit Master modes (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 371 PIC32MX FAMILY 20.1 PMP Registers PMP SFR SUMMARY Name PMCON 31:24 23:16 15:8 7:0 BF80_7004 BF80_7008 BF80_700C BF80_7010 PMCONCLR PMCONSET PMCONINV PMMODE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7014 BF80_7018 BF80_701C BF80_7020 PMMODECLR PMMODESET PMMODEINV PMADDR 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7024 BF80_7028 BF80_702C BF80_7030 PMADDRCLR PMADDRSET PMADDRINV PMDOUT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7034 BF80_7038 BF80_703C BF80_7040 PMDOUTCLR PMDOUTSET PMDOUTINV PMDIN 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7044 BF80_7048 BF80_704C BF80_7050 PMDINCLR PMDINSET PMDININV PMAEN 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7054 BF80_7058 BF80_705C BF80_7060 PMAENCLR PMAENSET PMAENINV PMSTAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_7064 BF80_7068 BF80_706C PMSTATCLR PMSTATSET PMSTATINV 31:0 31:0 31:0 -- -- IBF OBE -- -- -- -- CS2EN/A15 -- -- BUSY WAITB<1:0> Bit 31/23/15/7 -- -- ON CSF<1:0> Bit 30/22/14/6 -- -- FRZ Bit 29/21/13/5 -- -- SIDL ALP Bit 28/20/12/4 -- -- CS2P Bit 27/19/11/3 -- -- CS1P Bit 26/18/10/2 -- -- PMPTTL -- Bit 25/17/9/1 -- -- PTWREN WRSP Bit 24/16/8/0 -- -- PTRDEN RDSP TABLE 20-1: Virtual Address BF80_7000 ADRMUX<1:0> Write clears selected bits in PMCON, read yields undefined value Write sets selected bits in PMCON, read yields undefined value Write inverts selected bits in PMCON, read yields undefined value -- -- IRQM<1:0> -- -- -- -- -- -- -- -- MODE16 -- -- -- -- INCM<1:0> WAITM<3:0> MODE<1:0> WAITE<1:0> Write clears selected bits in PMMODE, read yields undefined value Write sets selected bits in PMMODE, read yields undefined value Write inverts selected bits in PMMODE, read yields undefined value -- -- CS1EN/A14 ADDR<7:0> Write clears selected bits in PRx, read yields undefined value Write sets selected bits in PRx, read yields undefined value Write inverts selected bits in PRx, read yields undefined value DATAOUT<31:24> DATAOUT<23:16> DATAOUT<15:8> DATAOUT<7:0> Write clears selected bits in PMDOUT, read yields undefined value Write sets selected bits in PMDOUT, read yields undefined value Write inverts selected bits in PMDOUT, read yields undefined value DATAIN<31:24> DATAIN<23:16> DATAIN<15:8> DATAIN<7:0> Write clears selected bits in PMDIN, read yields undefined value Write sets selected bits in PMDIN, read yields undefined value Write inverts selected bits in PMDIN, read yields undefined value -- -- -- -- -- -- PTEN<15:8> PTEN<7:0> Write clears selected bits in PMAEN, read yields undefined value Write sets selected bits in PMAEN, read yields undefined value Write inverts selected bits in PMAEN, read yields undefined value -- -- IBOV OBUF -- -- -- -- -- -- -- -- -- -- IB3F OB3E -- -- IB2F OB2E -- -- IB1F OB1E -- -- IB0F OB0E -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADDR<13:8> Write clears selected bits in PMSTAT, read yields undefined value Write sets selected bits in PMSTAT, read yields undefined value Write inverts selected bits in PMSTAT, read yields undefined value DS61143A -page 372 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 20-2: Virtual Address BF88_1040 BF88_1010 BF88_10D0 Note: PMP INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC7 7:0 7:0 7:0 Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 SPI2RXIE SPI2RXIF -- SPI2TXIE SPI2TXIF -- SPI2EIE SPI2EIF -- CMP2IE CMP2IF CMP1IE CMP1IF PMPIP<2:0> PMPIE PMPIF Bit 25/17/9/1 AD1IE AD1IF Bit 24/16/8/0 I2C1MIE I2C1MIF PMPIS<1:0> This summary table contains partial register definitions that only pertain to the PMP peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 373 PIC32MX FAMILY REGISTER 20-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 CSF1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) (1) PMCON: PARALLEL PORT CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 R/W-0 FRZ R/W-0 SIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 U-0 PMPTTL R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 CSF0(1) R/W-0 ALP(1) R/W-0 CS2P(1) R/W-0 CS1P(1) U-0 -- R/W-0 WRSP R/W-0 RDSP bit 0 Unimplemented: Read as `0' ON: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode SIDL: Stop in Idle Mode 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits 11 = All 16 bits of address are multiplexed on PMD<15:0> pins 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8> 00 = Address and data appear on separate pins PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled These bits have no effect when their corresponding pins are used as address lines bit 14 bit 13 bit 12-11 bit 10 bit 9 bit 8 Note 1: DS61143A -page 374 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 20-1: bit 7-6 PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) CSF<1:0>: Chip Select Function bits(1) 11 = Reserved 10 = PMCS2 and PMCS1 function as chip select 01 = PMCS2 functions as chip select, PMCS1 functions as address bit 14 00 = PMCS2 and PMCS1 function as address bits 15 and 14 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) CS2P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) CS1P: Chip Select 0 Polarity bit(1) 1 = Active-high (PMCS1/PMCS) 0 = Active-low (PMCS1/PMCS) Unimplemented: Read as `0' WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read Strobe active-high (PMWR) 0 = Read Strobe active-low (PMWR) For Master Mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master Mode 1 (PMMODE<9:8> = 11): 1 = Read/Write strobe active-high (PMRD/PMWR) 0 = Read/Write strobe active-low (PMRD/PMWR) These bits have no effect when their corresponding pins are used as address lines bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 375 PIC32MX FAMILY REGISTER 20-2: U-0 -- bit 31 U-0 -- bit 23 R-0 BUSY bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MODE16 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PMMODE: PARALLEL PORT MODE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 IRQM<1:0> INCM<1:0> MODE<1:0> WAITB1<1:0>(1) WAITM<3:0> WAITE1<1:0>(1) Unimplemented: Read as `0' BUSY: Busy bit (Master modes only) 1 = Port is busy 0 = Port is not busy IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved - do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only) 10 = Decrement ADDR<15:0> by 1 every read/write cycle(2) 01 = Increment ADDR<15:0> by 1 every read/write cycle(2) 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1= 16-bit mode: a read or write to the data register invokes a single 16-bit transfer(4) 0= 8-bit mode: a read or write to the data register invokes a single 8-bit transfer Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not subject to auto-increment/decrement. In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins PMD<7:0> are active when MODE16 = 0. On 64-pin devices, data pins PMD<15:8> are not available. bit 14-13 bit 12-11 bit 10 Note 1: 2: 3: 4: DS61143A -page 376 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 20-2: bit 9-8 PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) MODE1:MODE0: Parallel Port Mode Select bits 11 =Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA bit 7-6 bit 5-2 bit 3-0 Note 1: 2: 3: 4: Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not subject to auto-increment/decrement. In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins PMD<7:0> are active when MODE16 = 0. On 64-pin devices, data pins PMD<15:8> are not available. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 377 PIC32MX FAMILY REGISTER 20-3: U-0 -- bit 31 U-0 -- bit 23 R/W-0 CS2EN/A15 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS1EN/A14 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PMADDR: PARALLEL PORT ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 ADDR<13:8> ADDR<7:0> Unimplemented: Read as `0' CS2EN: Chip Select 2 bit 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive (pin functions as PMA<15>) CS1EN: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (pin functions as PMA<14>) ADDR13:ADDR0: Destination Address bits bit 14 bit 13-0 DS61143A -page 378 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 20-4: R/W-0 bit 31 R/W-0 bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDOUT: PARALLEL PORT DATAOUT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 DATAOUT<31:24> DATAOUT<23:16> DATAOUT<15:8> DATAOUT<7:0> DATAOUT<31:0>: Output Data Port bits for 8-bit write operations in Slave modes. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 379 PIC32MX FAMILY REGISTER 20-5: R/W-0 bit 31 R/W-0 bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDIN REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 DATAIN<31:24> DATAIN<23:16> DATAIN<15:8> DATAIN<7:0> DATAIN<31:0>: Input and Output Data Port bits for 8-bit or 16-bit read/write operations in Master modes; Input Data Port bits for read operations in Slave modes. DS61143A -page 380 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 20-6: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-14 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PMAEN: PARALLEL PORT PIN ENABLE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 PTEN<15:8> PTEN<7:0> Unimplemented: Read as `0' PTEN15:PTEN14: PMCSx Strobe Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1) 0 = PMA15 and PMA14 function as port I/O PTEN13:PTEN2: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads functions as port I/O The use of these pins as PMA15/PMA14 or CS2/CS1 are selected by bits CSF<1:0> in the PMCON register. The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits, ADRMUX<1:0>, in the PMCON register. bit 13-2 bit 1-0 Note 1: 2: (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 381 PIC32MX FAMILY REGISTER 20-7: U-0 -- bit 31 U-0 -- bit 23 R-0 IBF bit 15 R-1 OBE bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 OBUF U-0 -- U-0 -- R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0 R/W-0 IBOV U-0 -- U-0 -- R-0 IB3F R-0 IB2F R-0 IB1F U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODE ONLY) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 IB0F bit 8 Unimplemented: Read as `0' IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as `0' IB3F:IB0F: Input Buffer n Status Full bit 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as `0' OB3E:OB0E: Output Buffer n Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 DS61143A -page 382 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.2 20.2.1 Modes Of Operation CONSIDERATIONS 20.2.3 MASTER MODE SELECTION * The PMP module is enabled and ready when the ON bit (PMCON<15>) is set = 1, therefore it is recommended to configure the desired operating mode prior to enabling the module. * The PMP module is disabled and powered off when the ON bit (PMPCON<15>) = 0, thus providing maximum power savings. * It is recommended to wait for any pending read or write operation to be completed before enabling/disabling or re-configuring the module The two Master modes are selected using MODE<1:0> bits (PMCON<9:8>). Master Mode 1 is selected by configuring MODE<1:0> bits = 11; Master Mode 2 is selected by configuring MODE<1:0> bits = 10. 20.2.4 8, 16-BIT DATA MODES 20.2.2 CONSIDERATIONS FOR MASTER MODES The PMP in Master mode supports data widths 8 and 16 bits wide. By default, the data width is 8-bit, MODE16 (PMMODE<10>) bit = 0. To select 16-bit data width, set MODE16 = 1. When configured in 8-Bit Data mode, the upper 8 bits of the data bus, PMD<15:8>, are not controlled by the PMP module and are available as general purpose I/O pins. Note: On 64-pin devices, data pins PMD<15:8> are not available. * Setting address bits A15 and A14 = 1 when PMCS2 and PMCS1 are enabled as chip selects will cause both PMCS2 and PMCS1 to be active during a read or write operation. This may enable two devices simultaneously and should be avoided. * It is always recommended to poll the PMP's BUSY bit prior to any read or write operation to ensure the prior PMP operation has completed. The PMP module offers two Master modes of operation featuring 16-bit or 8-bit data (default), up to 16 bits of address, and all control signals to operate a variety of external parallel devices such as memory devices, peripherals, and slave microcontrollers. An example using Master Mode 2 is shown in Figure 20-2. 20.2.5 CHIP SELECTS Two chip select lines, PMCS1 and PMCS2, are available for the Master modes. The two chip select lines are multiplexed with the Most Significant bits of the address bus A14 and A15. If a pin is configured as a chip select, it is not included in any PMA<15:0> address auto-increment/decrement. It is possible to enable both PMCS2 and PMCS1 as chip selects, or enable only PMCS2 as a chip select, allowing PMCS1 to function strictly as address line A14. It is not possible to enable only PMCS1. The chip select signals are configured using the Chip Select Function bits CSF<1:0> (PMCON <7:6>). TABLE 20-3: CSF<1:0> 00 01 10 CHIP SELECT CONTROL FUNCTION PMCS2 = A15, PMCS1 = A14 PMCS2 = Enabled, PMCS1 = A14 PMCS2, PMCS1 = Enabled FIGURE 20-2: EXAMPLE PMP MASTER MODE 2, PARTIAL MULTIPLEXED INTERFACE PMA<13:8> PMD<7:0> PMD<15:8> PMA14/PMCS1 PMA15/PMCS2 PMA0/PMALL PMRD PIC32MX Refer to Section 20.2.16 "Addressing Considerations" for information regarding chip select address mapping. 20.2.6 PORT PIN CONTROL The PMAEN register controls the functionality of the address pins PMA<15:0>. Setting any PMAEN bit = 1 configures the corresponding PMA pin as an address line. Those bits set = 0 remain as general purpose I/O pins. Refer to Section 20.5 "I/O Pin Control" regarding I/O pin configuration. ADRMUX<1:0> = 01 PMWR Address Bus Multiplexed Data and Address Bus Data Bus Control Lines (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 383 PIC32MX FAMILY 20.2.7 READ/WRITE CONTROL The PMP module supports two distinct read/write signaling methods. In Master Mode 1, Read and Write strobe are combined into a single control line, PMRD/ PMWR; a second control line, PMENB, determines when a read or write action is to be taken. In Master Mode 2, Read and Write strobes (PMRD and PMWR) are supplied on separate pins. To enable the PMRD/PMWR and PMWR/PMENB pins, set PTRDEN bit (PMCON<8>) and PTWREN bit (PMCON<9>) = 1. If the Chip Select signals are disabled and configured as address bits, the bits will participate in the increment and decrement operations; otherwise, the PMCS2 and PMCS1 bit values will be unaffected. 20.2.10 WAIT STATES In Master modes, the user has control over the duration of the read, write, and address cycles by configuring the module Wait states. Three portions of the cycle, the beginning, middle, and end are configured using the corresponding WAITB, WAITM, and WAITE bits in the PMMODE register. 20.2.8 CONTROL LINE POLARITY 20.2.11 ADDRESS MULTIPLEXING All control signals (PMRD, PMWR, PMALL, PMALH, PMCS2 and PMCS1) can be individually configured for either positive (active-high) or negative (active-low) polarity. The polarity for each control line is controlled by separate bits in the PMCON register. TABLE 20-4: MASTER MODE PIN POLARITY In either of the Master modes the address bus can be multiplexed together with the data bus. There are three Address Multiplexing modes available; Demultiplexed, Partial Multiplexed and Full Multiplexed. The Addressing Multiplex mode is configured using bits ADRMUX<1:0> (PMCON<12:11). For detailed examples illustrating address multiplexing configurations, refer to the PMP chapter in the "PIC32MX Family Reference Manual" (DS61132). CONTROL PMCON Active-High Active-Low PIN Control Bit Select Select PMRD PMWR PMCS2 PMCS1 PMALL/H RDSP WRSP CS2P CS1P ALP 1 1 1 1 1 0 0 0 0 0 TABLE 20-6: ADRMUX<1:0> 00 01 10 11 Note: ADDRESS MULTIPLEX CONFIGURATIONS Multiplex Modes Demultiplexed Partial (uses PMD<7:0>) Full (uses PMD<7:0>) Full (uses PMD<15:0>) Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used. 20.2.9 AUTO-INCREMENT/DECREMENT While the module is operating in a Master mode, the auto-address increment/decrement bits INCM<1:0> (PMMODE<12:11>) control the behavior of the address value that appears on the PMA<15:0> address pins. The address can be made to automatically increment or decrement after each read and write operation, once each operation is completed, and the BUSY bit goes to `0'. A design implementing partial or full multiplexed address and data bus allows the unused PMA address pins to be used as general purpose I/O pins. However, depending on the Multiplexing mode, read and write operations will be extended by several peripheral bus clock cycles, TPBCLK. 20.2.12 DEMULTIPLEXED MODE TABLE 20-5: ADDRESS AUTOINCREMENT/DECREMENT CONFIGURATION FUNCTION No Increment, No Decrement Increment every R/W Cycle Decrement every R/W Cycle INCM<1:0> 00 01 10 In Demultiplexed mode, address bits are presented on pins PMA<15:0>. Note, PMA15 is not available if PMCS2 is enabled and PMA14 is not available if PMCS1 is enabled. Data bits are presented on pins PMD<15:0> in 16-Bit Data mode; pins PMD<7:0> in 8Bit Data mode. Demultiplexed mode is selected by configuring bits ADRMUX<1:0> = 00. DS61143A -page 384 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 20-3: PIC32MX DEMULTIPLEXED ADDRESSING PMA<13:0> PMD<7:0> PMD<15:8> PMA14/PMCS1 PMA15/PMCS2 PMRD (1) 20.2.14 FULL MULTIPLEXED MODE (8-BIT DATA PINS) ADRMUX<1:0> = 00 PMWR Address Bus Data Bus Control Lines Note 1: PMA15 is not available if PMCS2 is enabled. PMA14 is not available if PMCS1 is enabled. In 8-Bit Full Multiplexed mode, the entire 16 bits of the address are multiplexed with the data pins on PMD<7:0>. The PMA<0> and PMA<1> pins are used to present Address Latch Low enable (PMALL) and Address Latch High enable PMALH strobes, respectively. Pins PMA<13:2> are not used as address pins and can be used as general purpose I/O pins. In the event address bits PMA15 or PMA14 are configured as chip selects, the corresponding address bits PMADDR<15> and PMADDR<14> are automatically forced = 0. Full 8-Bit Multiplexed mode is selected by configuring bits ADRMUX<1:0> (PMCON<12:11>) = 10. FIGURE 20-5: 20.2.13 PARTIAL MULTIPLEXED MODE PIC32MX FULL MULTIPLEXED ADDRESSING (8-BIT BUS) PMD<7:0> (1) In Partial Multiplexed mode, the lower eight address bits are multiplexed with data pins PMD<7:0>. The upper eight address bits are unaffected and are presented on PMA<15:8>. Note, PMA15 is not available if PMCS2 is enabled and PMA14 is not available if PMCS1 is enabled. The PMA<0> pin is used as an Address Latch, and presents the Address Latch Low enable strobe (PMALL). PMA<7:1> are available as general purpose I/O pins. Partial Multiplexed mode is selected by configuring bits ADRMUX<1:0> = 00. PMA14/PMCS1 PMA15/PMCS2 PMA0 / PMALL PMA1 / PMALH PMRD ADRMUX<1:0> = 10 PMWR FIGURE 20-4: PIC32MX PARTIAL MULTIPLEXED ADDRESSING PMA<13:8> PMD<7:0> PMD<15:8> PMA14/PMCS1 PMA15/PMCS2 PMA0 / PMALL PMRD (1) Fully Multiplexed Address/Data Bus Control Lines Note 1: PMA15 is not available if PMCS2 is enabled. PMA14 is not available if PMCS1 is enabled. 20.2.15 FULL MULTIPLEXED MODE (16-BIT DATA PINS) ADRMUX<1:0> = 01 PMWR Address Bus Multiplexed Address/Data Bus Data Bus Control Lines Note 1: PMA15 is not available if PMCS2 is enabled. PMA14 is not available if PMCS1 is enabled. In Full 16-Bit Multiplexed mode, the entire 16 bits of the address are multiplexed with the data pins on PMD<15:0>. Pins PMA<0> and PMA<1> provide Address Latch Low enable PMALL and Address Latch High enable PMALH strobes, respectively, and at the same time. Pins PMA<13:2> are not used as address pins and can be used as general purpose I/O pins. In the event address bits PMA15 or PMA14 are configured as chip selects, the corresponding address bits PMADDR<15> and PMADDR<14> are automatically forced = 0. Full 16-Bit Multiplexed mode is selected by configuring bits: ADRMUX<1:0>(PMCON<12:11>) = 11 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 385 PIC32MX FAMILY FIGURE 20-6: FULL MULTIPLEXED ADDRESSING (16-BIT BUS) PMD<7:0> PMD<15:8> PMA14/PMCS1 PMA15/PMCS2 PMA0 / PMALL PMA1 / PMALH PMRD ADRMUX<1:0> = 11 PMWR (1) PIC32MX When configured as chip selects, a 1 must be written into bit position 15 or 14 of the PMADDR register in order for PMCS2 or PMCS1 to become active during a read or write operation. Failing to write a 1 to PMCS2 or PMCS1 does not prevent address pins PMA<13:0> from being active as the specified address appears, however, no chip select signal will be active. Note: When using Auto-Increment Address mode, PMCS2 and PMCS1 do not participate and must be controlled by the user's software by writing to `1' to PMADDR<15:14> explicitly. Disabling one or both chip selects PMCS2 and PMCS1 makes these pins available as address lines A15 and A14. In Full Multiplexed mode, address bits PMADDR<15:0> are multiplexed with the data bus and in the event address bits PMA15 or PMA14 are configured as chip selects, the corresponding PMADDR<15:14> address bits are automatically forced = 0. Disabling one or both PMCS2 and PMCS1 makes these bits available as address bits PMADDR<15:14>. In any of the Master mode multplexing schemes, disabling both chip select pins PMCS2 and PMCS1 requires the user to provide chip select line control through some other I/O pin under software control. See Figure 20-7. Fully Multiplexed Address/Data Bus Control Lines Note 1: PMA15 is not available if PMCS2 is enabled. PMA14 is not available if PMCS1 is enabled. 20.2.16 ADDRESSING CONSIDERATIONS PMCS2 and PMCS1 chip select pins share functionality with address lines A15 and A14. It is possible to enable both PMCS2 and PMCS1 as chip selects, or enable only PMCS2 as a chip select, allowing PMCS1 to function strictly as address line A14. It is not possible to enable only PMCS1. FIGURE 20-7: PMP CHIP SELECT ADDRESS MAPPING (DEMULTIPLEXED AND PARTIAL MULTIPLEXED MODES) PMCS2, CS1 PMCS2, A14 1 Device Selected PMCS2 = 1 1 0 1 0 1 Device Selected IOpin = 1 1 0 1 A15, A14, IO-pin 1 1 1 0xFFFF Both Devices Selected (INVALID) Device 2 Selected PMCS2 = 1 1 1 0xC000 0x8000 Device 1 Selected PMCS1 = 1 0x4000 No Device Selected 0x0000 2 - Chip Selects 2 - 16K Address Ranges 1 - Chip Select 1 - 32K Address Range IO-pin = Software controlled CS 1 - 64K Address Range 0 0 0 1 No Device Selected 0 0 0 0 1 0 1 0 1 1 DS61143A -page 386 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.3 Master Mode Timing The PMP Master mode timing for control, address and data signals is dependent on the PBCLK peripheral bus clock speed, address/data multiplexing and number of Wait states, if any. Table 20-7 provides a summary of PMP read and write maximum sustainable speeds for each of its Address Multiplex modes. Note: During any Master mode read or write operation, the busy flag will always deassert 1 peripheral bus clock cycle (TPBCLK), before the end of the operation, including Wait states. TABLE 20-7: READ/WRITE SPEEDS, NO WAIT STATES ADRMUX PMP Operation (PBCLK cycles) Read Write 3 6 9 6 Speed(1) (MHz) Read 36.0 14.4 9.0 14.4 Write 24.0 12.0 8.0 12.0 Address/Data Multiplex Configuration Demultiplexed 00 2 Partial Multiplex 01 5 Full Multiplexed (8-bit data) 10 8 Full Multiplexed (16-bit data) 11 5 Note 1: Peripheral bus clock operating at 1:1 with SYSCLK (72MHz) 20.3.1 MASTER PORT CONFIGURATION * * * * The Master mode configuration is determined primarily by the interface requirements to the external device. Address multiplexing, control signal polarity, data width and Wait states typically dictate the specific configuration of the PMP master port. The following illustrates example settings for Master Mode 2 operation: * Select Master Mode 2 MODE<1:0> (PMMODE<9:8>) = 10. * Select 16-Bit Data mode MODE16 (PMMODE<10>) = 1. * Select partial multiplexed addressing ADRMUX<1:0> (PMCON<12:11>) = 01. * Select auto-address increment INCM<1:0> (PMMODE<12:11>) = 01. * Enable Interrupt Request mode IRQM<1:0> (PMMODE<14:13>) = 01. * Enable PMRD strobe PTRDEN (PMCON<8>) = 1. * Enable PMWR strobe PTWREN (PMCON<9>) = 1. * Enable PMCS2 and PMCS1 chip selects CSF (PMCON<7:6>) = 10. * Select PMRD "active-low" pin polarity RDSP (PMCON<0>) = 0. * Select PMWR "active-low" pin polarity WRSP (PMCON<1>) = 0. * Select PMCS2, PMCS1 "active-low" pin polarity - CS2P (PMCON<4>) = 0 and CS1P (PMCON<3>) = 0. Select 1 wait cycle for data setup WAITB<1:0>(PMMODE<7:6>) = 00. Select 2 wait cycles to extend PMRD/PMWR WAITM<3:0>(PMMODE<5:2>) = 01. Select 1 wait cycle for data hold WAITB<1:0>(PMMODE<1:0>) = 00. Enable upper 8 PMA<15:8> address pins PMAEN<15:8> = 1 (lower 8 can be used as general purpose I/O). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 387 PIC32MX FAMILY 20.3.2 MASTER PORT INITIALIZATION 4. The Master mode initialization properly prepares the PMP port for communicating with an external device. The following steps should be performed to properly configure the PMP port: 1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit PMPIE (IEC1<2>) = 0. Stop and reset the PMP module by clearing the control bit ON (PMCON<15>) = 0. Configure the desired settings in the PMCON, PMMODE and PMAEN control registers. If interrupts are used: a) Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b) Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt sub priority bits PMPIS (IPC7<1:0>. c) Enable PMP interrupt by setting interrupt enable bit PMPIE = 1. Enable the PMP master port by setting control bit ON = 1. 2. 3. 5. EXAMPLE 20-1: IEC1CLR = 0x0004; PMCON = 0x0BC0; PMMODE = 0x2A04; PMAEN = 0xFF00; IPC7SET = 0x001C; IPC7SET = 0x0003; PARALLEL MASTER PORT INITIALIZATION //Disable PMP int //Stop and Configure //Config PMMODE reg //Config PMAEN reg //Priority level=7 //subpriority=3 //Same as.. //IPC7SET=0x001F //Clear PMP flag //Enable PMP int //Enable PMP //Set external address //Write to device IFS1CLR IEC1SET = 0x0004; = 0x0004; PMCONSET = 0x8000; PMADDR = 0x4000; PMDIN = 0x1234; ... 20.3.3 READ OPERATION To perform a read on the parallel bus, the user reads the PMDIN register. The effect of reading the PMDIN register retrieves the current value and causes the PMP to activate the chip select lines and the address bus. The read line PMRD is strobed and the new data is latched into the PMDIN register, making it available for the next time the PMDIN register is read. Note: The read data obtained from the PMDIN register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register. Also, the requested read value will not be ready until after the BUSY bit is observed low. Therefore, in a back-to-back read operation, the data read from the register will be the same for both reads. The next read of the register will yield the new value. Refer to the PIC32MX Family Reference Manual for a detailed description of the read operation and illustrated example. 20.3.4 WRITE OPERATION To perform a write onto the parallel port, the user writes to the PMDIN register (same register used for a read operation). This causes the module to first activate the chip select lines and the address bus. The write data from the PMDIN register is placed onto the PMD data bus and the write line PMPWR is strobed. DS61143A -page 388 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.3.5 PARALLEL MASTER PORT STATUS In addition to the PMP interrupt, a BUSY bit is provided to indicate the status of the module. This bit is only used in Master modes. While any read or write operation is in progress, the BUSY bit is set for all but the very last peripheral buscycle of the operation. While the bit is set, any request by the user to initiate a new operation will be ignored (i.e., writing or reading the PMDIN register will not initiate either a read nor a write). If a large number of wait-states are used, or if the PBCLK clock is operating slower than the SYSCLK clock, it is possible for the PMP module to be in the process of completing a read or write operation when the next CPU instruction is attempting to read or write the PMP module. For this reason, it is highly recommended that the PMP's BUSY bit be checked prior to any read or write operation and any user operation that modifies the PMADDR address register. See the following code example. EXAMPLE 20-2: POLLING THE BUSY FLAG /*An generic C example PMP write function utilizing the BUSY bit. */ pmpWrite(unsigned int value) { while(PMMODE & 0x8000); // PMP busy? PMDIN = value; // perform write } /*An MPLAB C32 example PMP write function utilizing BUSY bit. */ pmpWrite(unsigned int value) { while(PMMODEbits.BUSY); // PMP busy? PMDIN = value; // perform write } In most applications, the PMP's chip select pin(s) provide the chip select interface and are under the timing control of the PMP module. However, some applications may require the PMP chip select pin(s) not be configured as a chip select, but as a high-order address line, such as PMA<14> or PMA<15>. In this situation, the application's chip select function must be provided by an available I/O port pin under software control. In these cases, it is especially important that the user's software poll the BUSY bit to ensure any read or write operation is complete before de-asserting the software controlled chip select. The following example illustrates a common technique. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 389 PIC32MX FAMILY EXAMPLE 20-3: POLLING THE BUSY FLAG AND SOFTWARE CONTROLLED CHIP SELECT /* An generic C example PMP write function utilizing PORTD.RD1 as an active low chip select and the BUSY bit. */ pmpWrite(unsigned int value) { PORTDCLR = 0x0002; //CS enabled while(PMMODE & 0x8000); // PMP busy? PMDIN = value; //perform write while(PMMODE & 0x8000); //wait for PMP PORTDSET = 0x0002; //CS disabled } /* An MPLAB C32 example PMP write function utilizing PORTD.RD1 as an active low chip select and the BUSY bit. */ pmpWrite(unsigned int value) { PORTDCLR = 0x0002; //CS enabled while(PMMODEbits.BUSY); // PMP busy? PMDIN = value; // perform write while(PMMODEbits.BUSY); // wait for PMP PORTDSET = 0x0002; //CS disabled } DS61143A -page 390 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.3.6 20.3.6.1 SLAVE MODE Considerations for Slave Mode Figure 20-8: Master D<7:0> CS RD WR Legacy Slave Mode Interface PIC32MX Slave PMD<7:0> PMCS1 PMRD PMWR * Do not enable or disable the module during any read or write operation * Because of the asynchronous nature of the read and write operations, it is highly recommended that the user rely on the PSP status bits prior to any read or write operation. The PMP module provides 8-Bit (byte) legacy Parallel Slave Port functionality as well as new Buffered and Addressable Slave modes. 20.3.9 LEGACY SLAVE CONFIGURATION 20.3.7 MODE SELECTION The three Master modes are selected using MODE<1:0> bits (PMCON<9:8>). Legacy Slave mode is selected by configuring MODE<1:0> bits = 00; Buffered and Addressable Slave modes are selected by configuring MODE<1:0> = 01. Additionally, Buffered Slave mode requires bits INCM<1:0> (PMMODE<12:11>) = 11. The Legacy Slave mode configuration is determined automatically and dedicated to the PSP module when the Legacy Slave mode is selected. The user only need to configure the polarity of the PMCS1, PMRD and PMWR signals. The following example illustrates which control bits are to be set for Legacy Slave mode configuration: * Configure Legacy Slave mode bits MODE<1:0> (PMMODE<9:8>) = 00 * Select PMRD "active-low" pin polarity RDSP (PMCON<0>) = 0. * Select PMWR "active-low" pin polarity WRSP (PMCON<1>) = 0. * Select PMCS2, PMCS1 "active-low" pin polarity CS2P (PMCON<4>) = 0 and CS1P (PMCON<3>) = 0. TABLE 20-8: Slave Mode Legacy Buffered Addressable Slave Mode Selection PMCON MODE<1:0> 00 00 01 PMMODE INCM<1:0> x = don't care 11 x = don't care All Slave modes support 8-bit data only and the associated module control pins are automatically dedicated to the module when any of these modes are selected. The user only need to configure the polarity of the PMCS1, PMRD and PMWR signals. 20.3.10 SLAVE PORT INITIALIZATION The Legacy Slave mode initialization properly prepares the PMP port for communicating with an external master device. 1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit PMPIE (IEC1<2>) = 0. Stop and reset the PMP module by clearing the control bit ON (PMCON<15>) = 0. Configure the desired settings in the PMCON and PMMODE control registers. If interrupts are used: a) Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b) Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt sub priority bits PMPIS (IPC7<1:0>. c) Enable PMP interrupt by setting interrupt enable bit PMPIE = 1. Enable the PMP slave port by setting control bit ON = 1. TABLE 20-9: Slave Mode Pin Polarity Configuration 2. 3. 4. CONTROL PMCON Active-High Active-Low PIN Control Bit Select Select PMRD PMWR PMCS1 RDSP WRSP CS1P 1 1 1 0 0 0 20.3.8 LEGACY PARALLEL SLAVE MODE In Legacy Slave mode, an external device can asynchronously read and write data using the 8-bit data bus PMD<7:0>, the read PMRD, write PMWR, and chip-select PMCS1 inputs. 5. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 391 PIC32MX FAMILY EXAMPLE 20-4: IEC1CLR = 0x0004 PMCON = 0x0000 PMMODE = 0x0000 IPC7SET = 0x001C; IPC7SET = 0x0003; EXAMPLE CODE: LEGACY PARALLEL SLAVE PORT INITIALIZATION //Disable PMP int //Stop and Configure //Config PMMODE //Priority level=7 //subpriority =3 //Same as... //IPC7SET=0x001F //Clear PMP flag //Enable PMP int //Enable PMP IFS1CLR IEC1SET = 0x0004; = 0x0004; PMCONSET = 0x8000; DS61143A -page 392 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.3.11 Buffered Slave Mode Buffered Parallel Slave Port mode is functionally identical to the Legacy Parallel Slave Port mode with one exception: the implementation of 4-level read and write buffers. Buffered Slave mode is enabled by setting the PMMODE FIGURE 20-9: Master PARALLEL MASTER/SLAVE CONNECTION BUFFERED PIC32MX Slave PMD<7:0> D<7:0> CS RD WR PMCS1 PMRD PMWR Write Address Pointer PMDOUT (0) PMDOUT (1) PMDOUT (2) PMDOUT (3) Read Address Pointer PMDIN (0) PMDIN (1) PMDIN (2) PMDIN (3) 20.3.12 BUFFERED SLAVE CONFIGURATION 3. 4. The Buffered Slave mode configuration is determined automatically and dedicated to the PMP module when the Buffered Slave mode is selected. The user only need to configure the polarity of the PMCS1, PMRD and PMWR signals. The following example illustrates which control bits are to be set for Buffered Slave mode configuration: * Configure Buffered Slave mode bits MODE<1:0> (PMMODE<9:8>) = 00 and INCM<1:0> (PMMODE<12:11>) = 11. * Select PMRD "active-low" pin polarity RDSP (PMCON<0>) = 0. * Select PMWR "active-low" pin polarity WRSP (PMCON<1>) = 0. * Select PMCS2, PMCS1 "active-low" pin polarity CS2P (PMCON<4>) = 0 and CS1P (PMCON<3>) = 0. 5. control bit ON (PMCON<15>) = 0. Configure the desired settings in the PMCON and PMMODE control registers. If interrupts are used: a) Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b) Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt sub priority bits PMPIS (IPC7<1:0>. c) Enable PSP interrupt by setting interrupt enable bit PMPIE = 1. Enable the PMP slave port by setting control bit ON = 1. 20.3.13 BUFFERED SLAVE MODE INITIALIZATION The Buffered Slave mode initialization properly prepares the PSP port for communicating with an external master device. The following steps should be performed to properly configure the PSP port: 1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit PMPIE (IEC1<2>) = 0. Stop and reset the PMP module by clearing the 2. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 393 PIC32MX FAMILY EXAMPLE 20-5: IEC1CLR = 0x0004 PMCON = 0x0000 PMMODE = 0x1800 IPC7SET = 0x001C; IPC7SET = 0x0003; BUFFERED PARALLEL SLAVE MODE INITIALIZATION //Disable PMP //Stop and Configure //Configure PMMODE //Priority level=7 //subpriority=3 //Same as... //IPC7SET=0x001F //Clear PMP flag //Enable PMP int //Enable PMP IFS1CLR IEC1SET = 0x0004; = 0x0004; PMCONSET = 0x8000; 20.3.14 ADDRESSABLE SLAVE MODE In the Addressable Parallel Slave Port mode, the module is configured with two extra inputs, PMA<1:0>. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with Buffered Legacy mode, data is output from register PMDOUT and is input to register PMDIN. Table 20-1 shows the address resolution for the incoming address to the input and output registers. TABLE 20-10: SLAVE MODE BUFFER ADDRESSES PMA<1:0 > 00 01 10 11 Output Register PMDOUT(Buffer) <7:0> (0) <15:8> (1) <23:16> (2) <31:24> (3) Input Register PMDIN (Buffer) <7:0> (0) <15:8> (1) <23:16> (2) <31:24> (3) FIGURE 20-10: Master A<1:0> D<7:0> PARALLEL MASTER/SLAVE CONNECTION ADDRESSABLE BUFFER PMA<1:0> PMD<7:0> Write Address Decode PMDOUT (0) PIC32MX Slave Read Address Decode PMDIN (0) PMDIN (1) PMDIN (2) PMDIN (3) CS RD WR PMCS1 PMRD PMWR PMDOUT (1) PMDOUT (2) PMDOUT (3) 20.3.15 ADDRESSABLE SLAVE CONFIGURATION The Addressable Slave mode configuration is determined automatically and dedicated to the PSP module when the Addressable Slave mode is selected. The user only need to configure the polarity of the PMCS1, PMRD and PMWR signals. The following example illustrates which control bits are to be set for Addressable Slave mode configuration: * Configure Addressable Slave mode bits MODE<1:0> (PMMODE<9:8>) = 01. * Select PMRD "active-low" pin polarity RDSP (PMCON<0>) = 0. * Select PMWR "active-low" pin polarity WRSP (PMCON<1>) = 0. * Select PMCS2, PMCS1 "active-low" pin polarity CS2P (PMCON<4>) = 0 and CS1P (PMCON<3>) = 0. 20.3.16 ADDRESSABLE SLAVE PORT INITIALIZATION The Addressable Slave mode initialization properly prepares the PSP port for communicating with an external master device. The following steps should be performed to properly configure the PSP port: DS61143A -page 394 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit PMPIE (IEC1<2>) = 0. Stop and reset the PMP module by clearing the control bit ON (PMCON<15>) = 0. Configure the desired settings in the PMCON and PMMODE control registers. If interrupts are used: Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b) Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt sub priority bits PMPIS (IPC7<1:0>. c) Enable PSP interrupt by setting interrupt enable bit PMPIE = 1. Enable the PMP slave port by setting control bit ON = 1. a) 2. 3. 4. 5. EXAMPLE 20-6: ADDRESSABLE PARALLEL SLAVE PORT INITIALIZATION //Disable PMP int //Stop and Configure //Config PMMODE //Priority level=7 //subpriority=3 //Same as... //IPC7SET=0x001F //Clear PMP int flag //Enable PMP int //Enable PMP module IEC1CLR = 0x0004 PMCON = 0x0000 PMMODE = 0x0100 IPC7SET = 0x001C; IPC7SET = 0x0003; IFS1CLR = 0x0004; IEC1SET = 0x0004; PMCONSET = 0x8000; 20.4 PMP Interrupts The PMP module has the ability to generate the following types of interrupts reflecting the events that occur during data transfers. Master mode: * Interrupt on every read and write operation. Legacy Slave mode: * Interrupt on every read and write byte Buffered Slave mode: * Interrupt on every read and write byte * Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>) Addressable Slave mode: * Interrupt on every read and write byte * Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>), PMA<1:0> = 11 The PMP module is enabled as a source of interrupt using the PMP interrupt enable bit: * PMPIE (IEC1<2>). The interrupt priority level and subpriority level bits must also be configured: - PMPIP<2:0> (IPC7<4:2>) - PMPIS<1:0> (IPC7<1:0>) * The PMP interrupt status flag, PMPIF (IFS1<2>) is typically cleared by the user's software in the ISR. Below is a partial code example of an ISR. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 395 PIC32MX FAMILY EXAMPLE 20-7: /* The following code example illustrates a PMP interrupt configuration. When the PMP interrupt is generated, the CPU will branch to the vector assigned to PMP interrupt. */ // Configure PMP for desired mode of operation ... // Configure the PMP interrupts IPC7SET = 0x0014; // Set priority level=5 IPC7SET = 0x0003; // Set subpriority level=3 // Could have also done this in single // operation by assigning IPC7SET = 0x0017 IFS1CLR = 0x0002; IEC1SET = 0x0002; PMCONSET = 0x8000; // Clear the PMP interrupt status flag // Enable PMP interrupts // Enable PMP module PMP MODULE INTERRUPT INITIALIZATION EXAMPLE 20-8: /* PMP ISR The following code example demonstrates a simple interrupt service routine for PMP interrupts. The user's code at this vector should perform any application specific operations and must clear the PMP interrupt status flag before exiting. */ void _IRQ(_PMP_VECTOR, ipl3) PMP_Interrupt_ISR(void) { ... perform application specific operations in response to the interrupt IFS1CLR } = 0x00002; // Be sure to clear the PMP interrupt status // flag before exiting the service routine. DS61143A -page 396 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 20.5 20.5.1 I/O Pin Control I/O PIN RESOURCES TABLE 20-11: REQUIRED I/O PIN RESOURCES FOR MASTER MODES I/O Pin Name PMPCS2 / PMA15 PMPCS1 / PMA14 PMA<13:2> PMA1 / PMALH PMA0 / PMALL PMRD / PMWR PMWR / PMENB PMD<15:0> Demultiplex Yes(2) Yes Yes No (2) (2) Partial Multiplex Yes(2) Yes Yes Yes (2) (3) Full Multiplex Yes(2) Yes(2) No (1) Functional Description PMP Chip Select 2 / Address A15 PMP Chip Select 1 / Address A14 PMP Address A13..A2 PMP Address A1 / Address Latch High PMP Address A0 / Address Latch Low PMP Read / Write Control PMP Write / Enable Control PMP Bidirectional Data Bus D15..D0 No(1) (1) No(1) (2) Yes(4) Yes (4) Yes Yes Yes(5) Yes Yes Yes(5) Yes Yes Yes(5) Note 1: "No" indicates the pin is not required and is available as a general purpose I/O pin when the corresponding PMAEN bit is cleared, = 0. 2: Depending on the application, not all PMA<15:0> or CS2, CS1 may be required. 3: When Partial Multiplex mode is selected (ADDRMUX<1:0> = 01), the lower 8 Address lines are multiplexed with PMD<7:0>, PMA<0> becomes (PMALL) and PMA<7:1> are available as general purpose I/O pins. 4: When Full Multiplex mode is selected (ADDRMUX<1:0> = 10 or 11), all 16 Address lines are multiplexed with PMD<15:0>, PMA<0> becomes (PMALL), PMA<1> becomes (PMALH) and PMA<13:2> are available as general purpose I/O pins. 5: If MODE16 = 0, then only PMD<7:0> are required. PMD<15:8> are available as general purpose I/O pins. 6: Data pins PMD<15:0> are available on 100-pin PIC32MX devices and larger. For all other device variants, only pins PMD<7:0> are available. When enabling any of the PMP module for Slave mode operations, the PMPCS1, PMRD, PMWR control pins, PMD<7:0> data pins and PMA<1:0> address pins are automatically enabled and configured. The user is however responsible for selecting the appropriate polarity for these control lines. TABLE 20-12: REQUIRED I/O PIN RESOURCES FOR SLAVE MODES I/O Pin Name PMPCS1 / PMA14 PMA1 / PMALH PMA0 / PMALL PMRD / PMWR PMWR / PMENB PMD<7:0> Legacy Yes No (1) Buffered Yes No(1) No(1) Yes Yes Yes(2) Addressable Yes Yes Yes Yes Yes Yes(2) Functional Description Chip Select Address A1 Address A0 Read Control Write Control Bidirectional Data Bus D7..D0 No(1) Yes Yes Yes (2) Note 1: "No" indicates the pin is not required and is available as a general purpose I/O pin when the corresponding PMAEN bit is cleared, = 0. 2: Slave modes use PMD<7:0> only. Pins PMD<15:8> are available as general purpose I/O pins. Control bit MODE16 (PMMODE<10>) is ignored. 20.5.2 I/O PIN CONFIGURATION The following table provides a summary of settings required to enable the I/O pin resources used with this module. The PMAEN register controls the functionality of pins PMA<15:0>. Setting any PMAEN bit = 1 configures the corresponding PMA pin as an address line. Those bits set = 0 remain as general purpose I/O pins. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 397 PIC32MX FAMILY TABLE 20-13: I/O PIN CONFIGURATION Required Settings for Module Pin Control I/O Pin Name PMPCS2 / PMA15 PMPCS1 / PMA14 PMA<13:2> PMA1 / PMALH PMA0 / PMALL PMRD / PMWR PMWR / PMENB PMD<15:0> Required(1) Yes Yes Module Control ON ON Bit Field CSF<1:0>, CS2, PTEN15 CSF<1:0>, CS1 PTEN14 PTEN<13:2> PTEN<1> PTEN<0> PTRDEN PTWREN MODE16, ADRMUX<1:0> TRIS -- -- Pin Type O O Buffer Type(2) ST/TTL ST/TTL Description PMP Chip Select 2 / Address A15 PMP Chip Select 1 / Address A14 PMP Address A13 .. A2 PMP Address A1 / Address Latch Hi PMP Address A0 / Address Latch Lo PMP Read / Write Control PMP Write / Enable Control PMP Bidirectional Data Bus D15 .. D0 Yes Yes Yes Yes Yes Yes ON ON ON ON ON ON -- -- -- -- -- -- O I,O I,O O O I,O ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Legend: TTL = TTL compatible input or output, ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output Note 1: Depending on the PMP mode and the user's application, these pins may not be required. If not enabled, these pins can be used as general purpose I/O. 2: Default buffer type is ST. DS61143A -page 398 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The PIC32MX Real-Time Clock and Calendar (RTCC) module is intended for applications where accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. Following are some of the key features of this module: * * * * Time: Hours, Minutes and Seconds 24-Hour Format (Military Time) Visibility of One-Half-Second Period Provides Calendar: Weekday, Date, Month and Year * Alarm Intervals are configurable for Half a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year * Alarm Repeat with Decrementing Counter * Alarm with Indefinite Repeat: Chime * Year Range: 2000 to 2099 * Leap Year Correction * BCD Format for Smaller Firmware Overhead * Optimized for Long-Term Battery Operation * Fractional Second Synchronization * User Calibration of the Clock Crystal Frequency with Auto-Adjust * Calibration Range: 0.66 Seconds Error per Month * Calibrates up to 260 ppm of Crystal Error * Requirements: External 32.768 kHz Clock Crystal * Alarm Pulse or Seconds Clock Output on RTCC pin FIGURE 21-1: RTCC BLOCK DIAGRAM 32.768 kHz Input from SOSC Oscillator RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL YEAR, MTH, DAY WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks Repeat Counter ALRMVAL WKDAY HR, MIN, SEC RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin RTCOE (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 399 PIC32MX FAMILY 21.1 RTCC Registers RTCC SFR SUMMARY Name 31:24 23:16 15:8 7:0 BF80_0204 RTCCONCLR BF80_0208 RTCCONSET BF80_020C RTCCONINV BF80_0210 RTCALRM 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_0214 RTCALRMCLR BF80_0218 RTCALRMSET BF80_021C RTCALRMINV BF80_0220 RTCTIME 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_0224 RTCTIMECLR BF80_0228 RTCTIMESET BF80_022C RTCTIMEINV BF80_0230 RTCDATE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_0234 RTCDATECLR BF80_0238 RTCDATESET BF80_023C RTCDATEINV BF80_0240 ALRMTIME 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_0244 ALRMTIMCLR BF80_0248 ALRMTIMESET BF80_024C ALRMTIMEINV BF80_0250 ALRMDATE 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_0254 ALRMDATECLR BF80_0258 ALRMDATESET BF80_025C ALRMDATEINV 31:0 31:0 31:0 -- -- -- -- -- -- -- -- ALRMEN -- -- CHIME ON FRZ SIDL -- -- -- RTSECSEL RTCCLKON Bit 31/23/15/7 -- Bit 30/22/14/6 -- Bit 29/21/13/5 -- Bit 28/20/12/4 -- CAL<7:0> -- RTCWREN -- RTCSYNC -- HALFSEC -- RTCOE Bit 27/19/11/3 -- Bit 26/18/10/2 -- Bit 25/17/9/1 Bit 24/16/8/0 TABLE 21-1: Virtual Address BF80_0200 RTCCON CAL<9:8> Write clears selected bits in RTCCON, read yields undefined value Write sets selected bits in RTCCON, read yields undefined value Write inverts selected bits in RTCCON, read yields undefined value -- -- PIV -- -- ALRMSYNC ARPT<7:0> Write clears selected bits in RTCALRM, read yields undefined value Write sets selected bits in RTCALRM, read yields undefined value Write inverts selected bits in RTCALRM, read yields undefined value HR10<3:0> MIN10<3:0> SEC10<3:0> -- -- -- -- HR01<3:0> MIN01<3:0> SEC01<3:0> -- -- -- -- -- -- -- -- -- -- -- AMASK<3:0> Write clears selected bits in RTCTIME, read yields undefined value Write sets selected bits in RTCTIME, read yields undefined value Write inverts selected bits in RTCTIME, read yields undefined value YEAR10<3:0> MONTH10<3:0> DAY10<3:0> -- -- -- YEAR01<3:0> MONTH01<3:0> DAY01<3:0> WDAY01<3:0> Write clears selected bits in RTCDATE, read yields undefined value Write sets selected bits in RTCDATE, read yields undefined value Write inverts selected bits in RTCDATE, read yields undefined value HR10<3:0> MIN10<3:0> SEC10<3:0> -- -- -- -- HR01<3:0> MIN01<3:0> SEC01<3:0> -- -- -- Write clears selected bits in ALRMTIME, read yields undefined value Write sets selected bits in ALRMTIME, read yields undefined value Write inverts selected bits in ALRMTIME, read yields undefined value -- -- -- -- -- -- MONTH10<3:0> DAY10<3:0> -- -- -- MONTH01<3:0> DAY01<3:0> WDAY01<3:0> Write clears selected bits in ALRMDATE, read yields undefined value Write sets selected bits in ALRMDATE, read yields undefined value Write inverts selected bits in ALRMDATE, read yields undefined value TABLE 21-2: Virtual Address BF88_1070 BF88_1040 BF88_1110 RTCC INTERRUPT REGISTER SUMMARY Name IEC1 IFS1 IPC8 15:8 Bit 31/23/15/7 RTCCIE RTCCIF -- Bit 30/22/14/6 FSCMIE FSCMIF -- Bit 29/21/13/5 I2C2MIE I2C2MIF -- Bit 28/20/12/4 I2C2SIE I2C2SIF Bit 27/19/11/3 I2C2BIE I2C2BIF RTCCIP<2:0> Bit 26/18/10/2 U2TXIE U2TXIF Bit 25/17/9/1 U2RXIE U2RXIF Bit 24/16/8/0 U2EIE U2EIF 15:8 31:24 RTCCIS<1:0> Note: This summary table contains partial register definitions that only pertain to the RTCC peripheral. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of these registers. DS61143A-page 400 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 21-1: U-0 -- bit 31 R/W-0 bit 23 R/W-0 ON bit 15 R/W-0 RTSECSEL bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-26 bit 25-16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-0 RTCCLKON U-0 -- U-0 -- R/W-0 RTCWREN R-0 RTCSYNC R-0 HALFSEC R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CAL<7:0> bit 16 U-0 -- bit 8 R/W-0 RTCOE bit 0 R/W-0 R/W-0 R/W-0 RTCCON: RTC CONTROL REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 24 R/W-0 CAL<9:8> Unimplemented: Read as `0' CAL<9:0>: RTC Drift Calibration bits Contains a signed 10-bit integer value. 0111111111= Maximum positive adjustment, adds 511 RTC clock pulses every one minute ... 0000000001= Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000= No adjustment 1111111111= Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute ... 1000000000= Minimum negative adjustment, subtracts 512 clock pulses every one minute ON: RTCC On bit 1 = RTCC module is enabled 0 = RTCC module is disabled Note: The ON bit is only writable when RTCWREN = 1. FRZ: Freeze in Debug Mode bit 1 = When emulator is in Debug mode, module freezes operation 0 = When emulator is in Debug mode, module continues operation Note: The FRZ bit always reads `0' unless in Debug mode. SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin Note: Requires RTCOE == 1 (RTCCON<0>) for the output to be active. RTCCLKON: Status of the RTCC Clock Enable bit 1 = RTCC clock is actively running 0 = RTCC clock is not running bit 15 bit 14 bit 13 bit 12-8 bit 7 bit 6 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 401 PIC32MX FAMILY REGISTER 21-1: bit 5-4 bit 3 RTCCON: RTC CONTROL REGISTER(1) (CONTINUED) Unimplemented: Read as `0' RTCWREN: RTC Value Registers Write Enable bit 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user Note: The RTCWREN bit can be set only when the write sequence is enabled. The register can be written to a `0' at any time. RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading due to a roll over ripple that results in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTC Value registers can be read without concern about a roll over ripple HALFSEC: Half-Second Status bit 1 = Second half period of a second 0 = First half period of a second Note: This bit is read-only. It is cleared to `0' on a write to the SECONDS register. RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled - clock presented onto an I/O 0 = RTCC clock output disabled Note: This bit is ANDed with ON (RTCCON<15>) to produce the effective RTCC output enable. bit 2 bit 1 bit 0 Note 1: This register is only reset by Power-on Reset (POR). DS61143A-page 402 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 21-2: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ALRMEN bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHIME R/W-0 PIV R-0 ALRMSYNC R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- RTCALRM: RTC ALARM CONTROL REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 bit 8 R/W-0 bit 0 AMASK<3:0> ARPT<7:0> Unimplemented: Read as `0' ALRMEN: Alarm Enable bit 1 = Alarm is enabled 0 = Alarm is disabled Note: Hardware clears ALRMEN anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1. CHIME: Chime Enable bit 1 = Chime is enabled - ARPT<7:0> is allowed to roll over from 00 to FF 0 = Chime is disabled - ARPT<7:0> stops once it reaches 00 Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1. PIV: Alarm Pulse Initial Value bit When ALRMEN = 0, PIV is writable and determines the initial value of the alarm pulse. When ALRMEN = 1, PIV is read-only and returns the state of the alarm pulse. Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1. ALRMSYNC: Alarm Sync bit 1 = ARPT<7:0> and ALRMEN may change as a result of a half-second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain. 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because prescaler is > 32 RTC clock away from a half-second rollover Note: This assumes a CPU read will execute in less than 32 PBCLKs. bit 14 bit 13 bit 12 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 403 PIC32MX FAMILY REGISTER 21-2: bit 11-8 RTCALRM: RTC ALARM CONTROL REGISTER(1) (CONTINUED) AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 1010 = Reserved - do not use 1011 = Reserved - do not use 11XX = Reserved - do not use Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1. ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will trigger 256 times ... 00000000 = Alarm will trigger 1 time The counter decrements on any alarm event. The counter only rolls over from 00 to FF if CHIME = 1. Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1. bit 7-0 Note 1: This register is only reset by POR. DS61143A-page 404 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 21-3: R-0 bit 31 R-0 bit 23 R-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-28 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RTCTIME: RTC TIME VALUE REGISTER(1) R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> SEC10<3:0> SEC01<3:0> HR10<3:0>: Binary Coded Decimal Value of Hours bits 10 digits; contains a value from 0 to 2. Note: HR10<3:2> bits are always read `0'. HR01<3:0>: Binary Coded Decimal Value of Hours bits 1 digit; contains a value from 0 to 9. MIN10<3:0>: Binary Coded Decimal Value of Minutes bits 10 digits; contains a value from 0 to 5. Note: MIN10<3> bit is always read `0'. MIN01<3:0>: Binary Coded Decimal Value of Minutes bits 1 digit; contains a value from 0 to 9. SEC10<3:0>: Binary Coded Decimal Value of Seconds bits 10 digits; contains a value from 0 to 5. Note: SEC10<3> bit is always read `0'. SEC01<3:0>: Binary Coded Decimal Value of Seconds bits 1 digit; contains a value from 0 to 9. Unimplemented: Read as `0' bit 27-24 bit 23-20 bit 19-16 bit 15-12 bit 11-8 bit 7-0 Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 405 PIC32MX FAMILY REGISTER 21-4: R/W-x bit 31 R-0 bit 23 R-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-28 bit 27-24 bit 23-20 bit 19-16 bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- R-0 R/W-x R/W-x R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R-0 R-0 R/W-x R/W-x R/W-x R/W-x RTCDATE: RTC DATE VALUE REGISTER(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> DAY10<3:0> DAY01<3:0> WDAY01<3:0> YEAR10<3:0>: Binary Coded Decimal Value of Years bits (10 digits) YEAR01<3:0>: Binary Coded Decimal Value of Years bits (1 digit) MONTH10<3:0>: Binary Coded Decimal Value of Months bits (10 digits; contains a value from 0 to 1) Note: MONTH10<3:1> bits are always read `0'. MONTH01<3:0>: Binary Coded Decimal Value of Months bits (1 digit; contains a value from 0 to 9) DAY10<3:0>: Binary Coded Decimal Value of Days bits (10 digits; contains a value from 0 to 3) Note: DAY10<3:2> bits are always read `0'. DAY01<3:0>: Binary Coded Decimal Value of Days bits (1 digit; contains a value from 0 to 9) Unimplemented: Read as `0' WDAY01<3:0>: Binary Coded Decimal Value of Weekdays bits (1 digit; contains a value from 0 to 6) Note: WDAY01<3> bit is always read `0'. Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>). DS61143A-page 406 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 21-5: R-0 bit 31 R-0 bit 23 R-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-28 bit 27-24 bit 23-20 bit 19-16 bit 15-12 bit 11-8 bit 7-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ALRMTIME: ALARM TIME VALUE REGISTER R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 24 R/W-x bit 16 R/W-x bit 8 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> SEC10<3:0> SEC01<3:0> HR10<3:0>: Binary Coded Decimal Value of Hours bits (10 digit; contains a value from 0 to 2) Note: HR10<3:2> bits are always read `0'. HR01<3:0>: Binary Coded Decimal Value of Hours bits (1 digit; contains a value from 0 to 9) MIN10<3:0>: Binary Coded Decimal Value of Minutes bits, (10 digit; contains a value from 0 to 5) Note: MIN10<3> bit is always read `0'. MIN01<3:0>: Binary Coded Decimal Value of Minutes bits (1 digit; contains a value from 0 to 9) SEC10<3:0>: Binary Coded Decimal Value of Seconds bits (10 digit; contains a value from 0 to 5) Note: SEC10<3> bit is always read `0'. SEC01<3:0>: Binary Coded Decimal Value of Seconds bits (1 digit; contains a value from 0 to 9) Unimplemented: Read as `0' (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 407 PIC32MX FAMILY REGISTER 21-6: U-0 -- bit 31 R-0 bit 23 R-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-24 bit 23-20 bit 19-16 bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- R-0 R/W-x R/W-x R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R-0 R-0 R/W-x R/W-x R/W-x R/W-x ALRMDATE: ALARM DATE VALUE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 R/W-x bit 16 R/W-x bit 8 R/W-x bit 0 MONTH10<3:0> MONTH01<3:0> DAY10<3:0> DAY01<3:0> WDAY01<3:0> Unimplemented: Read as `0'. MONTH10<3:0>: Binary Coded Decimal Value of Months bits (10 digit; contains a value from 0 to 1) Note: MONTH10<3:1> bits are always read `0'. MONTH01<3:0>: Binary Coded Decimal Value of Months bits (1 digit; contains a value from 0 to 9) DAY10<3:0>: Binary Coded Decimal Value of Days bits (10 digit; contains a value from 0 to 3) Note: DAY10<3:2> bits are always read `0'. DAY01<3:0>: Binary Coded Decimal Value of Days bits (1 digit; contains a value from 0 to 9) Unimplemented: Read as `0' WDAY01<3:0>: Binary Coded Decimal Value of Weekdays bits (1 digit; contains a value from 0 to 6) Note: WDAY01<3> bit is always read `0'. DS61143A-page 408 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.2 Clock Calendar Mode The PIC32MX RTCC module provides clock and calendar functions with the following features: * 100-year clock and calendar with automatic leap year detection. * Clock range from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. * Clock granularity of one second with half-second visibility to the user. cial "unlock" sequence to be performed prior to writing to these registers. Additionally, the user should verify that the RTCSYNC bit (RTCCON<2>) = 0 (safe to access registers) for any read or write operations. Refer to Section 21.2.3 Example 21-3 "Write Lock" and 21.2.2 SAFETY WINDOW FOR REGISTER READS AND WRITES 21.2.1 RTCC CONFIGURATION The RTCTIME and RTCDATE registers can be programmed with the desired time and date numeric values expressed in Binary Coded Decimal (BCD) format. This simplifies users' firmware as each of the digit values is contained within its own 4-bit value (see Figure 21-2). The RTCTIME and RTCDATE registers can be safely accessed when the RTCC module is disabled (ON bit (RTCCON<15>) = 0). However, when the RTCC module is enabled (ON bit = 1), the module provides a single RTCSYNC bit (RTCCON<2>) that the user must use to determine when it is safe to read and update the time and date registers. The RTCSYNC bit indicates a time window during which the RTCC time registers (RTCTIME, RTCDATE ) are not about to be updated and can be safely read and written. For read or write operations, the registers can be safely accessed by the CPU when RTCSYNC = 0. For a read operation when RTSYNC = 1, the user must employ a firmware solution to assure that the data read did not fall on an update boundary, resulting in an invalid or partial read. For example, reading and comparing a Timer register value twice can ensure in code that the register read did not span an RTCC clock update. Write operations to the Time and Date registers should not be performed when RTCSYNC = 1. Refer to Example 21-1 and Example 21-2. FIGURE 21-2: YEAR TIMER DIGIT FORMAT MONTH DAY DAY OF WEEK 0-9 0-9 0-1 0-9 0-3 0-9 0-6 1/2 SECOND BIT (binary format) HOURS (24-hr format) MINUTES SECONDS 0-2 0-9 0-5 0-9 0-5 0-9 0/1 The user can configure the current time by simply writing the desired year, month, day, hour, minutes and seconds to the RTCTIME and RTCDATE registers. However, these registers are write-protected and require a speEXAMPLE 21-1: /* */ UPDATING THE RTCC TIME AND DATE The following code example will update the RTCC time and date. // assume the secondary oscillator is enabled and ready, i.e. // OSCCON<1>=1, OSCCON<22>=1, and RTCC write is enabled i.e. // RTCWREN (RTCCON<3>) =1; unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec unsigned long date=0x06102705;// set date to Friday 27 Oct 2006 RTCCONCLR=0x8000; while(RTCCON&0x40); RTCTIME=time; RTCDATE=date; RTCCONSET=0x8000; while(!(RTCCON&0x40)); // // // // // // turn off the RTCC wait for clock to be turned off safe to update the time update the date turn on the RTCC wait for clock to be turned on // can disable the RTCC write (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 409 PIC32MX FAMILY EXAMPLE 21-2: /* */ // assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1; unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec unsigned long date=0x06102705;// set date to Friday 27 Oct 2006 // disable interrupts, critical section follows __asm__ __volatile__ ("di"); while((RTCCON&0x4)!=0); // wait for not RTCSYNC RTCTIME=time; // safe to update the time RTCDATE=date; // update the date // restore interrupts, critical section ended __asm__ __volatile__ ("ei"); // can disable the RTCC write UPDATING THE RTCC TIME USING THE RTCSYNC WINDOW The following code example will update the RTCC time and date. 21.2.3 WRITE LOCK In order to perform a write to any of the RTCC Time registers, the RTCWREN bit (RTCCON<3>) must be set. Setting of the RTCWREN bit is only allowed once the device level unlocking sequence has been executed. The unlocking sequence is as follows: 1. Suspend or disable all initiators that can access the peripheral bus and interrupt the unlock sequence. (i.e., DMA and Interrupts). Store 0xAA996655 to the SYSKEY register. Store 0x556699AA to the SYSKEY register. 4. 5. 6. Set RTCWREN bit into the RTCCON register. Perform the device relock by writing a dummy value to the SYSKEY register. Re-enable DMA and interrupts. Note that steps 2 through 4 must be followed exactly to unlock RTCC write operations. If the sequence is not followed exactly, the RTCWREN bit will not be set. Refer to Example 21-3 for a "C" language implementation of the write unlock operation. 2. 3. EXAMPLE 21-3: WRITE UNLOCK SEQUENCE // assume interrupts are disabled // assume the DMA controller is suspended // assume the device is locked // starting critical sequence SYSKEY = 0xaa996655; // write first unlock key to SYSKEY SYSKEY = 0x556699aa; // write second unlock key to SYSKEY RTCCONSET = 0x8; // set RTCWREN in RTCCONSET // end critical sequence SYSKEY = 0x33333333; // perform device re-lock // can resume the DMA controller activity // can re-enable interrupts Note: To avoid accidental writes to the RTCC time values, it is recommended that the RTCWREN bit (RTCCON<3>) is kept clear at any other time. DS61143A-page 410 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.3 Alarm Mode FIGURE 21-4: Alarm Mask Setting AMASK<3:0> 0000 - Every half-second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year (1) ALARM MASK SETTINGS Day Hours Minutes Seconds The PIC32MX RTCC module provides alarm functions with the following features: * * * * One-time alarm Repeat alarms Indefinite alarm repetition Configurable from half-second to one year Day of the Week Month s s m m h d d m m d d d h h h h h h h m m m m m m m m m s s s s s s s s s s s s s The RTCC alarm generates an alarm event when the RTCC timer matches the masked alarm value. The RTCC alarm functions are configurable from a half-second to one year and can repeat the alarm at preconfigured intervals. The chime feature provides indefinite repetition of the alarm. To enable the alarm feature, configure the ALRMEN bit (RTCALRM<15>) = 1. To disble the alarm feature, configure the ALRMEN bit = 0. An alarm event is generated when the RTCC timer matches the masked alarm registers. Note 1: Once the timer value reaches the alarm setting, one RTCC clock period will elapse prior to setting the alarm interrupt. 2: IF RTCC is off (RTCCON<15> = 0) the writable fields in the RTCALRM register can be safely modified. If RTCC is ON, the write of the RTCALRM register has to be done while ALRMSYNC = 0. Not following the above steps can result in a false alarm event. 3: The same applies to the ALRMTIME and ALRMDATE registers: They can be safely modified only when ALRMSYNC = 0. Note 1: Annually, except when configured for February 29. 21.3.2 ONE-TIME ALARM A single, one-time alarm can be generated by configuring the Alarm Repeat Counter bits, ARPT (RTCALRM<7:0>) = 0, and the CHIME bit, (RTCALRM<14>) = 0. Once the alarm event occurs, the ALRMEN bit is automatically cleared in hardware, disabling future alarms. The user must re-enable this bit for any new alarm configuration. It is suggested to read and verify the Alarm Sync bit, ALRMSYNC (RTCALRM<12>) = 0, before performing the following configuration: * Disable Alarm - ALRMEN (RTCALRM<15>) = 0. * Disable Chime - CHIME (RTCALRM<14>) = 0. * Clear Alarm Repeat Counter - ARPT (RTCALRM<7:0>) = 0. The remaining bits are shown with example configurations and may be configured as desired: * Configure alarm date and time - Load ALRMDATE and ALRMTIME registers with the desired alarm date/time values. * Configure mask - Load the desired AMASK value. * Enable Alarm - ALRMEN (RTCALRM<15>) = 0. Refer to Example 21-4 21.3.1 ALARM CONFIGURATION The ALRMTIME and ALRMDATE registers can be programmed with the desired time and date numeric values expressed in Binary Coded Decimal (BCD) format. This simplifies users' firmware as each of the digit values is contained within its own 4-bit value (see Figure 21-3). FIGURE 21-3: ALARM DIGIT FORMAT MONTH DAY DAY OF WEEK 0-1 HOURS (24-hr format) 0-9 0-3 0-9 0-6 MINUTES SECONDS 0-2 0-9 0-5 0-9 0-5 0-9 The alarm interval selection is based on the settings of the alarm mask, AMASK (RTCALRM<11:8>). The AMASK bits determine which and how many digits of the alarm must match the RTCC clock value for the alarm event to occur (see Figure 21-4). (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 411 PIC32MX FAMILY EXAMPLE 21-4: /* */ CONFIGURING THE RTCC FOR A ONE-TIME ALARM The following code example will update the RTCC one-time alarm. Assumes the interrupts are disabled. unsigned long alTime=0x16153300;// set time to 04 hr, 15 min, 33 sec unsigned long alDate=0x06102705;// set date to Friday 27 Oct 2006 // turn off the alarm, chime and alarm repeats; clear // the alarm mask while(RTCALRM&0x1000); RTCALRMCLR=0xCFFF; ALRMTIME=alTime; ALRMDATE=alDate; RTCALRMSET=0x8000|0x00000600; // wait ALRMSYNC to be off // clear ALRMEN, CHIME, AMASK and ARPT; // update the alarm time and date // re-enable the alarm, set alarm mask at once per day 21.3.3 REPEAT ALARM A repeat alarm can be generated by configuring the Alarm Repeat Counter bits, ARPT (RTCALRM<7:0>) = 0x00 to 0xFF (0 to 255), and the CHIME bit (RTCALRM<14>) = 0. Once the the alarm is enabled and an alarm event occurs, the ARPT count is decremented by one. Once the register reaches 0, the alarm will be generated one last time; after which point, ALRMEN bit is cleared automatically and the alarm will turn off. The user must re-enable this bit for any new alarm configuration. Note: An alarm event is generated when ARPT bits are = 0x00. It is recommended to read and verify the Alarm Sync bit ALRMSYNC (RTCALRM<12>) = 0, before performing the following configuration steps: * Disable alarm - ALRMEN (RTCALRM<15>) = 0. * Disable chime - CHIME (RTCALRM<14>) = 0. * Configure alarm repeat counter - ARPT (RTCALRM<7:0>) = 0x00 to 0xFF. * Configure alarm date and time - Load ALRMDATE and ALRMTIME registers with the desired alarm date/time values. * Configure mask - Load the desired AMASK value. * Enable alarm - ALRMEN (RTCALRM<15>) = 0. Refer to Example 21-5. EXAMPLE 21-5: /* */ CONFIGURING THE RTCC FOR A TEN TIMES PER HOUR ALARM The following code example will update the RTCC repeat alarm. Assumes the interrupts are disabled. unsigned long alTime=0x23352300; unsigned long alDate=0x06111301; // set time to 23hr, 35 min, 23 sec // set date to Monday 13 Nov 2006 // // // // turn off the alarm, chime and alarm repeats; clear the alarm mask wait ALRMSYNC to be off clear the ALRMEN, CHIME, AMASK and ARPT; while(RTCALRM&0x1000); RTCALRMCLR=0xCFFF; ALRMTIME=alTime; ALRMDATE=alDate; RTCALRMSET=0x8000|0x0509; // update the alarm time and date // re-enable the alarm, set alarm mask at once per hour // for 10 times repeat DS61143A-page 412 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.3.4 INDEFINITE ALARM An indefinite alarm can be generated by configuring the CHIME bit (RTCALRM<14>) = 1; ARPT can be any value. Once the the alarm is enabled and an alarm event occurs, the ARPT count is decremented by one. ARPT rolls over from 0x00 to 0xFF and continues to decrement on each alarm event indefinitely. The ALRMEN bit is never automatically cleared in hardware. The user must clear this bit to disable the indefinite alarm. Note: An alarm event is generated when the ARPT are = 0x00. * Disable alarm - ALRMEN (RTCALRM<15>) = 0. * Enable chime - CHIME (RTCALRM<14>) = 1. * Configure alarm repeat counter - ARPT (RTCALRM<7:0>) = 0 to 256. * Configure alarm date and time - Load ALRMDATE and ALRMTIME registers with the desired alarm date/time values. * Configure mask - Load the desired AMASK value. * Enable Alarm - ALRMEN (RTCALRM<15>) = 0. Refer to Example 21-6. It is recommended to read and verify the Alarm Sync bit, ALRMSYNC (RTCALRM<12>) = 0, before performing the following configuration: EXAMPLE 21-6: /* */ CONFIGURING THE RTCC FOR INDEFINITE ALARM The following code example will update the RTCC indefinite alarm. Assumes the interrupts are disabled. unsigned long alTime=0x23352300; unsigned long alDate=0x06111301; // set time to 23hr, 35 min, 23 sec // set date to Monday 13 Nov 2006 // // // // turn off the alarm, chime and alarm repeats; clear the alarm mask wait ALRMSYNC to be off clear ALRMEN, CHIME, AMASK, ARPT; while(RTCALRM&0x1000); RTCALRMCLR=0xCFFF; ALRMTIME=alTime; ALRMDATE=alDate; RTCALRMSET=0xC600; // update the alarm time and date // re-enable the alarm, set alarm mask at once per // hour, enable CHIME 21.4 RTCC Clock Source 21.4.1 CALIBRATION The RTCC module is intended to be clocked by an external Real-Time Clock crystal that is oscillating at 32.768 kHz. To allow the RTCC to be clocked by an external 32.768 kHz crystal, the SOSCEN bit (OSCCON<1>) must be set (see Section 10.0 "Oscillators") or the FSOSCEN (DEVCFG1<5>) Configuration bit must be programmed to `1'. This is the only bit outside of the RTCC module with which the user must be concerned of for enabling the RTCC. The status bit, SOSCRDY (OSCCON<22>), can be used to check that the secondary oscillator is running. Note: The RTCC does not have an exclusive access to use the SOSC oscillator. This oscillator may be used by other peripherals, such as the CPU as a low-power clock source or Timer1. Refer to the "PIC32MX Family Reference Manual" (DS61132) regarding the operation of the Secondary Low-Power Oscillator. The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 0.66 seconds per month. Calibration has the ability to eliminate an error of up to 260 ppm. The calibration is accomplished by finding the number of error clock pulses and writing this value into the CAL field of the RTCCCON register (RTCCON<9:0>). This 10-bit signed value will either be added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute. 2. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 413 PIC32MX FAMILY EQUATION 21-1: ERROR CLOCKS PER MINUTE 4. Load the CAL bits (RTCCON<9:0>) with the correct value. Writes to the CAL bits should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse (except when the seconds (RTCTIME<15:8>) field is `00' due to the possibility of the auto-adjust event). Note: It is up to the user, to include in the error value, the initial error of the crystal drift, due to temperature and drift due to crystal aging. A write to the seconds bits resets the state of calibration (not its value). If an adjustment just occurred, it will occur again because of the minute roll over. (Ideal Frequency (32,758) - Measured Frequency) * 60 = Error Clocks per Minute 3. a) If the oscillator is faster than ideal (negative result from step 2), the CAL bits register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) If the oscillator is slower than ideal (positive result from step 2), the CAL bits register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. EXAMPLE 21-7: /* */ int cal=0x3FD; UPDATING THE RTCC CALIBRATION VALUE The following code example will update the RTCC calibration. // 10 bits adjustment, -3 in value if(RTCCON&0x8000) { unsigned intt0, t1; do { t0=RTCTIME; t1=RTCTIME; }while(t0!=t1); if((t0&0xFF)==00) { while(!(RTCCON&0x2)); } } RTCCONCLR=0x03FF0000; RTCCONSET=cal; // RTCC is ON // read valid time value // we're at second 00, wait auto-adjust to be performed // wait until second half... // clear the calibration DS61143A-page 414 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.5 RTCC Interrupts The RTCC alarm can be configured to generate an interrupt at every alarm event. Refer to Section 21.3 "Alarm Mode" for details regarding the various alarm events. The RTCC module is enabled as a source of interrupts via the respective RTCC interrupt enable bit: * RTCCIE (IEC1<15>). The alarm interrupt is signalled by the corresponding RTCC interrupt flag bit: * RTCCIF (IFS1<15>). This interrupt flag must be cleared in software. EXAMPLE 21-8: /* The following code example illustrates an RTCC initialization with interrupts enabled. When the RTCC alarm interrupt is generated, the cpu will jump to the vector assigned to RTCC interrupt. */ IEC1CLR=0x00008000; RTCCONCLR=0x8000; while(RTCCON&0x40); IFS1CLR=0x00008000; IPC8CLR=0x1f000000; IPC8SET=0x0d000000; IEC1SET=0x00008000; RTCTIME=0x16153300; RTCDATE=0x06102705; RTCALRMCLR=0xCFFF; ALRMTIME=0x16154300; ALRMDATE=0x06102705; // assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1; // disable RTCC interrupts // turn off the RTCC // wait for clock to be turned off // // // // clear RTCC existing event clear the priority Set IPL=3, subpriority 1 Enable RTCC interrupts The interrupt priority level bits and interrupt subpriority level bits must be also be configured: * RTCCIP<2:0> (IPC8<28:26>) * RTCCIS<1:0> (IPC8<25:24>) In addition to enabling the RTCC interrupt, an Interrupt Service Routine, ISR, is required (see Example 21-9).. Note: It is the user's responsibility to clear the corresponding interrupt flag bit before returning from an ISR. RTCC INITIALIZATION WITH INTERRUPTS // safe to update time to 16 hr, 15 min, 33 sec // update the date to Friday 27 Oct 2006 // clear ALRMEN, CHIME, AMASK and ARPT; // set alarm time to 16 hr, 15 min, 43 sec // set alarm date to Friday 27 Oct 2006 RTCALRMSET=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day RTCCONSET=0x8000; while(!(RTCCON&0x40)); // turn on the RTCC // wait for clock to be turned on (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 415 PIC32MX FAMILY EXAMPLE 21-9: /* The following code example demonstrates a simple interrupt service routine for RTCC interrupts. The user's code at this vector should perform any application specific operations and must clear the RTCC interrupt flag before exiting. */ void__ISR(_RTCC_VECTOR, ipl7) __RTCCInterrupt(void) { // ... perform application specific operations // in response to the interrupt IFS1CLR=0x00008000; } // be sure to clear RTCC interrupt flag // before exiting the service routine. RTCC ISR Note: The RTCC ISR code example shows MPLAB(R) C32 C compiler specific syntax. Refer to your compiler manual regarding support for ISRs. 21.6 I/O Pin Control Enabling the RTCC modules configures the I/O pin direction. When the RTCC module is enabled, configured and the output enabled, the I/O pin direction is properly configured as a digital output. The RTCC pin can be configured to toggle at every alarm or "seconds" event. To enable the RTCC pin output, set the RTCOE bit (RTCCON<0>) = 1. To select the output to toggle on an alarm event, configure RTSECSEL bit (RTCCON<7>) = 0. To select the output to toggle on every "seconds" update, configure RTSECSEL bit = 1. TABLE 21-3: IO Pin Name I/O PIN CONFIGURATION FOR USE WITH RTCC MODULE Required Settings for Module Pin Control Module Control Bit Field Pin Type Buffer Type Required TRIS(4) Description RTCC Yes(1) ON RTSECSEL = 1 and RTCOE(2) ON RTSECSEL = 0 and RTCOE(2) and ALRMEN and PIV(3) RTCC Seconds Clock X O CMOS RTCC Alarm Pulse X O CMOS RTCC Yes(1) Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output Note 1: The RTCC pin is only required when seconds clock or alarm pulse output is needed. Otherwise, this pin can be used for general purpose IO and require the user to set the corresponding TRIS control register bit. 2: The ON (RTCCON<15>) and RTCOE (RTCCON<0>) bits are always required to validate the output function of the RTCC pin, either seconds clock or alarm pulse. 3: When RTSECSEL (RTCCON<7>) = 0, the RTCC pin output is the alarm pulse. If the ALRMEN (RTCALRM<15>) = 0, PIV (RTCALRM<13>) selects the value at the RTCC pin. When the ALRMEN = 1, the RTCC pin reflects the state of the alarm pulse. 4: The setting of the TRIS bit is irrelevant. DS61143A-page 416 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 21.7 Updating the Time and Date Registers The following flowchart explains in detail the steps that have to be performed in order to update the RTCTIME and RTCDATE registers. Updating the RTCCTIME, RTCCDATE registers logic flow Start RTCCON.ON? Yes di No Wait RTCC clock off (ALRMEN && AMASK==HALFSEC && ALRMSYNC)||RTCSYNC? No Yes Write RTCTIME, RTCDATE Write RTCTIME, RTCDATE ? Or, slower Pulse=ALRMSYNC Or Pulse=RTCSYNC Either, faster ei ei While(pulse); RTCON.ON=0; di Wait RTCC clock off pulse? No Write RTCTIME, RTCDATE Yes Write RTCTIME, RTCDATE ei ei End (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 417 PIC32MX FAMILY 21.8 Updating the Alarm Registers The following flowchart explains in detail the steps that have to be performed in order to update the ALRMTIME, ALRMDATE and RTCALRM registers. Updating the ALRMTIME, ALRMDATE or RTCALRM registers logic flow Start No RTCC.ON? Yes Wait RTCC clock off. While(ALRMSYNC); di W rite RTCALRM, ALRMTIME, ALRMDATE ALRMSYNC? No Yes Write RTCALRM, ALRMTIME, ALRMDATE ei ei End DS61143A-page 418 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 22.0 Note: ANALOG-DIGITAL CONVERTER This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer. The PIC32MX Family 10-bit Analog-to-Digital (A/D) converter (or ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 400 kilo samples per second (ksps) conversion speed * Up to 16 analog input pins * External voltage reference input pins * One unipolar, differential Sample-and-Hold Amplifier (SHA) * Automatic Channel Scan mode * Selectable conversion trigger source * 16-word conversion result buffer * Selectable Buffer Fill modes * Eight conversion result format options * Operation during CPU SLEEP and IDLE modes A block diagram of the 10-bit ADC is shown in Figure 22-1. The 10-bit ADC can have up to 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The actual number of analog input pins and external voltage reference input configuration will depend on the specific PIC32MX device. Refer to the device data sheet for further details. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 419 PIC32MX FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD AVSS VREF+ VREFAN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 MUX B AN10 AN11 AN12 AN13 AN14 AN15 Pin Config Control Input MUX Control CH0NB Sample Control Control Logic CH0NA VINH VR Select VR+ 32 VRVINH Comparator + SHA VR- VR+ VINL - DAC + MUX A 10-bit SAR Conversion Logic - VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 VINH AD1CHS AD1PCFG AD1CSSL VINL Data Formatting + - Conversion Control DS61143A-page 420 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 22.1 Control Registers The ADC module includes the following Special Function Registers (SFRs): The AD1CON1, AD1CON2 and AD1CON3 registers control the operation of the ADC module. * AD1CON1: ADC Control Register 1 AD1CON1CLR, AD1CON1SET, AD1CON1INV: Atomic Bit Manipulation, Write-only Registers for AD1CON1. * AD1CON2: ADC Control Register 2 AD1CON2CLR, AD1CON2SET, AD1CON2INV: Atomic Bit Manipulation, Write-only Registers for AD1CON2. * AD1CON3: ADC Control Register 3 AD1CON3CLR, AD1CON3SET, AD1CON3INV: Atomic Bit Manipulation, Write-only Registers for AD1CON3. The AD1CHS register selects the input pins to be connected to the SHA. * AD1CHS: ADC Input Channel Select Register AD1CHSCLR, AD1CHSSET, AD1CHSINV: Atomic Bit Manipulation, Write-only Registers for AD1CHS. The AD1PCFG register configures the analog input pins as analog inputs or as digital I/O. * AD1PCFG: ADC Port Configuration Register AD1PCFGCLR, AD1PCFGSET, AD1PCFGINV: Atomic Bit Manipulation, Write-only Registers for AD1PCFG. The AD1CSSL register selects inputs to be sequentially scanned. * AD1CSSL: ADC Input Scan Selection Register AD1CSSLCLR, AD1CSSLSET, AD1CSSLINV: Atomic Bit Manipulation, Write-only Registers for AD1CSSL. The ADC module also has the following associated bits for interrupt control: * Interrupt Request Flag Status bit (AD1IF) in IFS1: Interrupt Flag Status Register 1 * Interrupt Enable Control bit (AD1IE) in IEC1: Interrupt Enable Control Register 1 * Interrupt Priority Control bits (AD1IP<2:0>) and (AD1IS<1:0>) in IPC6: Interrupt Priority Control Register 6 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 421 PIC32MX FAMILY 22.1.1 SPECIAL FUNCTION REGISTERS ASSOCIATED WITH THE 10-BIT ADC Table 22-1 provides a summary of all ADC-related registers, including their addresses and formats. Corresponding registers appear after the summary, followed by a detailed description of each register. All unimplemented registers and/or bits within a register read as zeros. TABLE 22-1: Virtual Address BF80_9000 Name ADC SFR SUMMARY Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- ON SSRC2 Bit 30/22/14/6 -- -- FRZ SSRC1 . Bit 29/21/13/5 -- -- SIDL SSRC0 Bit 28/20/12/4 -- -- -- CLRASAM Bit 27/19/11/3 -- -- -- -- Bit 26/18/10/2 -- -- FORM2 ASAM Bit 25/17/9/1 -- -- FORM1 SAMP Bit 24/16/8/0 -- -- FORM0 DONE AD1CON1 BF80_9004 BF80_9008 BF80_900C BF80_9010 AD1CON1CLR AD1CON1SET AD1CON1INV AD1CON2 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- VCFG2 BUFS Write clears selected bits in AD1CON1, read yields undefined value Write sets selected bits in AD1CON1, read yields undefined value Write inverts selected bits in AD1CON1, read yields undefined value -- -- VCFG1 -- -- -- VCFG0 SMPI3 -- -- OFFCAL SMPI2 -- -- -- SMPI1 -- -- CSCNA SMPI0 -- -- -- BUFM -- -- -- ALTS BF80_9014 BF80_9018 BF80_901C BF80_9020 AD1CON2CLR AD1CON2SET AD1CON2INV AD1CON3 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- ADRC ADCS7 Write clears selected bits in AD1CON2, read yields undefined value Write sets selected bits in AD1CON2, read yields undefined value Write inverts selected bits in AD1CON2, read yields undefined value -- -- -- ADCS6 -- -- -- ADCS5 -- -- SAMC4 ADCS4 -- -- SAMC3 ADCS3 -- -- SAMC2 ADCS2 -- -- SAMC1 ADCS1 -- -- SAMC0 ADCS0 BF80_9024 BF80_9028 BF80_902C BF80_9040 AD1CON3CLR AD1CON3SET AD1CON3INV AD1CHS 31:0 31:0 31:0 31:24 23:16 15:8 7:0 CH0NB CH0NA -- -- Write clears selected bits in AD1CON3, read yields undefined value Write sets selected bits in AD1CON3, read yields undefined value Write inverts selected bits in AD1CON3, read yields undefined value -- -- -- -- -- -- -- -- -- -- -- -- CH0SB3 CH0SA3 -- -- CH0SB2 CH0SA2 -- -- CH0SB1 CH0SA1 -- -- CH0SB0 CH0SA0 -- -- BF80_9044 BF80_9048 BF80_904C BF80_9060 AD1CHSCLR AD1CHSSET AD1CHS1INV AD1PCFG 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- PCFG15 PCFG7 -- -- Write clears selected bits in AD1CHS, read yields undefined value Write sets selected bits in AD1CHS, read yields undefined value Write inverts selected bits in AD1CHS, read yields undefined value -- -- PCFG13 PCFG5 -- -- PCFG12 PCFG4 -- -- PCFG11 PCFG3 -- -- PCFG10 PCFG2 -- -- PCFG9 PCFG1 -- -- PCFG8 PCFG0 PCFG14 PCFG6 BF80_9064 BF80_9068 BF80_906C BF80_9050 AD1PCFGCLR AD1PCFGSET AD1PCFGINV AD1CSSL 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- CSSL15 CSSL7 Write clears selected bits in AD1PCFG, read yields undefined value Write sets selected bits in AD1PCFG, read yields undefined value Write inverts selected bits in AD1PCFG, read yields undefined value -- -- CSSL14 CSSL6 -- -- CSSL13 CSSL5 -- -- CSSL12 CSSL4 -- -- CSSL11 CSSL3 -- -- CSSL10 CSSL2 -- -- CSSL9 CSSL1 -- -- CSSL8 CSSL0 DS61143A-page 422 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 22-1: Virtual Address BF80_9050 BF80_9050 BF80_9050 BF80_9070 BF80_9080 BF80_9090 BF80_90A0 BF80_9070 BF80_90C0 BF80_90D0 BF80_90E0 BF80_90F0 BF80_910 BF80_9110 BF80_9120 BF80_9130 BF80_9140 BF80_9150 BF80_9160 Name AD1CSSLCLR AD1CSSLSET AD1CSSLINV ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 ADC SFR SUMMARY (CONTINUED) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Write clears selected bits in AD1CSSL, read yields undefined value Write sets selected bits in AD1CSSL, read yields undefined value Write inverts selected bits in AD1CSSL, read yields undefined value ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 423 PIC32MX FAMILY REGISTER 22-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SSRC<2:0> R/W-0 R/W-0 CLRASAM U-0 -- R/W-0 ASAM R/W-0 SAMP R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- R/W-0 R/W-0 FORM<2:0> bit 8 R/C-0 DONE bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- AD1CON1: ADC CONTROL REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 Unimplemented: Read as `0' ON: ADC Operating Mode bit 1 = A/D converter module is operating 0 = A/D converter is off FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU enters Debug Exception mode 0 = Continue operation when CPU enters Debug Exception mode Note: FRZ is writable in Debug Exception mode only. It reads `0' in Normal mode. SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' FORM<2:0>: Data Output Format bits 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) bit 14 bit 13 bit 12-11 bit 10-8 DS61143A-page 424 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 22-1: bit 7-5 AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion CLRASAM: Stop Conversion Sequence bit (when the first A/D converter interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence Unimplemented: Read as `0' ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit 1 = The ADC SHA is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing `1' to this bit starts sampling. When SSRC = 000, writing `0' to this bit will end sampling and start conversion. DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done or has not started Clearing this bit will not affect any operation in progress. Note: Bit is cleared by software, or by hardware, at the start of a new conversion. bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 425 PIC32MX FAMILY REGISTER 22-2: U-0 -- bit 31 U-0 -- bit 23 R/W-0 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-13 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM R/W-0 VCFG<2:0> R/W-0 R/W-0 OFFCAL U-0 -- R/W-0 CSCNA U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- AD1CON2: ADC CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 ALTS bit 0 SMPI<3:0> Unimplemented: Read as `0' VCFG<2:0>: Voltage Reference Configuration bits ADC VR+ 000 001 010 011 1xx AVDD External VREF+ pin AVDD External VREF+ pin AVDD ADC VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode VINH and VINL of the SHA are connected to VR0 = Disable Offset Calibration mode The inputs to the SHA are controlled by AD1CHS or AD1CSSL bit 11 bit 10 Unimplemented: Read as `0' CSCNA: Scan Input Selections for CH0+ SHA Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit Only valid when BUFM = 1 (ADRES split into 2 x 8-word buffers). 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as `0' bit 9-8 bit 7 bit 6 DS61143A-page 426 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 22-2: bit 5-2 AD1CON2: ADC CONTROL REGISTER 2 (CONTINUED) SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF(7...0), ADC1BUF(15...8) 0 = Buffer configured as one 16-word buffer ADC1BUF(15...0.) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always use MUX A input multiplexer settings bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 427 PIC32MX FAMILY REGISTER 22-3: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ADRC bit 15 R/W-0 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 SAMC<4:0> bit 8 R/W-0 bit 0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- AD1CON3: ADC CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 ADCS<7:0> Unimplemented: Read as `0' ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from Peripheral Bus Clock (PBClock) Unimplemented: Read as `0' SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD ***** 00001 = 1 TAD 00000 = 0 TAD (Not allowed) ADCS<7:0>: ADC Conversion Clock Select bits 11111111 =TPB * (ADCS<7:0> + 1) * 2 = 512 * TPB = TAD ****** 00000001 =TPB * (ADCS<7:0> + 1) * 2 = 4 * TPB = TAD 00000000 =TPB * (ADCS<7:0> + 1) * 2 = 2 * TPB = TAD bit 14-13 bit 12-8 bit 7-0 DS61143A-page 428 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 22-4: R/W-0 CH0NB bit 31 R/W-0 CH0NA bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- r-0 -- R/W-0 R/W-0 R/W-0 AD1CHS: ADC INPUT SELECT REGISTER U-0 -- U-0 -- r-0 -- R/W-0 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 U-0 -- bit 8 CH0SB<3:0> CH0SA<3:0> CH0NB: Negative Input Select for MUX B bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' Reserved: Reserved for future use, maintain as `0' CH0SB<3:0>: Positive Input Select for MUX B bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 1101 = Channel 0 positive input is AN13 || || || 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Negative Input Select for MUX A Multiplexer Setting bit(2) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' Reserved: Reserved for future use, maintain as `0' CH0SA<3:0>: Positive Input Select for MUX A Multiplexer Setting bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 1101 = Channel 0 positive input is AN13 || || || 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 Unimplemented: Read as `0' bit 30-29 bit 28 bit 27-24 bit 23 bit 22-21 bit 20 bit 19-16 bit 15-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 429 PIC32MX FAMILY REGISTER 22-5: r-0 -- bit 31 r-0 -- bit 23 R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W PCFG1 R/W-0 PCFG14 R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- AD1PCFG: ADC PORT CONFIGURATION REGISTER r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- bit 24 r-0 -- bit 16 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0 Reserved: Reserved for future use, maintain as `0' PCFG<15:0>: Analog Input Pin Configuration Control bits 1 = Analog input pin in Digital mode, port read input enabled, ADC input multiplexer input for this analog input connected to AVss 0 = Analog input pin in Analog mode, digital port read will return as a `1' without regard to the voltage on the pin, ADC samples pin voltage Note: The AD1PCFG register functionality will vary depending on the number of ADC inputs available on the selected device. Please refer to the specific device data sheet for additional details on this register. DS61143A-page 430 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 22-6: r-0 -- bit 31 r-0 -- bit 23 R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W CSSL1 R/W-0 CSSL14 R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- AD1CSSL: ADC INPUT SCAN SELECT REGISTER r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- bit 24 r-0 -- bit 16 R/W-0 CSSL8 bit 8 R/W-0 CSSL0 bit 0 Reserved: Reserved for future use, maintain as `0' CSSL<15:0>: ADC Input Pin Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note: The AD1CSSL register functionality will vary depending on the number of ADC inputs available on the selected device. Please refer to the specific device data sheet for additional details on this register. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 431 PIC32MX FAMILY 22.2 ADC Operation, Terminology and Conversion Sequence Acquisition time can be controlled manually or automatically. The acquisition time may be started manually by setting the SAMP bit (AD1CON1<1>), and ended manually by clearing the SAMP in the user software. The acquisition time may be started automatically by the A/D converter hardware and ended automatically by a conversion trigger source. The acquisition time is set by the SAMC bits (AD1CON3<12:8>). The SHA has a minimum acquisition period. Refer to the device data sheet for acquisition time specifications Conversion time is the time required for the A/D converter to convert the voltage held by the SHA. The A/D converter requires one ADC clock cycle (TAD) to convert each bit of the result, plus two additional clock cycles. Therefore, a total of 12 TAD cycles are required to perform the complete conversion. When the conversion time is complete, the result is written into one of the 16 ADC result registers (ADC1BUF0...ADC1BUFF). The sum of the acquisition time and the A/D conversion time provides the total sample time (refer to Figure 22-2). There are multiple input clock options for the A/D converter that are used to create the TAD clock. The user must select an input clock option that does not violate the minimum TAD specification. The sampling process can be performed once, periodically, or based on a trigger as defined by the module configuration. This section will describe the operation the A/D converter, the steps required to configure the converter, describe the special feature of the module, and provide examples of ADC configuration with timing diagrams and charts showing the expected output of the converter. 22.2.1 OVERVIEW OF OPERATION Analog sampling consists of two steps: acquisition and conversion (see Figure 22-2). During acquisition the analog input pin is connected to the Sample and Hold Amplifier (SHA). After the pin has been sampled for a sufficient period, the sample voltage is equivalent to the input, the pin is disconnected from the SHA to provide a stable input voltage for the conversion process. The conversion process then converts the analog sample voltage to a binary representation. An overview of the ADC is presented in Figure 22-1. The 10-bit A/D converter has a single SHA. The SHA is connected to the analog input pins via the analog input MUXs, MUX A and MUX B. The analog input MUXs are controlled by the AD1CHS register. There are two sets of MUX control bits in the AD1CHS register. These two sets of control bits allow the two different analog input to be independently controlled. The A/D converter can optionally switch between MUX A and MUX B configurations between conversions. The A/D converter can also optionally scan through a series of analog inputs using a single MUX. FIGURE 22-2: ADC SAMPLE/CONVERSION SEQUENCE ADC Total Sample Time Acquisition Time A/D Conversion Time A/D conversion complete, result is written into the ADC result buffer. Optionally generate interrupt. SHA is disconnected from input and holds the signal. A/D conversion is started by the conversion trigger source. SHA is connected to the analog input pin for sampling. DS61143A-page 432 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY The start time for sampling can be controlled in software by setting the SAMP control bit. The start of the sampling time can also be controlled automatically by the hardware. When the A/D converter operates in the Auto-Sample mode, the SHA is reconnected to the analog input pin at the end of the conversion in the sample/convert sequence. The auto-sample function is controlled by the ASAM control bit (AD1CON1<2>). The conversion trigger source ends the sampling time and begins an A/D conversion or a sample/convert sequence. The conversion trigger source is selected by the control bits SSRC<2:0> (AD1CON1<7:5>). The conversion trigger can be taken from a variety of hardware sources, or can be controlled manually in software by clearing the SAMP control bit. One of the conversion trigger sources is an auto-conversion. The time between auto-conversions is set by a counter and the ADC clock. The Auto-Sample mode and auto-conversion trigger can be used together to provide endless automatic conversions without software intervention. An interrupt may be generated at the end of each sample sequence or multiple sample sequences as determined by the value of the SMPI<3:0> (AD1CON2<5:2>). The number of sample sequences between interrupts can vary between 1 and 16. The user should note that the A/D conversion buffer holds the results of a single conversion sequence. The next sequence starts filling the buffer from the top even if the number of samples in the previous sequence was less than 16. The total number of conversion results between interrupts is the SMPI value. The total number of conversions between interrupts cannot exceed the physical buffer length. can select from integer, signed integer, fractional or signed fractional as a 16-bit or 32-bit result.". C-2. Select the sample clock source using SSRC<2:0> (AD1CON1<7:5>), as described in Section 22.3.3.1 "Selecting the Sample Clock Source". D-1. Select the voltage reference source using VCFG<2:0> (AD1CON2<15:13>), as described in Section 22.3.6 "Selecting the Voltage Reference Source". D-2. Select the Scan mode using CSCNA (AD1CON2<10>), as described in Section 22.3.7 "Selecting the Scan Mode". D-3. Set the number of conversions per interrupt SMPI<3:0> (AD1CON2<5:2>), if interrupts are to be used, as described in Section 22.3.8 "Setting the Number of Conversions per Interrupt". D-4. Set Buffer Fill mode using BUFM (AD1CON2<1>), as described in Section 22.3.9 "Buffer Fill Mode". D-5. Select the MUX to be connected to the ADC in ALTS (AD1CON2<0>), as described in Section 22.3.10 "Selecting the MUX to be Connected to the ADC (Alternating Sample Mode)". E-1. Select the ADC clock source using ADRC (AD1CON3<15>), as described in Section 22.3.11 "Selecting the ADC Conversion Clock Source and Prescaler". E-2. Select the sample time using SAMC<4:0> (AD1CON3<12:8>), if auto-convert is to be used, as described in Section 22.3.12 "Acquisition Time Considerations". E-3. Select the ADC clock prescaler using ADCS<7:0> (AD1CON3<7:0>), as described in Section 22.3.11 "Selecting the ADC Conversion Clock Source and Prescaler". F. Turn on ADC module using AD1CON1<15>, as described in Section 22.3.13 "Turning the ADC On". Steps A through E, above, can be performed in any order, but Step F must be the final step in every case. 22.3 ADC Module Configuration Operation of the ADC module is directed through bit settings in the appropriate registers. The following instructions summarize the actions and the settings. Options and details for each configuration step are provided in subsequent sections. 1. To configure the ADC module, perform the following steps: A-1. Configure analog port pins in AD1PCFG<15:0>, as described in Section 22.3.1 "Configuring Analog Port Pins". B-1. Select the analog inputs to the ADC MUXs in AD1CHS<32:0>, as described in Section 22.3.2 "Selecting the Analog Inputs to the ADC MUXs". C-1. Select the format of the ADC result using FORM<2:0> (AD1CON1<10:8>), as described in Section "The data in the ADC Result register can be read as one of eight formats. The format is controlled by FORM<2:0> (AD1CON1<10:8>). The user Note: 2. To configure ADC interrupt (if required). A-1. Clear AD1IF bit (IFS1<1>), as described in Section 9.0 "Interrupts". A-2. Select ADC interrupt priority AD1IP<2:0> (IPC<28:26>) and sub priority AD1IS<1:0> (IPC<24:24>), as described in Section 9.0 "Interrupts", if interrupts are to be used. 3. Start the conversion sequence by initiating (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 433 PIC32MX FAMILY sampling, as described in Section 22.3.14 "Initiating Sampling". 22.3.3 SELECTING THE FORMAT OF THE ADC RESULT 22.3.1 CONFIGURING ANALOG PORT PINS The AD1PCFG register and the TRISB register control the operation of the ADC port pins. AD1PCFG specifies the configuration of device pins to be used as analog inputs. A pin is configured as an analog input when the corresponding PCFGn bit (AD1PCFG The data in the ADC Result register can be read as one of eight formats. The format is controlled by FORM<2:0> (AD1CON1<10:8>). The user can select from integer, signed integer, fractional or signed fractional as a 16-bit or 32-bit result. 22.3.3.1 Selecting the Sample Clock Source It is often desirable to synchronize the end of sampling and the start of conversion with some other time event. The ADC module may use one of four sources as a conversion trigger. The selection of the conversion trigger source is controlled by the SSRC<2:0> (AD1CON1<7:5>) bits. 22.3.3.2 Manual Conversion To configure the ADC to end sampling and start a conversion when SAMP is cleared (= 0), SSRC is set to `000'. 22.3.3.3 Timer Compare Trigger The ADC is configured for this Trigger mode by setting SSRC<2:0> = 010. When a period match occurs for the 32-bit timer, TMR3/TMR2, or the 16-bit Timer3, a special A/D converter trigger event signal is generated by Timer3. 22.3.2 SELECTING THE ANALOG INPUTS TO THE ADC MUXS The AD1CHS register is used to select which analog input pin is connected to MUX A and MUX B. Each MUX has two inputs referred to as the positive and the negative input. The positive input to MUX A is controlled by CH0SA<4:0> and the negative input is controlled by CH0NA. The positive input for MUX B is controlled by CH0SB<4:0> and the negative input is controlled by CH0NB. The positive input can be selected from any one of the available analog input pins. The negative input can be selected as the ADC negative reference or AN0. The use of AN0 as the negative input allows the ADC to be used in a Unipolar Differential mode. Refer to the device data sheet for AN0 input voltage restrictions when used as a negative reference. DS61143A-page 434 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 22.3.3.3.1 External INT0 Pin Trigger To configure the ADC to begin a conversion on an active transition on the INT0 pin, SSRC<2:0> is set to `001'. The INT0 pin may be programmed for either a rising edge input or a falling edge input to trigger the conversion process. 22.3.3.3.2 Auto-Convert 22.3.7 SELECTING THE SCAN MODE The ADC module has the ability to scan through a selected vector of inputs. The CSCNA bit (AD1CON2<10>) enables the MUX A input to be scanned across a selected number of analog inputs. The ADC can be configured to automatically perform conversions at the rate selected by the Auto-Sample Time bits, SAMC<4:0>. The ADC is configured for this Trigger mode by setting SSRC<2:0> = 111. In this mode, the ADC will perform continuous conversions on the selected channels. 22.3.7.1 Scan Mode Enable 22.3.4 SYNCHRONIZING ADC OPERATIONS TO INTERNAL OR EXTERNAL EVENTS Scan mode is enabled by setting CSCNA (AD1CON2<10>). When Scan mode is enabled, the positive input of MUX A is controlled by the contents of the AD1CSSL register. Each bit in the AD1CSSL register corresponds to an analog input. Bit 0 corresponds to AN0, bit 1 corresponds to AN1 and so on. If a particular bit in the AD1CSSL register is `1', the corresponding input is part of the scan sequence. The modes where an external event trigger pulse ends sampling and starts conversion (SSRC2:SSRC0 = 001, 010 or 011) may be used in combination with auto-sampling (ASAM = 1) to cause the ADC to synchronize the sample conversion events to the trigger pulse source. For example, where SSRC = 010 and ASAM = 1, the ADC will always end sampling and start conversions synchronously with the timer compare trigger event. The ADC will have a sample conversion rate that corresponds to the timer comparison event rate. 22.3.7.2 Using Scan and Alternate Modes Together The Scan and Alternate modes may be combined to allow a vector of inputs to be scanned and a single input to be converted every other sample. This mode is enabled by setting the CSCNA bit = 1, and setting the ALTS (AD1CON2<0>) bit = 1. The CSCNA bit enables the scan for MUX A, and the CH0SB<3:0> (AD1CHS<27:24>) and CH0NB (AD1CHS<31>) are used to configure the inputs to MUX B. Scanning only applies to the MUX A input selection. The MUX B input selection, as specified by CH0SB<3:0>, will still select a single input. 22.3.5 SELECTING AUTOMATIC OR MANUAL SAMPLING Sampling can be started manually or automatically when the previous conversion is complete. 22.3.8 SETTING THE NUMBER OF CONVERSIONS PER INTERRUPT 22.3.5.1 Manual Clearing the ASAM (AD1CON1<2>) bit disables the Auto-Sample mode. Acquisition will begin when the SAMP (AD1CON1<1>) bit is set by software. Acquisition will not resume until the SAMP bit is once again set. 22.3.5.2 Automatic Setting the ASAM (AD1CON1<2>) bit enables the Auto-Sample mode. In this mode, the sampling will start automatically after the pervious sample has been converted. The SMPI<3:0> bits (AD1CON2<5:2>) select how many A/D conversions will take place before a CPU interrupt is generated. This also defines the number of locations that will be written in the result buffer stating with ADC1BUF0 (ADC1BUF0 or ADC1BUF8 for Dual Buffer mode). This can vary from 1 sample to 16 samples (1 to 8 samples for Dual Buffer mode). After the interrupt is generated, the sampling sequence restarts; with the result of the first sample being written to the first buffer location. The data in the result registers will be overwritten by the next sampling sequence. The data in the result buffer must be read before the completion of the first sample after the interrupt is generated. 22.3.6 SELECTING THE VOLTAGE REFERENCE SOURCE The user can select the voltage reference for the ADC module. The reference can be internal or external. The VCFG<2:0> control bits (AD1CON2<15:13>) select the voltage reference for A/D conversions. The upper voltage reference (VR+) and the lower voltage reference (VR-) may be the internal AVDD and AVSS voltage rails, or the VREF+ and VREF- input pins. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 435 PIC32MX FAMILY 22.3.9 BUFFER FILL MODE The Buffer Fill mode allows the output buffer to be used as a single, 16-word buffer or two, 8-word buffers. When BUFM is `0', the complete 16-word buffer is used for all conversion sequences. Conversion results will be written sequentially in the buffer, starting at ADC1BUF0 until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The next conversion result will be written to ADC1BUF0 and the process repeats. If the ADC interrupt is enabled, an interrupt will be generated when the number of samples in the buffer equals SMPI<3:0>. When the BUFM bit (AD1CON2<1>) is `1', the 16-word results buffer (ADRES) will be split into two 8-word groups. Conversion results will be written sequentially into the first buffer starting at ADC1BUF0, BUFS (AD1CON2<7>) will be cleared, until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The ADC interrupt flag will then be set. After the ADC interrupt flag is set, the following result will be written sequentially to the second buffer, starting at ADC1BUF8 The next conversion result will be written to the second buffer; starting at ADC1BUF8, BUFS (AD1CON2<7>) will be set until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The ADC interrupt flag will then be set. The process then restarts with BUFS = 0 and the results being written to the first buffer. The inputs specified by CH0SA<3:0> and CH0NA are called the MUX A inputs. The inputs specified by CH0SB<3:0> and CH0NB are called the MUX B inputs. When ALTS is `1', the module will alternate between the MUX A inputs on one sample and the MUX B inputs on the subsequent sample. When ALTS is `0', only the inputs specified by CH0SA<3:0> and CH0NA are selected for sampling. 22.3.11 SELECTING THE ADC CONVERSION CLOCK SOURCE AND PRESCALER The ADC module can use the internal RC oscillator or the PBCLK as the conversion clock source. When the internal RC oscillator is used as the clock source, ADRC (AD1CON3<15>) = 1, the TAD is the period of the oscillator, no prescaler are used. When using the internal oscillator the ADC can continue to function in SLEEP and in IDLE. When the PBCLK is used as the conversion clock source, ADRC = 0, the TAD is the period of the PBCLK after the prescaler ADCS<7:0> (AD1CON3<7:0>) is applied. The A/D converter has a maximum rate at which conversions may be completed. An analog module clock, TAD, controls the conversion timing. The A/D conversion requires 12 clock periods (12 TAD). The period of the ADC conversion clock is software selected using a 8-bit counter. There are 256 possible options for TAD, specified by the ADCS<7:0> bits (AD1CON3<7:0>). Equation 22-3 gives the TAD value as a function of the ADCS control bits and the device instruction cycle clock period, TCY. 22.3.10 SELECTING THE MUX TO BE CONNECTED TO THE ADC (ALTERNATING SAMPLE MODE) The ADC has two input MUXs that connect to the SHA. These MUXs are used to select which analog input is to be sampled. Each of the MUXs have a positive and a negative input. EQUATION 22-3: TAD = 22.3.10.1 Single Input Selection ADC CONVERSION CLOCK PERIOD TPB(ADCS + 1) 2 2 * TAD TPB -1 The user may select one of up to 16 analog inputs, as determined by the number of analog channels on the device, as the positive input of the SHA. The CH0SA<3:0> bits (AD1CHS<19:16>) select the positive analog input. The user may select either VR- or AN1 as the negative input. The CH0NA bit (AD1CHS<23>) selects the analog input for the negative input of channel 0. Using AN1 as the negative input allows unipolar differential measurements. The ALTS bit (AD1CON2<0>) must be clear for this mode of operation. ADCS = For correct A/D conversions, the ADC conversion clock (TAD) must be selected to meet the minimum TAD time. 22.3.10.2 Alternating Input Selections The ALTS bit causes the module to alternate between the two input MUXs. DS61143A-page 436 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EQUATION 22-4: AVAILABLE SAMPLING TIME, SEQUENTIAL SAMPLING ically started after a conversion is completed. AutoSample mode can be used with any trigger source other than manual. TSMP TSMP = Trigger Pulse Interval (TSEQ) - Conversion Time (TCONV) = TSEQ - TCONV TSEQ is the trigger pulse interval time. 22.4 Miscellaneous ADC Functions The following section describes bits not covered in the previous section. 22.4.1 Note: Aborting Sampling 22.3.12 ACQUISITION TIME CONSIDERATIONS Clearing the SAMP (AD1CON1<1>) bit while in Manual Sample mode will terminate sampling, but may also start a conversion if SSRC (AD1CON1<7:5>) = 000. Clearing the ASAM (AD1CON1<2>) bit while in AutoSample mode will not terminate an ongoing acquire/ convert sequence, however, sampling will not automatically resume after the current sample is converted. Different acquisition/conversion sequences provide different times for the sample-and-hold channel to acquire the analog signal. The user must ensure the acquisition time meets the sampling requirements. When SSRC<2:0> (AD1CON1<7:5>) = 111, the conversion trigger is under ADC clock control. The SAMC<4:0> bits (AD1CON3<12:8>) select the number of TAD clock cycles between the start of acquisition and the start of conversion. This trigger option provides the fastest conversion rates on multiple channels. After the start of acquisition, the module will count a number of TAD clocks specified by the SAMC bits. 22.4.2 ABORTING A CONVERSION Clearing the ON (AD1CON1<15>) bit during a conversion will abort the current conversion. The ADC Result register will NOT be updated with the partially completed A/D conversion sample. That is, the corresponding result buffer location will continue to contain the value of the last completed conversion (or the last value written to the buffer). 22.3.13 TURNING THE ADC ON 22.4.3 BUFFER FILL STATUS When the ON bit (AD1CON1<15>) is `1', the module is in Active mode and is fully powered and functional. When ON is `0', the module is disabled. The digital and analog portions of the circuit are turned off for maximum current savings. In order to return to the Active mode from the Off mode, the user must wait for the analog stages to stabilize. For the stabilization time, refer to the Electrical Characteristics section of the device data sheet. Note: Writing to ADC control bits other than ON (AD1CON1<15>), SAMP (AD1CON1<1>), and DONE (AD1CON1<0>) is not recommended while the A/D converter is running. When the conversion result buffer is split using the BUFM control bit, the BUFS Status bit (AD1CON2<7>) indicates which half of the buffer the A/D converter is currently filling. If BUFS = 0, then the A/D converter is filling ADC1BUF0-ADC1BUF7 and the user software should read conversion values from ADC1BUF8ADC1BUFF. If BUFS = 1, the situation is reversed and the user software should read conversion values from ADC1BUF0-ADC1BUF7. 22.4.4 OFFSET CALIBRATION The ADC module provides a method of measuring the internal offset error. After this offset error is measured, it can be subtracted, in software, from the result of an A/D conversion. Use the following steps to perform an offset measurement: 1. 2. Configure the A/D converter in the same manner as it will be used in the application. Set the OFFCAL bit (AD1CON2<12>). This overrides the input selections and connects the sample and hold inputs to AVss. If auto-sample is used set the CLRASAM bit (AD1CON1<4>) to force conversions. Enable the A/D converter and perform a conversion. The result that is written to the ADC result buffer is the internal offset error. Clear the OFFCAL (AD2CON<12>) bit to return the A/D converter to normal operation. Note: Only positive ADC offsets can be measured with this method. DS61143A-page 437 22.3.14 22.3.14.1 INITIATING SAMPLING Manual Mode In manual sampling, a acquisition is started by writing a `1' to the SAMP (AD1CON1<1>) bit. Software must manually manage the start and end of the acquisition period by setting SAMP and then clearing SAMP after the desired acquisition period has elapsed. 3. 4. 22.3.14.2 Auto-Sample Mode In Auto-Sample mode, the sampling process is started by writing a `1' to the ASAM (AD1CON1<2>) bit. In Auto-Sample mode, the acquisition period is defined by ADCS<7:0> (AD1CON3<7:0>). Acquisition is automat- 5. (c) 2007 Microchip Technology Inc. Advance Information PIC32MX FAMILY 22.4.5 TERMINATE CONVERSION SEQUENCE AFTER AN INTERRUPT 22.4.6 CONVERSION SEQUENCE EXAMPLES The CLRASAM bit provides a method to terminate auto-sample after the first sequence is completed. Setting the CLRASAM and starting an auto-sample sequence will cause the A/D converter to complete one auto-sample sequence (the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>)). Hardware will clear ASAM (AD1CON1<2>) and set the interrupt flag. This will stop the sampling process to allow inspection of the result buffer without results being overwritten by the next automatic conversion sequence. The CLRASAM must be cleared by software to disable this mode. Note: Disabling interrupts or masking the ADC interrupt has no effect on the operation of the CLRASAM bit. The following configuration examples show the ADC operation in different sampling and buffering configurations. In each example, setting the ASAM bit starts automatic sampling. A conversion trigger ends sampling and starts conversion. 22.4.7 MANUAL CONVERSION CONTROL When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit (AD1CON1<1>) starts the conversion sequence. See Example 22-1 for sample code to manually control the sampling of a single channel. EXAMPLE 22-1: CONVERTING 1 CHANNEL, MANUAL SAMPLE START, MANUAL CONVERSION START CODE // // // // // PORTB = Digital; RB2 = analog SAMP bit = 0 ends sampling ... and starts converting Connect RB2/AN2 as CH0 input .. in this example RB2/AN2 is the input AD1PCFG = 0xFFFB; AD1CON1 = 0x0000; AD1CHS = 0x00020000; AD1CSSL = 0; AD1CON3 = 0x0002; AD1CON2 = 0; // Manual Sample, Tad = internal 2 Tcy AD1CON1SET = 0x8000; // while (1) // { AD1CON1SET = 0x0002; // DelayNmSec(100); // AD1CON1CLR = 0x0002; // while (!(AD1CON1 & 0x0001));// ADCValue = ADC1BUF0; // } // turn ADC ON repeat continuously start sampling ... for 100 mS start Converting conversion done? yes then get ADC value repeat 22.4.8 AUTOMATIC ACQUISITION Automatic acquisition control is enabled by setting the ASAM (AD1CON1<2>) bit. Setting the ASAM bit initiates automatic acquisition, and clearing the SAMP (AD1CON1<1>) bit terminates sampling and starts conversion. After the conversion completes, the module will automatically return to an acquisition state. The SAMP bit is automatically set at the start of the acquisition interval. The user software must time the clearing of the SAMP bit to ensure adequate acquisition time of the input signal, understanding that the time between clearing of the SAMP bit includes the conversion time as well as the acquisition time. See Example 22-2 for a code example. DS61143A-page 438 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 22-2: CONVERTING 1 CHANNEL, AUTOMATIC SAMPLE START, MANUAL CONVERSION START CODE // // // // // // all PORTB = Digital but RB7 = analog ASAM bit = 1 implies acquisition .. starts immediately after last conversion is done Connect RB7/AN7 as CH0 input .. in this example RB7/AN7 is the input AD1PCFG = 0xFF7F; AD1CON1 = 0x0004; AD1CHS = 0x00070000; AD1CSSL = 0; AD1CON3 = 0x0002; AD1CON2 = 0; // Sample time manual, Tad = internal 2 Tcy AD1CON1SET = 0x8000; // while (1) // { DelayNmSec(100); // AD1CON1SET = 0x0002; // while (!(AD1CON1 & 0x0001));// ADCValue = ADC1BUF0; // } // turn ADC ON repeat continuously sample for 100 mS start Converting conversion done? yes then get ADC value repeat 22.4.9 CLOCKED CONVERSION TRIGGER When SSRC<2:0> = 111, the conversion trigger is under ADC clock control. The SAMC bits (AD1CON3<4:0>) select the number of TAD clock cycles between the start of acquisition and the start of conversion. This trigger option provides the fastest conversion rates on multiple channels. After the start of acquisition, the module will count a number of TAD clocks specified by the SAMC bits. EQUATION 22-1: CLOCKED CONVERSION TRIGGER TIME TSMP = SAMC<4:0>* TAD SAMC must always be programmed for at least one clock cycle. See Example 22-1 for a code example. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 439 PIC32MX FAMILY Example 22-1: Converting 1 Channel, Manual Sample Start, TAD Based Conversion Start Code // // // // // // all PORTB = Digital; RB12 = analog SSRC bit = 111 implies internal counter ends sampling and starts converting. Connect RB12/AN12 as CH0 input .. in this example RB12/AN12 is the input AD1PCFG = 0xEFFF; AD1CON1 = 0x00E0; AD1CHS = 0x000C0000; AD1CSSL = 0; AD1CON3 = 0x1F02; AD1CON2 = 0; // Sample time = 31Tad AD1CON1SET = 0x8000; while (1) { AD1CON1CLR = 0x0002; while (!(AD1CON1 & 0x0001)); ADCValue = ADC1BUF0; } // turn ADC ON // repeat continuously // // // // // start sampling then ... after 31Tad go to conversion conversion done? yes then get ADC value repeat DS61143A-page 440 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 22.4.10 Free-Running Sample Conversion Sequence The Auto-Convert Conversion Trigger mode (SSRC = 111) in combination with the Automatic Sampling Start mode (ASAM = 1), allows the ADC module to schedule acquisition/conversion sequences with no intervention by the user or other device resources. This "Clocked" mode allows continuous data collection after module initialization. See Example 22-3 for a code example. EXAMPLE 22-3: AD1PCFG = 0xFFFB; AD1CON1 = 0x00E0; CONVERTING 1 CHANNEL, AUTO-SAMPLE START, AUTO-CONVERT CODE // // // // // // all PORTB = Digital; RB2 = analog SSRC bit = 111 internal counter ends sampling and starts converting. Connect RB2/AN2 as CH0 input .. in this example RB2/AN2 is the input AD1CHS = 0x00020000; AD1CSSL = 0; AD1CON3 = 0x0F00; AD1CON2 = 0x0004; // Sample time = 15Tad // Interrupt after every 2 samples AD1CON1SET = 0x8000; AD1CON1SET = 0x0004; while (1) { IFS1CLR = 0x0002; while (!IFS1 & 0x0002); // turn ADC ON // auto start sampling // repeat continuously // clear ADC interrupt flag // for 31Tad then go to conversion // poll for conversion done\ // result of conversions is available in ADC1BUF0 // and ADC1BUF1 22.4.11 SAMPLING A SINGLE CHANNEL MULTIPLE TIMES inputs. Other conditions are similar to the previous example (see Section 22.4.11 "Sampling a Single Channel Multiple Times"). Initially, the AN0 input is acquired and converted. The result is stored in the ADC1BUF buffer. Then the AN1 input is acquired and converted. This process of scanning the inputs repeats 16 times until the buffer is full and then the module generates an interrupt. Then the entire process repeats. In this case, one ADC input, AN0, will be acquired and converted. The results are stored in the ADC1BUF buffer. This process repeats 15 times until the buffer is full, and then the module generates an interrupt. Then entire process repeats. With ALTS (AD1CON2<0>) clear, only the MUX A inputs are active. The CH0SA (AD1CHS<19:16>) bits and CH0NA (AD1CHS<23>) bit are specified (AN0VREF-) as the input to the sample/hold channel. Other input selection bits are not used. 22.4.12.1 Example: Using Dual 8-Word Buffers 22.4.12 EXAMPLE: A/D CONVERSIONS WHILE SCANNING THROUGH ANALOG INPUTS A typical setup might include all available analog input channels to be sampled and converted. The CSCNA (AD1CON2<10>) bit specifies scanning of the ADC To enable the dual 8-word buffers and alternating the buffer fill, set the BUFM (AD1CON2<1>) bit. The BUFM setting does not affect other operational parameters. First, the conversion sequence starts filling the buffer at ADC1BUF0 (buffer location 0 x 0). After the first interrupt occurs, the buffer begins to fill at ADC1BUF8 (buffer location 0 x 8). The BUFS (AD1CON2<7>) bit is alternately set and cleared after each interrupt to show which buffer is being filled. In this example, three analog inputs are sampled and an interrupt occurs after every third sample. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 441 PIC32MX FAMILY 22.4.12.2 Example: Using Alternating MUX A, MUX B Input Selections 22.5 Initialization Setting the ALTS (AD1CON2<0>) bit enables alternating input selections. The first sample uses the MUX A inputs specified by the CH0SA (AD1CHS<19:16>) and CH0NA (AD1CHS<23>) bits. The next sample uses the MUX B inputs specified by the CH0SB (AD1CHS<27:24>) and CH0NB (AD1CHS<31>) bits. In the following example, one of the MUX B input specifications uses 2 analog inputs as a differential source to the sample/hold. This example also demonstrates use of the dual 8-word buffers. An interrupt occurs after every 4th sample, which results in filling 4-words into the buffer on each interrupt. A simple initialization code example for the ADC module is provided in Example 22-4. In this particular configuration, all 16 analog input pins, AN0-AN15, are set up as analog inputs. Operation in IDLE mode is disabled, output data is in unsigned fractional format, and AVDD and AVSS are used for VR+ and VR-. The start of acquisition, as well as start of conversion (conversion trigger), are performed manually in software. The CH0 SHA is used for conversions. Scanning of inputs is disabled, and an interrupt occurs after every acquisition/convert sequence (1 conversion result). The ADC conversion clock is TPB/2. Since acquisition is started manually by setting the SAMP bit (AD1CON1<1>) after each conversion is complete, the auto-sample time bits, SAMC<4:0> (AD1CON3<12:8>), are ignored. Moreover, since the start of conversion (i.e., end of acquisition) is also triggered manually, the SAMP bit needs to be cleared each time a new sample needs to be converted. 22.4.12.3 Example: Converting Three Analog Inputs Using Alternating Sample Mode and a Scan List It is possible to sample by scanning through the input channels and alternate between MUX A and MUX B. When the Alternating Sample mode is selected, the first input to be sampled will be the input selected for MUX A, the second sample will be the input selected for MUX B. Then the process repeats. When scanning is combined with Alternating Input mode, the positive input to MUX A is selected by the contents of the AD1CSSL register, not CH0SA. For each sample that MUX A is selected the next item in the scan list is sampled. The positive input to MUX B is selected by CH0SB (AD1CHS<27:24>). When ASAM (AD1CON1<2>) is clear, sampling will not resume after conversion completion, but will occur when setting the SAMP (AD1CON1<1>) bit. DS61143A-page 442 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY EXAMPLE 22-4: ADC INITIALIZATION CODE EXAMPLE /* Configure ADC port all input pins are analog */ /* Configure sample clock source and Conversion Trigger mode. Unsigned Fractional format, Manual conversion trigger, Manual start of sampling, Simultaneous sampling, No operation in IDLE mode. */ /* Configure ADC voltage reference and buffer fill modes. VREF from AVDD and AVSS, Inputs are not scanned, Interrupt every sample */ /* Configure ADC conversion clock */ /* Configure input channels, CH0+ input is AN0. CHO- input is VREFL (AVss) /* No inputs are scanned. Note: Contents of AD1CSSL are ignored when CSCNA = 0 */ /*Clear ADC conversion interrupt*/ AD1PCFG = 0x0000; AD1CON1 = 0x2208; AD1CON2 = 0x0000; AD1CON3 = 0x0000; AD1CHS = 0x0000; AD1CSSL = 0x0000; IFS1CLR = 2; // Configure ADC interrupt priority bits (AD1IP<2:0>) here, if // required. (default priority level is 4) IEC1SET = 2; AD1CON1SET = 0x8000; AD1CON1SET = 0x0002; DelayNmSec(100); /* Enable ADC conversion interrupt*/ /* Turn on the ADC module */ /* Start sampling the input */ /* Ensure the correct sampling time has elapsed before starting a conversion.*/ /* End Sampling /* The DONE bit is finished. /* The ADIF bit and start Conversion*/ is set by hardware when the convert sequence */ will be set. */ AD1CON1CLR = 0x0002; : : (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 443 PIC32MX FAMILY 22.6 I/O Pin Control The pins used for analog input can also be used for digital I/O. Configuring a pin for analog input requires three steps. Any digital peripherals that share the desired pin must be disabled. The pin must be configured as a digital input, by setting the corresponding TRIS bit to a `1' to disable the output driver. Then, the pin must be placed in Analog mode by setting the corresponding bit in the AD1PCFG register. TABLE 22-2: Pin Name AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 VREF+ VREF- PINS ASSOCIATED WITH THE ADC MODULE Module Control ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Controlling Bit Field AD1PCFG<0> AD1PCFG<1> AD1PCFG<2> AD1PCFG<3> AD1PCFG<4> AD1PCFG<5> AD1PCFG<6> AD1PCFG<7> AD1PCFG<8> AD1PCFG<9> AD1PCFG<10> AD1PCFG<11> AD1PCFG<12> AD1PCFG<13> AD1PCFG<14> AD1PCFG<15> AD1CON2<15:13> AD1CON2<15:13> Pin Type A A A A A A A A A A A A A A A A P P Buffer Type -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A = Analog P = Power TRIS Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input -- -- Description Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Positive Voltage Reference Negative Voltage Reference Legend: ST = Schmitt Trigger input with CMOS levels I = Input O = Output DS61143A-page 444 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 22.6.1 ADC CONVERSION SPEEDS The PIC32MX 10-bit A/D converter specifications permit a maximum 400 ksps sampling rate. Table 22-3 summarizes the conversion speeds for the PIC32MX 10-bit A/D converter and the required operating conditions.. TABLE 22-3: 10-BIT CONVERSION RATE PARAMETERS PIC32MX 10-Bit A/D Converter Conversion Rates TAD Sampling Minimum Time Min 200 ns 2 TAD ADC Speed 400 ksps(1) RS Max 500 VDD 4.5V to 5.5V Temperature -40C to +85C ADC Channels Configuration VREF- VREF+ ANx CHX SHA ADC Up to 400 ksps 200 ns 1 TAD 5.0 k 4.5V to 5.5V -40C to +125C VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC ANx Up to 300 ksps 256.41 ns 1 TAD 5.0 k 3.0V to 5.5V -40C to +125C VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC ANx Note 1: External VREF- and VREF+ pins must be used for correct operation. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 445 PIC32MX FAMILY 22.6.2 ADC SAMPLING REQUIREMENTS The analog input model of the 10-bit A/D converter is shown in Figure 22-3. The total acquisition time for the A/D conversion is a function of the internal amplifier settling time and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The analog output source impedance (RS), the interconnect impedance (RIC) and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the CHOLD. The combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy of the A/D converter, the maximum recommended source impedance, RS, is 5 k for the conversion rates of up to 300 ksps and a maximum of 500 for conversion rates of up to 400 ksps). After the analog input channel is selected (changed), this acquisition function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation. At least 1 TAD time period should be allowed between conversions for the acquisition time. For more details, see the device electrical specifications. FIGURE 22-3: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA ANx CPIN VT = 0.6V RIC 250 Sampling Switch RSS RSS 3 k VT = 0.6V ILEAKAGE 500 nA CHOLD = DAC Capacitance = 4.4 pF VSS Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k. Legend: CPIN = input capacitance RSS = sampling switch resistance RS = source resistance VT = threshold voltage RIC = interconnect resistance CHOLD = sample/hold capacitance (from DAC) ILEAKAGE = leakage current at the pin due to various junctions DS61143A-page 446 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 23.0 Note: COMPARATOR This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. Following are some of the key features of this module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the comparator module is shown in Figure 23-1. The PIC32MX Family Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways. FIGURE 23-1: COMPARATOR BLOCK DIAGRAM Comparator 1 CREF C1IN+ CVREF CCH<1:0> C1INC1IN+ C2IN+ IVREF(1) C1 COE ON COUT (CM1CON) C1OUT (CMSTAT) CPOL C1OUT Comparator 2 CREF C2IN+ CVREF CCH<1:0> C2INC2IN+ C1IN+ IVREF(1) C2 COE ON COUT (CM2CON) C2OUT (CMSTAT) CPOL C2OUT Note 1: IVref is the internal 1.2V reference. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 447 PIC32MX FAMILY 23.1 Note: Comparator Control Registers Each PIC32MX device variant may have one or more Comparator modules. An `x' used in the names of pins, control/status bits and registers denotes the particular module. Refer to the specific device data sheets for more details. Table 23-1 provides brief summaries of all comparator related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. A Comparator module consists of the following Special Function Registers (SFRs): * CMxCON: Comparator Control Register * CMxCONCLR, CMxCONSET, CMxCONINV: Atomic Bit Manipulation Registers for CMxCON * CMSTAT: Comparator Status Registers * CMSTATCLR, CMSTATSET, CMSTATINV: Atomic Bit Manipulation Registers for CMSTAT The comparator module also has the following interrupt control registers: * IFS1: Interrupt Flag Status Register * IEC: Interrupt Enable Control Register * IPC7: Interrupt Priority Control Register TABLE 23-1: Virtual Address COMPARATOR SFRS SUMMARY Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 31:24 23:16 15:8 7:0 -- -- ON -- -- COE -- -- CPOL -- -- -- -- CREF -- -- -- -- -- -- -- -- -- -- -- Bit 24/16/8/0 -- -- COUT Name BF80_A000 CM1CON EVPOL<1:0> CCH<1:0> BF80_A004 CM1CONCLR BF80_A008 CM1CONSET BF80_A00C CM1CONINV BF80_A010 CM2CON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- ON Write clears selected bits in CM1CON, read yields undefined value Write sets selected bits in CM1CON, read yields undefined value Write inverts selected bits in CM1CON, read yields undefined value -- -- COE -- -- CPOL -- -- -- -- CREF -- -- -- -- -- -- -- -- -- -- -- -- -- COUT EVPOL<1:0> CCH<1:0> BF80_A004 CM2CONCLR BF90_A008 CM2CONSET BF80_A00C CM2CONINV BF80_A060 CMSTAT 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- -- -- Write clears selected bits in CM2CON, read yields undefined value Write sets selected bits in CM2CON, read yields undefined value Write inverts selected bits in CM2CON, read yields undefined value -- -- FRZ -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C2OUT -- -- -- C1OUT BF80_A064 CMSTATCLR BF80_A068 CMSTATSET BF80_A06C CMSTATINV BF88_1010 BF88_1040 BF88_10D0 IFS1 IEC1 31:0 31:0 31:0 7:0 7:0 Write clears selected bits in CMSTAT, read yields undefined value Write sets selected bits in CMSTAT, read yields undefined value Write inverts selected bits in CMSTAT, read yields undefined value SPI2RXIF SPI2TXIF SPI2RXIE SPI2TXIE -- -- -- -- SPI2EIF SPI2EIE -- -- CMP2IF CMP2IE CMP1IF CMP1IE CMP2IP<2:0> CMP1IP<2:0> PMPIF PMPIE AD1IF AD1IE CNIF CNIE IPC7 IPC7 23:16 15:8 CMP2IS<1:0> CMP1IS<1:0> DS61143A-page 448 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 23-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 U-0 -- R/W-0 CREF U-0 -- U-0 -- R/W-1 R/W-0 COE R/W-0 CPOL r-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CM1CON: COMPARATOR 1 CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 COUT bit 8 R/W-1 bit 0 EVPOL<1:0> CCH<1:0> Unimplemented: Read as `0' ON: Comparator ON bit 1 = Module is enabled. Setting this bit does not affect the other bits in this register. 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register. COE: Comparator Output Enable bit 1 = Comparator output is driven on the output C1OUT pin 0 = Comparator output is not driven on the output C1OUT pin CPOL: Comparator Output Inversion bit 1 = Output is inverted 0 = Output is not inverted Note: Setting this bit will invert the signal to the to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. Reserved: Maintain as `0' Unimplemented: Read as `0' COUT: Comparator Output bit 1 = Output of the comparator is a `1' 0 = Output of the comparator is a `0' EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11-9 bit 8 bit 7-6 bit 5 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 449 PIC32MX FAMILY REGISTER 23-1: bit 4 CM1CON: COMPARATOR 1 CONTROL REGISTER (CONTINUED) CREF: Comparator 1 Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the C1IN+ pin Unimplemented: Read as `0' CCH<1:0>: Comparator Negative Input Select bits for Comparator 1 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the C2IN+ pin 01 = Comparator inverting input is connected to the C1IN+ pin 00 = Comparator inverting input is connected to the C1IN- pin bit 3-2 bit 1-0 DS61143A-page 450 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 23-2: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 R/W-1 bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-1 U-0 -- R/W-0 CREF U-0 -- U-0 -- R/W-1 R/W-0 COE R/W-0 CPOL r-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CM2CON: COMPARATOR 2 CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R-0 COUT bit 8 R/W-1 bit 0 EVPOL<1:0> CCH<1:0> Unimplemented: Read as `0' ON: Comparator ON bit 1 = Module is enabled. Setting this bit does not affect the other bits in this register. 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register. COE: Comparator Output Enable bit 1 = Comparator output is driven on the output C2OUT pin 0 = Comparator output is not driven on the output C2OUT pin CPOL: Comparator Output Inversion bit 1 = Output is inverted 0 = Output is not inverted Note: Setting this bit will invert the signal to the to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. Reserved: Maintain as `0' Unimplemented: Read as `0' COUT: Comparator Output bit 1 = Output of the comparator is a `1' 0 = Output of the comparator is a `0' EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11-9 bit 8 bit 7-6 bit 5 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 451 PIC32MX FAMILY REGISTER 23-2: bit 4 CM2CON: COMPARATOR 2 CONTROL REGISTER (CONTINUED) CREF: Comparator 1 Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the C2IN+ pin Unimplemented: Read as `0' CCH<1:0>: Comparator Negative Input Select bits for Comparator 2 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the C1IN+ pin 01 = Comparator inverting input is connected to the C2IN+ pin 00 = Comparator inverting input is connected to the C2IN- pin bit 3-2 bit 1-0 DS61143A-page 452 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 23-3: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-15 bit 14 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0 C2OUT R-0 C1OUT bit 0 R/W-0 FRZ R/W-0 SIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CMSTAT: COMPARATOR CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' FRZ: Freeze Control bit 1 = Freeze operation when CPU enters Debug Exception mode 0 = Continue operation when CPU enters Debug Exception mode Note: FRZ is writable in Debug Exception mode only. It always reads `0' in normal mode. SIDL: Stop in Idle Control bit 1 = All comparator modules are disabled in IDLE mode 0 = All comparator modules continue to operate in IDLE mode. Unimplemented: Read as `0' C2OUT: Comparator Output bit 1 = Output of comparator 2 is a `1' 0 = Output of comparator 2 is a `0' C1OUT: Comparator Output bit 1 = Output of comparator 1 is a `1' 0 = Output of comparator 1 is a `0' bit 13 bit 12-2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 453 PIC32MX FAMILY REGISTER 23-4: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 20-18 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-0 -- U-0 -- R/W-0 R/W-0 PMPIP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CMP1IP<2:0> R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 R/W-0 CMP2IP<2:0> R/W-0 R/W-0 IPC7- INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 -- U-0 -- R/W-0 R/W-0 SPI2IP<2:0> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 16 R/W-0 bit 8 R/W-0 bit 0 SPI2IS<1:0> CMP2IS<1:0> CMP1IS<1:0> PMPIS<1:0> CMP2IP<2:0>: Comparator 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CMP2IS<1:0>: Comparator 2 Interrupt Sub Priority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 CMP1IP<2:0>: Comparator 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled CMP1IS<1:0>: Comparator 1 Interrupt Sub Priority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 17-6 bit 12-10 bit 9-8 DS61143A-page 454 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 23.2 23.2.1 Comparator Operation COMPARATOR CONFIGURATION 23.3 Comparator Inputs The Comparator module has a flexible input and output configuration to allow the module to be tailored to the needs of the application. The PIC32MX Family comparator module has individual control over the enables, output inversion, output on I/O pin and input selections. The VIN+ pin of each comparator can select from an input pin or the CVREF. The VIN- input of the comparator can select from one of 3 input pins or the IVREF. In addition, the module has two individual comparator event generation control bits. These control bits can be used for detecting when the output of an individual comparator changes to a desired state or changes states. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay (refer to the device data sheet for more information). Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may be generated. Depending on the Comparator Operating mode, the inputs to the comparators may be from two input pins or a combination of an input pin and one of two internal voltage references. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is set or cleared according to the result of the comparison (see Figure 23-2). FIGURE 23-2: SINGLE COMPARATOR VIN+ VIN- + - Output VIN+ VIN- A single comparator is shown in the upper portion of Figure 23-2. The lower portion represents the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input at VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in the lower portion of Figure 23-2 demonstrate the uncertainty that is due to input offsets and the response time of the comparator. Output 23.3.0.1 External Reference Signal An external voltage reference may be used with the comparator by using the output of the reference as an input to the comparator. Refer to the device data sheet for input voltage limits. 23.3.0.2 Internal Reference Signals The CVREF module and the IVREF can be used as inputs to the comparator (see Figure 23-1). The CVREF provides a user-selectable voltage for use as a comparator reference. Refer to 24.0 "Comparator Reference" of this manual for more information on this module. The IVREF has a fixed, 1.2V output that does not change with the device supply voltage. Refer to the device data sheet for specific details and accuracy of this reference. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 455 PIC32MX FAMILY 23.4 Comparator Outputs 23.5 The comparator output is read through the CMSTAT register and the COUT bit (CM2CON<8> or CM1CON<8>). This bit is read-only. The comparator output may also be directed to an I/O pin via the CxOUT bit; however, the COUT bit is still valid when the signal is routed to a pin. For the comparator output to be available on the CxOut pin, the associated TRIS bit for the output pin must be configured as an output. When the COUT signal is routed to a pin the signal is the unsynchronized output of the comparator. The output of the comparator has a degree of uncertainty. The uncertainty of each of the comparators is related to the input offset voltage and the response time, as stated in the specifications. The lower portion of Figure 23-2 provides a graphical representation of this uncertainty. The comparator output bit, COUT, provides the latched sampled value of the comparator's output- when the register was read. There are two common methods used to detect a change in the comparator output: * Software polling * Interrupt generation Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 23-3. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. See the device data sheet for input voltage limits. If a pin is to be shared by two or more analog inputs that are to be used simultaneously, the loading effects of all the modules involved must be taken into consideration. This loading may reduce the accuracy of one or more of the modules connected to the common pin. This may also require a lower source impedance than is stated for a single module with exclusive use of a pin in Analog mode. Notes: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. 23.4.1 CHANGING THE POLARITY OF COMPARATOR OUTPUTS The polarity of the comparator outputs can be changed using the CPOL bit (CMxCON<13>). CPOL appears below the comparator Cx on the left side of Figure 23-1. FIGURE 23-3: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k AIN VA CPIN 5 pF ILEAKAGE 500 nA RIC Comparator Input VSS Legend: CPIN ILEAKAGE RIC RS VA = = = = = Input Capacitance Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage DS61143A-page 456 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 23.6 Interrupts COMPARATOR INITIALIZATION WITH INTERRUPTS ENABLED CODE EXAMPLE // // // // // // // // // // // // // Configure both comparators to generate an interrupt on any output transition Initialize Comparator 1 Comparator enabled, output enabled, interrupt on any output change, inputs: CVref, C1INInitialize Comparator 2 Comparator enabled, output enabled, interrupt on any output change, inputs: C2IN+, C1IN+ Enable interrupts for Comparator modules and set priorities Set priority to 7 & sub priority to 3 Set CMP1 interrupt sub priority Clear the CMP1 interrupt flag Enable CMP1 interrupt EXAMPLE 23-1: CM1CON = 0xC0D0; CM2CON = 0xA0C2; IPC7SET = 0x00000700; IFS1CLR = 0x00000008; IEC1SET = 0x00000008; IPC7SET = 0x00070000; IFS1CLR = 0x000000010; IEC1SET = 0x000000010; // Set CMP2 interrupt sub priority // Clear the CMP2 interrupt flag // Enable CMP2 interrupt EXAMPLE 23-2: COMPARATOR ISR CODE EXAMPLE // Insert user code here #pragma interrupt CmpIntHandler ipl4 vector 29 void CmpIntHandler(void) { // Insert user code here IFS1CLR = 0x00000010; // Clear the CMP2 interrupt flag } #pragma interrupt CmpIntHandler ipl4 vector 30 void CmpIntHandler(void) { // Insert code user here IFS1CLR = 0x00000008; // Clear the CMP1 interrupt flag } (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 457 PIC32MX FAMILY 23.7 I/O Pin Control PINS ASSOCIATED WITH A COMPARATOR Controlling Bit Field CVREF(1), CCH<1:0>(1), CCH<1:0>(2), AD1PCFG CCH<1:0>(1), AD1PCFG CVREF(2), CCH<1:0>(1), CCH<1:0>(2), AD1PCFG CCH<1:0>(2), AD1PCFG COE(1) COE(2) Required TRIS Bit Setting Input Input Input Input Output Output Pin Type A, I A, I A, I A, I D, O D, O Buffer Type -- -- -- -- -- -- Description Analog Input for C1IN+ Analog Input for C1INAnalog Input for C2IN+ Analog Input for C2INDigital Output of the C1 Digital Output of the C2 TABLE 23-2: Pin Name C1IN+ C1INC2IN+ C2INC1OUT C2OUT Module Control ON ON ON ON ON ON Legend: ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output, A = Analog, D = Digital Note 1: In CM1CON register. 2: In CM2CON register. DS61143A-page 458 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 24.0 Note: COMPARATOR REFERENCE This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. The Comparator Voltage Reference (CVREF) is a 16tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. A block diagram of the module is shown in Figure 24-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. Please see the specific device data sheet for information. The comparator voltage reference has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R R R R CVR3:CVR0 CVREN 16 Steps 16-to-1 MUX R CVREF R R R CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 459 PIC32MX FAMILY 24.1 Comparator Voltage Reference Control Registers Table 24-1 provides a brief summary of all CVREF module related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. The CVREF module consists of the following Special Function Registers (SFRs): * CVRCON: Control Register for the Module * CVRCONCLR, CVRCONSET, CVRCONINV: atomic Bit Manipulation Registers for CVRCON TABLE 24-1: Virtual Address BF80_9800 COMPARATOR VOLTAGE REFERENCE SFR SUMMARY Name CVRCON 31:24 23:16 15:8 7:0 Bit 31/23/15/7 -- -- ON -- Bit 30/22/14/6 -- -- -- CVROE Bit 29/21/13/5 -- -- -- CVRR Bit 28/20/12/4 -- -- -- CVRSS Bit 27/19/11/3 -- -- -- Bit 26/18/10/2 -- -- -- CVR<3:0> Bit 25/17/9/1 -- -- Bit 24/16/8/0 -- -- BF80_9804 BF80_9808 BF80_980C CVRCONCLR CVRCONSET CVRCONINV 31:0 31:0 31:0 Write clears selected bits in CVRCON, read yields undefined value Write sets selected bits in CVRCON, read yields undefined value Write inverts selected bits in CVRCON, read yields undefined value DS61143A-page 460 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 24-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 R/W-0 bit 0 CVR<3:0> Unimplemented: Read as `0' ON: CVREF Peripheral On bit 1 = Module is enabled; setting this bit does not affect the other bits in the register 0 = Module is disabled and does not consume current; clearing this bit does not affect the other bits in the register Unimplemented: Read as `0' CVROE: CVREF Output Enable bit 1 = Voltage level is output on CVREF pin 0 = Voltage level is disconnected from CVREF pin Note: CVROE overrides the TRIS bit setting; see Section 12.0 "I/O Ports" for more information. CVRR: CVREF Range Selection bit 1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD - AVSS CVR<3:0>: CVREF Value Selection 0 CVR3:CVR0 15 bits When CVRR = 1: CVREF = (CVR<3:0>/24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR<3:0>/32) * (CVRSRC) bit 14-7 bit 6 bit 5 bit 4 bit 3-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 461 PIC32MX FAMILY 24.2 Operation The CVREF module is controlled through the CVRCON register (Register 24-1). The CVREF provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Value Selection bits, CVR3:CVR0, with one range offering finer resolution and the other offering a wider range of output voltage. The typical output voltages are listed in Table 24-2. The equations used to calculate the CVREF output are as follows: If CVRR = 1: Voltage Reference = ((CVR3:CVR0)/ 24) x (CVRSRC) If CVRR = 0: Voltage Reference = (CVRSRC/ 4) + ((CVR3:CVR0)/32) x (CVRSRC) The CVREF Source Voltage (CVRSRC) can come from either VDD and VSS, or the external VREF+ and VREFpins that are multiplexed with I/O pins. The voltage source is selected by the CVRSS bit (CVRCON<4>). The voltage reference is output to the CVREF pin by setting the CVROE (CVRCON<6>) bit; this will override the corresponding TRIS bit setting. The settling time of the CVREF must be considered when changing the CVREF output (refer to the data sheet for your device). TABLE 24-2: CVR<3:0> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TYPICAL VOLTAGE REFERENCE WITH CVRSRC = 3.3 Voltage Reference CVRR = 0 (CVRCON <5>) 0.83V 0.93V 1.03V 1.13V 1.24V 1.34V 1.44V 1.55V 1.65V 1.75V 1.86V 1.96V 2.06V 2.17V 2.27V 2.37V CVRR = 1 (CVRCON <5> 0.00V 0.14V 0.28V 0.41V 0.55V 0.69V 0.83V 0.96V 1.10V 1.24V 1.38V 1.51V 1.65V 1.79V 1.93V 2.06V DS61143A-page 462 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 24.2.1 CVREF OUTPUT CONSIDERATIONS The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 24-1) keep the voltage reference from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the voltage reference output changes with fluctuations in that source. Refer to the product data sheet for the electrical specifications. Table 24-3 contains the typical output impedances for the CVREF module. TABLE 24-3: TYPICAL CVREF OUTPUT IMPEDANCE IN OHMS Voltage Reference CVRR = 0 (CVRCON <5>) 12k 13k 13.8k 14.4k 15k 15.4k 15.8k 15.9k 16k 15.9k 15.8k 15.4k 15k 14.4k 13.8k 12.9k CVRR = 1 (CVRCON <5> 500 1.9k 3.7k 5.3k 6.7k 7.9k 9k 9.9k 10.7k 11.3k 11.7k 11.9k 12k 11.9k 11.7k 11.3k CVR<3:0> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24.2.2 INITIALIZATION This initialization sequence, shown in Example 24-1, configures the CVREF module for: module enabled, output enabled, high range, and set output for maximum (2.37V). EXAMPLE 24-1: VOLTAGE REFERENCE CONFIGURATION //Initialize Voltage Reference Module //enable module, enable output, set // range to high, set output to maximum CVRCON = 0x804F; (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 463 PIC32MX FAMILY 24.3 Interrupts There are no Interrupt configuration registers or bits for the CVREF module. The CVREF module does not generate interrupts. 24.4 I/O Pin Control The CVREF module has the ability to output to a pin. When the CVREF module is enabled and CVROE (CVRCON<6>) is `1', the output driver for the CVREF pin is disabled and the CVREF voltage is available at the pin. For proper operation, the TRIS bit corresponding to the CVREF pin must be a `1' when CVREF is to be output to a pin. This disables the Digital Input mode for the pin and prevents undesired current draw resulting from applying an analog voltage to a digital input pin. The output buffer has very limited drive capability. An external buffer amplifier is recommended for any application that uses the CVREF voltage externally. An output capacitor may be used to reduce output noise. Use of an output capacitor will increase settling time. TABLE 24-4: Pin Name CVREF Legend: PINS ASSOCIATED WITH A COMPARATOR Module Control ON Controlling Bit Field CVROE Required TRIS Bit Setting Input Pin Type A, O Buffer Type -- CVREF Output Description ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output, A = Analog, D = Digital DS61143A-page 464 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 25.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. PIC32MX Family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * Flexible Device Configuration * Code Protection * Internal Voltage Regulator TABLE 25-1: Virtual Address BFC0_2FF0 DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- USERID15 USERID7 -- -- -- -- -- FWDTEN IESO -- -- PWP15 -- -- -- -- -- -- PWP14 -- Bit 30/22/14/6 -- -- USERID14 USERID6 -- -- -- Bit 29/21/13/5 -- -- USERID13 USERID5 -- -- -- FPLLMULT<2:0> -- -- FPBDIV<1:0> FSOSCEN -- -- PWP13 -- -- CP -- PWP12 -- -- -- -- PWP19 -- ICESEL -- PWP18 -- -- -- Bit 28/20/12/4 -- -- USERID12 USERID4 -- -- -- Bit 27/19/11/3 -- -- USERID11 USERID3 -- -- -- -- -- -- WDTPS<4:0> OSCIOFNC POSCMD<1:0> FNOSC<2:0> -- PWP17 -- BWP PWP16 -- -- Bit 26/18/10/2 -- -- USERID10 USERID2 -- Bit 25/17/9/1 -- -- USERID9 USERID1 -- FPLLODIV<2:0> -- FPLLIDIV<2:0> -- -- -- Bit 24/16/8/0 -- -- USERID8 USERID0 -- DEVCFG3 BFC0_2FF4 DEVCFG2 31:24 23:16 15:8 7:0 BFC0_2FF8 DEVCFG1 31:24 23:16 15:8 7:0 FCKSM<1:0> BFC0_2FFC DEVCFG0 31:24 23:16 15:8 7:0 DEBUG<1:0> TABLE 25-2: Virtual Address BF80_F220 DEVID SUMMARY Name DEVID 31:24 23:16 15:8 7:0 Bit 31/23/15/7 VER3 -- DEV3 MANID7 Bit 30/22/14/6 VER2 -- DEV2 MANID6 Bit 29/21/13/5 VER1 -- DEV1 MANID5 Bit 28/20/12/4 VER0 -- DEV0 MANID4 Bit 27/19/11/3 -- DEV7 MANID11 MANID3 Bit 26/18/10/2 -- DEV6 MANID10 MANID2 Bit 25/17/9/1 -- DEV5 MANID9 MANID1 Bit 24/16/8/0 -- DEV4 MANID8 1 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 465 PIC32MX FAMILY REGISTER 25-1: r-0 -- bit 31 r-1 -- bit 23 R/P-1 PWP15 bit 15 r-1 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31 bit 30-29 bit 28 DEVCFG0: DEVICE CONFIGURATION WORD 0 r-1 -- r-1 -- R/P-1 CP r-1 -- r-1 -- r-1 -- R/P-1 BWP bit 24 R/P-1 PWP16 bit 16 r-1 -- bit 8 r-1 -- r-1 -- r-1 -- R/P-1 ICESEL r-1 -- R/P-1 DEBUG1 R/P-1 DEBUG0 bit 0 r-1 -- r-1 -- r-1 -- R/P-1 PWP19 R/P-1 PWP18 R/P-1 PWP17 R/P-1 PWP14 R/P-1 PWP13 R/P-1 PWP12 r-1 -- r-1 -- r-1 -- W = Writable bit P = Programmable bit -n = Bit Value at POR: (`0', `1', x = Unknown) r = Reserved bit bit 27-25 bit 24 bit 23-20 Reserved: Maintain as `0'. Reserved: Maintain as `1' CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled Reserved: Maintain as `1' BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable Reserved: Maintain as `1' DS61143A-page 466 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY (Continued) bit 19-12 PWP<19:12>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF ... 01111111 = 0xBD07_FFFF Reserved: Maintain as `1' ICESEL: ICE/ICD Communication Channel Select bit 1 = ICE uses PGC2/PGD2 pins 0 = ICE uses PGC1/PGD1 pins Reserved: Maintain as `1' DEBUG<1:0>: Background Debugger Enable bits 11 = Debugger disabled (forced if device is code-protected) 10 = ICE debugger enabled 01 = Reserved 00 = Reserved bit 11-4 bit 3 bit 2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 467 PIC32MX FAMILY REGISTER 25-2: r-1 -- bit 31 R/P-1 FWDTEN bit 23 R/P-1 bit 15 R/P-1 IESO bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-24 bit 23 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) r-1 -- R/P-1 FSOSCEN r-1 -- r-1 -- R/P-1 R/P-1 FNOSC<2:0> bit 0 R/P-1 R/P-1 R/P-1 r-1 -- R/P-1 OSCIOFNC R/P-1 r-1 -- r-1 -- R/P-1 R/P-1 R/P-1 WDTPS<4:0> bit 16 R/P-1 bit 8 R/P-1 R/P-1 DEVCFG1: DEVICE CONFIGURATION WORD 1 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 R/P-1 FCKSM<1:0> FPBDIV<1:0> POSCMD<1:0> bit 22-21 bit 20-16 bit 15-14 Reserved: Maintain as `1' FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software Reserved: Maintain as `1' WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = `10100' FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled DS61143A-page 468 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY (Continued) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Reserved: Maintain as `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 OR 00) 0 = CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Reserved: Maintain as `1' FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Maintain as `1' FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: Do not disable POSC (POSCMD = 00) when using this oscillator source. bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 469 PIC32MX FAMILY REGISTER 25-3: r-1 -- bit 31 r-1 -- bit 23 r-1 -- bit 15 r-1 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-19 bit 18-16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/P-1 R/P-1 FPLLMULT<2:0> R/P-1 r-1 -- R/P-1 R/P-1 FPLLIDIV<2:0> bit 0 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FPLLODIV<2:0> bit 16 r-1 -- bit 8 R/P-1 DEVCFG2: DEVICE CONFIGURATION WORD 2 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 R/P-1 bit 15-7 bit 6-4 bit 3 bit 2-0 Reserved: Maintain as `1' FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 Reserved: Maintain as `1' FPLLMULT<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier Reserved: Maintain as `1' FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider DS61143A-page 470 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 25-4: r-1 -- bit 31 r-1 -- bit 23 R/P-x USERID15 bit 15 R/P-x USERID7 bit 7 DEVCFG3: DEVICE CONFIGURATION WORD 3 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- bit 16 R/P-x USERID8 bit 8 R/P-x USERID0 bit 0 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- R/P-x USERID14 R/P-x USERID13 R/P-x USERID12 R/P-x USERID11 R/P-x USERID10 R/P-x USERID9 R/P-x USERID6 R/P-x USERID5 R/P-x USERID4 R/P-x USERID3 R/P-x USERID2 R/P-x USERID1 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit -n = Bit Value at POR: (`0', `1', x = Unknown) r = Reserved bit Reserved: Maintain as `1' USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSPTM and JTAG. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 471 PIC32MX FAMILY REGISTER 25-5: R VER3 bit 31 r -- bit 23 R DEV3 bit 15 R-0 MANID07 bit 7 DEVID: DEVICE ID REGISTER R VER1 R VER0 r -- r -- r -- r -- bit 24 R DEV4 bit 16 R-0 MANID08 bit 8 R-1 1 bit 0 R VER2 r -- r -- r -- R DEV7 R DEV6 R DEV5 R DEV2 R DEV1 R DEV0 R-0 MANID11 R-0 MANID10 R-0 MANID09 R-0 MANID06 R-0 MANID05 R-0 MANID04 R-0 MANID03 R-0 MANID02 R-0 MANID01 Legend: R = Readable bit U = Unimplemented bit bit 31-28 bit 27-20 bit 19-12 W = Writable bit P = Programmable bit -n = Bit Value at POR: (`0', `1', x = Unknown) r = Reserved bit bit 11-1 bit 0 VER<3:0>: Revision Identifier bits Reserved: For factory use only DEVID<7:0>: Device ID 38h = PIC32MX360F512L 34h = PIC32MX360F256L 2Ah = PIC32MX320F128L 12h = PIC32MX340F256H 0Ah = PIC32MX320F128H 06h = PIC32MX320F064H 00h = PIC32MX300F032H MANID<11:0>: JEDEC Manufacturer's Identification Code for Microchip Technology Inc. Fixed Value: Read as `1' DS61143A-page 472 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 25.1 Device Configuration 25.2 Device Code Protection In PIC32MX Family devices, the Configuration Words select various device configurations. These Configuration Words are implemented as volatile memory registers and must be loaded from the nonvolatile programmed configuration data mapped in the last four words (32-bit x 4 words) of boot Flash memory, DEVCFG0-DEVCFG3. These are the four locations an external programming device programs with the appropriate configuration data (see Table 25-3). The PIC32MX Family features a single device code protection bit, CP that when programmed = 0, protects boot Flash and program Flash from being read or modified by an external programming device. When code protection is enabled, only the Device ID and User ID registers are available to be read by an external programmer. Boot Flash and program Flash memory are not protected from self-programming during program execution when code protection is enabled. See Section 25.3 "Program Write Protection (PWP)". TABLE 25-3: DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG LOCATIONS Address 0xBFC0_2FFC 0xBFC0_2FF8 0xBFC0_2FF4 0xBFC0_2FF0 Configuration Word 25.3 Program Write Protection (PWP) In addition to a device code protection bit, the PIC32MX Family also features write protection bits to prevent boot Flash and program Flash memory regions from being written during code execution. Boot Flash memory is write protected with a single Configuration bit, BWP (DEVCFG0<24>), when programmed = 0. Program Flash memory can be write-protected entirely or in selectable page sizes using Configuration bits PWP<7:0> (DEVCFG0<19:12>). A page of Program Flash memory is 4096 bytes (1024 words). The PWP bits represent the one's complement of the number of protected pages. For example, programming PWP bits = 0xFF selects 0 pages to be write-protected, effectively disabling the program Flash write protection. Programming PWP bits = 0xFE selects the first page to be write protected. When enabled, the write-protected memory range is inclusive from the beginning of program Flash memory (0xBD00_0000) up through the selected page. Refer to Table 25-4. Note: The PWP bits represent the one's complement of the number of protected pages. On Power-on Reset (POR) or any Reset, the Configuration Words are copied from boot FLASH memory to their corresponding Configuration registers. A Configuration bit can only be programmed = 0 (unprogrammed state = 1). During programming, a Configuration Word can be programmed a maximum of two times before a page erase must be performed. After programming the Configuration Words, the user should reset the device to ensure the Configuration registers are reloaded with the new programmed data. 25.1.1 CONFIGURATION REGISTER PROTECTION To prevent inadvertent Configuration bit changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires changes to the configuration data in the boot Flash memory and power to the device be cycled. To ensure the 128-bit data integrity, a comparison is continuously made between each Configuration bit and its stored complement. If a mismatch is detected, a Configuration Mismatch Reset is generated, causing a device Reset. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 473 PIC32MX FAMILY TABLE 25-4: PWP Bit Value 0xFF 0xFE 0xFD 0xFC 0xFB 0xFA 0xF9 0xF8 0xF7 0xF6 0xF5 0xF4 0xF3 0xF2 0xF1 0xF0 0xEF 0x7F Note 1: FLASH PROGRAM MEMORY WRITE-PROTECT RANGES Range Size (Kbytes) 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 ... 512 0xBD07_FFFF Write Protected Memory Ranges(1) Disabled 0xBD00_0FFF 0xBD00_1FFF 0xBD00_2FFF 0xBD00_3FFF 0xBD00_4FFF 0xBD00_5FFF 0xBD00_6FFF 0xBD00_7FFF 0xBD00_8FFF 0xBD00_9FFF 0xBD00_AFFF 0xBD00_BFFF 0xBD00_CFFF 0xBD00_DFFF 0xBD00_EFFF 0xBD00_FFFF Write-protected memory range is inclusive from 0xBD00_0000. The amount of program Flash memory available for write protection depends on the family device variant. DS61143A-page 474 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 25.4 On-Chip Voltage Regulator FIGURE 25-1: All PIC32MX Family device's core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX Family incorporate an on-chip regulator providing the required core logic voltage from VDD. The internal 1.8V regulator is controlled by the ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low ESR capacitor (such as tantalum) must be connected to the VDDCORE/VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor is provided in Section 29.1 "DC Characteristics". Tying the ENVREG pin to VSS disables the regulator. In this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the VDDCORE/VCAP pin. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-1 for possible configurations. CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V PIC32MX VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) VSS Regulator Disabled (ENVREG tied to ground): 1.8V(1) 3.3V(1) PIC32MX VDD ENVREG VDDCORE/VCAP VSS 25.4.1 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up. Note 1: These are typical operating voltages. Refer to Section 29.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. 25.4.2 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC32MX Family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 29.1 "DC Characteristics". 25.4.3 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 475 PIC32MX FAMILY NOTES: DS61143A-page 476 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 26.0 Note: WATCHDOG TIMER This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. ting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. Refer to Figure 26-1. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle This section describes the operation of the Watchdog Timer (WDT) and Power-up Timer of the PIC32MX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by reset- TABLE 26-1: RESULTS OF A WDT TIME-OUT EVENT FOR AVAILABLE MODES OF DEVICE OPERATION Device Reset Generated Yes No No Non-Maskable Interrupt Generated No Yes Yes WDTO(1) Bit Set Yes Yes Yes SLEEP(1) Bit Set No Yes No IDLE(1) Bit Set No No Yes Device Registers Reset Yes No No Device Mode Awake Sleep Idle Note 1: Status bits are in the RCON register. FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable PWRT Enable LPRC Oscillator 1:64 Output LPRC Control PWRT 1 Clock WDTCLR = 1 WDT Enable Wake WDT Counter Reset 25-Bit Counter 25 0 1 Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0>(DEVCFG1<20:16>) (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 477 PIC32MX 26.1 Watchdog Timer Registers WDT SFR SUMMARY Name WDTCON 31:24 23:16 15:8 7:0 BF80_0004 WDTCONCLR BF80_0008 WDTCONSET BF80_000C WDTCONINV BF80_F600 RCON 31:0 31:0 31:0 31:24 23:16 15:8 7:0 BF80_F604 BF80_F608 BF80_F60C BFC0_2FF8 RCONCLR RCONSET RCONINV DEVCFG1 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- FWDTEN FCKSM1 IESO -- -- FCKSM0 -- -- -- TRAPR EXTR Bit 31/23/15/7 -- -- ON -- Bit 30/22/14/6 -- -- -- Bit 29/21/13/5 -- -- -- Bit 28/20/12/4 -- -- -- SWDTPS Bit 27/19/11/3 -- -- -- Bit 26/18/10/2 -- -- -- Bit 25/17/9/1 -- -- -- -- Bit 24/16/8/0 -- -- -- WDTCLR TABLE 26-2: Virtual Address BF80_0000 Write clears selected bits in WDTCON, Read yields an undefined value Write sets selected bits in WDTCON, Read yields an undefined value Write inverts selected bits in WDTCON, Read yields an undefined value -- -- -- SWR -- -- -- SWDTEN -- -- -- WDTO -- -- -- SLEEP -- -- -- IDLE -- -- CM BOR -- -- VREGS POR Write clears selected bits in RCON, Read yields an undefined value Write sets selected bits in RCON, Read yields an undefined value Write inverts selected bits in RCON, Read yields an undefined value -- -- FPBDIV1 FSOSCEN -- WDTPS4 FPBDIV0 -- -- WDTPS3 -- -- -- WDTPS2 OSCIOFNC FNOSC2 -- WDTPS1 POSCMD1 FNOSC1 -- WDTPS0 POSCMD0 FNOSC0 DS61143-page 478 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX REGISTER 26-1: U-0 -- bit 31 U-0 -- bit 23 R/W-0 ON bit 15 U-0 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-16 bit 15 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R-x R-x R-x SWDTPS R-x R-x r-0 -- U-0 -- U-0 -- U-0 -- U-0 -- r-1 -- r-1 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 r-0 -- bit 8 R/W-0 WDTCLR bit 0 Unimplemented: Read as `0' ON: Watchdog Timer Enable bit(1) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if is was enabled in software. Unimplemented: Read as `0' SWDTPS<4:0>: Shadow Copy of Watchdog Timer Post-Scaler Value from Device Configuration bits Reserved: Maintain as `0' WDTCLR: Watchdog Timer Reset bit 1 = Writing a `1' will reset the WDT. 0 = Software cannot force this bit to a `0'. A read of this bit will result in a `1' if the WDT is enabled by the device configuration or by software. bit 14-7 bit 6-2 bit 1 bit 0 Note 1: (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 479 PIC32MX Register 26-1: RCON: RESETS CONTROL REGISTER U-0 -- bit 31 U-0 -- bit 23 R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit U = Unimplemented bit bit 4 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 SWR R/W-0 SWDTEN R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-0 BOR U-0 -- U-0 -- U-0 -- U-0 -- R-0 -- R/W-0 CM U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 R/W-0 VREGS bit 8 R/W-0 POR bit 0 WDTO: Watchdog Time-Out bit 1 = A WDT time-out has occurred since the device was powered up 0 = A WDT time-out has not occurred since the WDTO bit was cleared by software SLEEP: Sleep Mode Status bit 1 = The device has been in Sleep mode since the device was powered up 0 = The device has not been in Sleep mode since the SLEEP bit was cleared by software IDLE: Idle Mode Status bit 1 = The device has been in Idle mode since the device was powered up 0 = The device has not been in Idle mode since the Idle bit was cleared by software bit 3 bit 2 DS61143-page 480 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX REGISTER 26-2: U-1 -- bit 31 R/P-1 FWDTEN bit 23 R/P-1 bit 15 R/P-1 IESO bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-24 bit 23 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-1 -- U-1 FSOSCEN U-1 -- U-1 -- R/P-1 R/P-1 FNOSC<2:0> bit 0 R/P-1 U-1 FPBDIV1 U-1 FPBDIV0 U-1 -- R/P-1 OSCIOFNC R/P-1 r-1 -- U-1 -- R/P-1 R/P-1 R/P-1 WDTPS<4:0> bit 16 R/P-1 bit 8 R/P-1 R/P-1 DEVCFG1: DEVICE CONFIGURATION WORD 1 U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 24 R/P-1 FCKSM<1:0> POSCMD<1:0> Reserved: Maintain as `1' FWDTEN: WatchDog Timer Hardware Enable bit. 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled. It can be enabled in software Reserved: Maintain as `1' WDTPS<4:0>: Watchdog Timer Postscaler Selection bits(1) These bits are used to set the WDT time-out period. 10100 = 1:1,045,876 10011 = 1:524,288 10010 = 1:262,144 10001 = 1:131,072 10000 = 1:65,536 01111 = 1:32,768 01110 = 1:16,384 01101 = 1:8,192 01100 = 1:4,096 01011 = 1:2,048 01010 = 1:1,024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All combinations not listed result in operation as if the selection was 10100 . Do not disable POSC (POSCMD = 00) when using this oscillator source. bit 22 bit 20-16 Note 1: 2: (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 481 PIC32MX bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Reserved: Maintain as `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock (EC) mode for the CLKO to be active (POSCMD<1:0> = 11 or 00) 0 = CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator is disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-Up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-Up disabled) Reserved: Maintain as `1' FSOSCEN: Secondary Oscillator Enable bits 1 = Enable secondary oscillator 0 = Disable secondary oscillator Reserved: Maintain as `1' FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV + PLL) 010 = Primary Oscillator (XT, HS, EC)(2) 011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)(2) 100 = Secondary Oscillator 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIVIG Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV) bit 13-12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 Note 1: 2: All combinations not listed result in operation as if the selection was 10100 . Do not disable POSC (POSCMD = 00) when using this oscillator source. DS61143-page 482 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 26.2 Watchdog Timer and Power-Up Timer Operation 26.2.5 WDT OPERATION IN POWER SAVE MODES The WDT, if enabled, will continue operation in Sleep or Idle modes. The WDT may be used to wake the device from Sleep or Idle. When the WDT times out in a Power Save mode, a Non-Maskable Interrupt (NMI) is generated and the WDTO (RCON<4>) bit is set. The NMI vectors execution to the CPU start-up address but does not reset registers or peripherals. If the device was in Sleep, the SLEEP (RCON<3>) status bit will also be set. If the device was in Idle, the IDLE (RCON<2>) status bit will also be set. These bits allow the start-up code to determine the cause of the wake-up. This describes the operation of the Watchdog Timer operation and the Power-up Timer 26.2.1 WATCHDOG TIMER OPERATION If enabled, the WDT will increment until it overflows or "times out". A WDT time-out will force a device Reset, except during Sleep or Idle modes. To prevent a WDT time-out Reset, the user must periodically clear the Watchdog Timer by setting the WDTCLR (WDTCON<0>) bit. The WDT uses the LPRC oscillator for reliability. Note: The LPRC is enabled whenever the WDT is enabled. 26.2.6 TIME DELAYS ON WAKE 26.2.2 ENABLING AND DISABLING THE WDT The WDT is enabled or disabled by the device configuration or controlled via software by writing to the WDTCON register. There will be a time delay between the WDT event in Sleep and the beginning of code execution. The duration of this delay consists of the Start-up time for the oscillator in use and the Power-up Timer delay, if it is enabled. Unlike a wake-up from Sleep mode, there are no time delays associated with wake-up from Idle mode. The system clock is running during Idle mode; therefore, no start-up delays are required at wake-up. 26.2.3 DEVICE CONFIGURATION CONTROLLED WDT If the FWDTEN Configuration bit is set, then the WDT is always enabled. The WDT ON control bit (WDTCON<15>) will reflect this by reading a `1'. In this mode, the ON bit cannot be cleared in software. This bit will not be cleared by any form of Reset. To disable the WDT in this mode, the configuration must be rewritten to the device. Note: The default state for the WDT on an unprogrammed device is WDT enabled. 26.2.7 RESETTING THE WDT TIMER The WDT is reset by any of the following: * On ANY device Reset * By a WDTCONSET = 0x01 or equivalent instruction during normal execution. * Execution of a DEBUG command * Exiting from Idle or Sleep due to an interrupt Note: The WDT timer is not reset when the device enters a Power Save mode. The WDT should be serviced prior to entering a Power Save mode. 26.2.4 SOFTWARE CONTROLLED WDT 26.2.8 If the FWDTEN Configuration bit is a `0', then the WDT can be enabled or disabled (the default condition) by software. In this mode, the ON (WDTCON<15>) bit reflects the status of the WDT under software control. A `1' indicates the WDT is enabled and a `0' indicates it is disabled. The WDT is enabled in software by setting the WDT ON control bit. The WDT ON control bit is cleared on any device Reset, The bit is not cleared upon a wake from Sleep or exit from Idle mode. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during noncritical segments for maximum power savings. This bit can also be used to disable the WDT while the part is awake to eliminate the need for WDT servicing, and then re-enable it before the device is put into Idle or Sleep to wake the part at a later time. WDT TIMER PERIOD SELECTION The WDT clock source is the internal LPRC oscillator, which has a nominal frequency of 32 kHz. This creates a nominal time-out period for the WDT (TWDT) of 1 millisecond when no postscaler is used. Note: The WDT time-out period is directly related to the frequency of the LPRC oscillator. The frequency of the LPRC oscillator will vary as a function of device operating voltage and temperature. Please refer to the specific PIC32MX device data sheet for LPRC clock frequency specifications. (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 483 PIC32MX 26.2.9 WDT POSTSCALERS The WDT has a 5-bit postscaler to create a wide variety of time-out periods. This postscaler provides 1:1 through 1: 1048576 divider ratios. Time-out periods that range between 1 ms and 1048.576 seconds (nominal) can be achieved using the postscaler. The postscaler settings are selected using the WDTPS bits in the DEVCFG1 Configuration register. The timeout period of the WDT is calculated as follows: EQUATION 26-1: WDT TIME-OUT PERIOD CALCULATIONS WDT Period = 1 ms * 2 Prescaler TABLE 26-3: FWDTPS<4:0> WDT TIME-OUT PERIOD VS. POSTSCALER SETTINGS Postscaler Ratio Time-out Period 00000 1:1 1 ms 00001 1:2 2 ms 00010 1:4 4 ms 00011 1:8 8 ms 00100 1:16 16 ms 00101 1:32 32 ms 00110 1:64 64 ms 00111 1:128 128 ms 01000 1:256 256 ms 01001 1:512 512 ms 01010 1:1024 1.024 s 01011 1:2048 2.048 s 01100 1:4096 4.096 s 01101 1:8192 8.192 s 01110 1:16384 16.384 s 01111 1:32768 32.768 s 10000 1:65536 65.536 s 10001 1:131072 131.072 s 10010 1:262144 262.144 s 10011 1:524288 524.288 s 10100 1:1045876 1048.576 s Note 1: All other combinations will result in an operation as if the prescaler was set to 10100. 2: The periods listed are based on a 32 kHz (nominal) input clock. DS61143-page 484 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX 26.3 Interrupts and Resets 26.3.2 WATCHDOG TIMER NMI When the WDT expires in Sleep or Idle, a NMI is generated. The NMI causes the CPU code execution to jump to the device Reset vector. Though the NMI share the same vector as a device Reset, registers and peripherals are not reset. To detect a wake from a Power Save mode by WDT, the WDTO (RCON<4>), SLEEP (RCON<3>) and IDLE (WDTCON<2>) bits must be tested. If the WDTO bit is a `1' the event was caused by a WDT time-out. The SLEEP and IDLE bits can then be tested to determine if the WDT event occurred in Sleep or Idle. To cause a WDT time-out in Sleep to act like an interrupt, a return from interrupt instruction may be used in the start-up code after the event was determined to be a WDT wake-up. This will cause code execution to continue with the opcode following the WAIT instruction that put the device into Power Save mode. See Example 26-1. The WDT will cause an NMI or a device Reset when it expires. The Power Save mode of the device determines which event occurs. The PWRT does not generate interrupts or Resets. 26.3.1 WATCHDOG TIMER RESET When the WDT expires and the device is not in Sleep or Idle, a device Reset is generated. The CPU code execution jumps to the device Reset vector and the Registers and Peripherals are forced to their Reset values. To detect a WDT Reset, the WDTO (RCON<4>), SLEEP (RCON<3>) and IDLE (WDTCON<2>) bits must be tested. If the WDTO bit is a `1', the event was do to a WDT time-out. The SLEEP and IDLE bits can then be tested to determine if the WDT event occurred while the device was awake or if it was in Sleep or Idle. EXAMPLE 26-1: SAMPLE WDT INITIALIZATION AND SERVICING //This code fragment assumes the WDT was not enabled by the device configuration // The Postscaler value must be set with the device configuration WDTCONSET = 0x8000;// Turn on the WDT main { WDTCONSET = 0x01;// Service the WDT ... User code goes here ... } (c) 2007 Microchip Technology Inc. Advance Information DS61143-page 485 PIC32MX EXAMPLE 26-2: SAMPLE CODE TO DETERMINE THE CAUSE OF A WDT EVENT // sample code to determine the cause of a WDT event // Unlock the OSCCON register asm ("la $t3, SYSREG");//load the address of SYSREG into t3 asm ("li $t0,0xaa996655");// load Key value into t0 asm ("nor $t1, $0, $t0");// complement Key1 to form Key2 // the following writes must be performed back to back asm ("sw $t0, 0($t3)" ); //write Key1 to SYSREG asm ("sw $t1, 0($t3)"); //write Key2 to SYSREG // OSCCON is now unlocked OSCCONSET = 0x10;// set power save mode to Sleep // Alternate relock code in `C' SYSREG = 0x33333333; // OSCCON is relocked WDTCONSET = 0x8000;//Enable WDT while (1) { ... user code ... WDTCONSET = 0x01;// service the WDT asm ( "wait" );// put device is selected power save mode // code execution will resume here after wake ... user code ... } // The following code fragment is at the top of the device start-up code if ( RCON & 0x18 ) { // The WDT caused a wake from sleep asm ( "eret" );// return from interrupt } if ( RCON & 0x14 ) { // The WDT caused a wake from idle asm ( "eret" );// return from interrupt } if ( RCON & 0x10 ) { // The WDT timed-out while the device was awake } DS61143-page 486 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 27.0 Note: PROGRAMMING AND DIAGNOSTICS This data sheet summarizes the features of the PIC32MX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for a detailed description of this peripheral. * Simplified field programmability using two-wire In-Circuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32MX Family devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. They are summarized in Table 27-1. PIC32MX Family devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: FIGURE 27-1: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS PGC1 PGD1 ICSPTM Controller PGC2 PGD2 ICESEL TDI TDO TCK TMS JTAGEN TRCLK TRD0 TRD1 TRD2 TRD3 DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> JTAG Controller Core TABLE 27-1: COMPARISON OF PIC32MX FAMILY PROGRAMMING AND DIAGNOSTIC FEATURES Pins Used TDI, TDO, TMS and TCK pins TDI, TDO, TMS and TCK pins PGCx and PGDx pins Interface JTAG EJTAG ICSPTM Functions Boundary Scan Programming and Debugging Programming and Debugging (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 487 PIC32MX FAMILY 27.1 Control Registers The programming and diagnostics module consists of the following Special Function Registers (SFRs): * DDPCON: Control Register for the Diagnostic Module DDPCONCLR, DDPCONSET, DDPCONINV: Atomic Bit Manipulation Write-Only Registers for DDPCON * DEVCFG0: Device Configuration Register The following table summarizes all programming and diagnostics related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. TABLE 27-2: Virtual Address BF80_F200 PROGRAMMING AND DIAGNOSTICS SFR SUMMARY Name Bit 31/23/15/7 31:24 23:16 15:8 7:0 -- -- -- -- Bit 30/22/14/6 -- -- -- DDPU1 Bit 29/21/13/5 -- -- -- DDPU2 Bit 28/20/12/4 -- -- -- DDPSPI1 Bit 27/19/11/3 -- -- -- JTAGEN Bit 26/18/10/2 -- -- -- TROEN Bit 25/17/9/1 -- -- -- -- Bit 24/16/8/0 -- -- -- -- DDPCON BF80_F204 BF80_F208 BF80_F20C DDPCONCLR DDPCONSET DDPCONINV 31:0 31:0 31:0 31:24 23:16 15:8 7:0 -- -- PWP3 -- -- -- Write clears selected bits in DDPCON, read yields undefined value Write sets selected bits in DDPCON, read yields undefined value Write inverts selected bits in DDPCON, read yields undefined value -- -- PWP1 -- CP -- PWP0 -- -- PWP7 -- ICESEL -- PWP6 -- -- -- PWP5 -- DEBUG1 BWP PWP4 -- DEBUG0 BFC0_2FFC DEVCFG0 PWP2 -- DS61143A-page 488 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY REGISTER 27-1: U-0 -- bit 31 U-0 -- bit 23 U-0 -- bit 15 U-r -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 31-8 bit 7 bit 6 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) R/W-0 DDPU1 R/W-0 DDPU2 R/W-0 DDPSPI1 R/W-1 JTAGEN R/W-1 TROEN U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DDPCON: DEBUG DATA PORT CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 24 U-0 -- bit 16 U-0 -- bit 8 Unimplemented: Read as `0' Reserved: Maintain as `0' DDPU1: Debug Data Port Enable for UART1 bit 1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting 0 = UART1 peripheral follows FRZ setting DDPU2: Debug Data Port Enable for UART2 bit 1 = UART2 peripheral ignores FRZ (U2MODE<14) setting 0 = UART2 peripheral follows FRZ setting DDPSPI1: Debug Data Port Enable for SPI1 bit 1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting 0 = SPI1 peripheral follows FRZ setting JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port Unimplemented: Read as `0' bit 5 bit 4 bit 3 bit 2 bit 1-0 (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 489 PIC32MX FAMILY REGISTER 27-2: r-1 -- bit 31 U-1 -- bit 23 R/P-1 PWP3 bit 15 U-1 -- bit 7 Legend: R = Readable bit U = Unimplemented bit bit 3 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) U-1 -- U-1 -- U-1 -- R/P-1 ICESEL U-1 -- R/P-1 DEBUG1 R/P-1 PWP2 R/P-1 PWP1 R/P-1 PWP0 U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- R/P-1 PWP7 R/P-1 PWP6 R/P-1 PWP5 DEVCFG0: DEVICE CONFIGURATION REGISTER U-1 -- U-1 -- R/P-1 CP U-1 -- U-1 -- U-1 -- R/P-1 BWP bit 24 R/P-1 PWP4 bit 16 U-1 -- bit 8 R/P-1 DEBUG0 bit 0 ICESEL: ICE Debugger Port Select bit 1 = ICE debugger uses PGC2/PGD2 0 = ICE debugger uses PGC1/PGD1 DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = ICE debugger disabled 10 = ICE debugger enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting) bit 1-0 DS61143A-page 490 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 27.2 Operation FIGURE 27-2: The PIC32MX Family of devices has multiple programming and Debugging options including: * * * * * In-Circuit Serial Programming via ICSP In-Circuit Programming EJTAG Debugging via ICSP Debugging via EJTAG Special Debug modes for Select Communication Peripherals * Boundary Scan TYPICAL IN-CIRCUIT SERIAL PROGRAMMINGTM CONNECTION ICSPTM VSS VDD VPP CLK Data I/O PIC32MX VSS VDD MCLR/VPP PGCx PGDx 27.2.1 Note: DEVICE PROGRAMMING OPTIONS The following sections provide a brief overview of each programming option. For more detailed information, refer to "PIC32MX Flash Programming Specification" (DS61145). 27.2.1.1 In-Circuit Serial Programming 27.2.1.3 ICSP Operation ICSP is Microchip's proprietary solution to providing microcontroller programming in the target application. ICSP is also the most direct method to program the device, whether the controller is embedded in a system or loaded into a device programmer. 27.2.1.2 ICSP Interface ICSP uses two pins as the core of its interface. The Programming Data (PGD) line functions as both an input and an output, allowing programming data to be read in and device information to be read out on command. The Programming Clock (PGC) line is used to clock in data and control the overall process. PIC32MX Family devices have more than one pair of PGC and PGD pins; these are multiplexed with other I/O or peripheral functions. Individual ICSP pin pairs are indicated by number (e.g., PGC1/PGD1, etc.), and are generically referred to as `PGCx' and `PGDx'. The multiple PGCx/PGDx pairs provide additional flexibility in system design by allowing users to incorporate ICSP on the pair of pins that is least constrained by the circuit design. All PGCx and PGDx pins are functionally tied together and behave identically, and any one pair can be used for successful device programming. The only limitation is that both pins from the same pair must be used. In addition to the PGCx and PGDx pins, ICSP requires that all voltage supply (including voltage regulator pin ENVREG) and ground pins on the device must be connected. The MCLR pin, which is used with PGCx to enter and control the programming process, must also be connected to the programmer. A typical In-Circuit Serial Programming connection is shown in Figure 27-2. ICSP uses a combination of internal hardware and external control to program the target device. Programming data and instructions are provided on PGD. ICSP uses a special set of commands to control the overall process, combined with standard PIC32MX Family instructions to execute the actual writing of the program memory. PGD also returns data to the external programmer when responding to queries. Users who are interested in a more detailed description, or who are considering designing their own programming interface for PIC32MX Family devices, should consult the appropriate PIC32MX Family device programming specification. 27.2.1.4 Enhanced In-Circuit Serial Programming The Enhanced In-Circuit Serial Programming (ICSP) protocol is an extension of the original ICSP. It uses the same physical interface as the original, but changes the location and execution of programming control to a software application written to the PIC32MX Family device. Use of Enhanced ICSP results in significant decrease in overall programming time. For additional information on Enhanced ICSP and the program executive, refer to the appropriate PIC32MX Family device programming specification. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 491 PIC32MX FAMILY 27.2.1.5 EJTAG Device Programming Using the JTAG Interface The JTAG interface can also be used to program PIC32MX Family devices in their target applications. Using EJTAG with the JTAG interface allows application designers to include a dedicated test and programming port into their applications, with a single 4-pin interface, without imposing the circuit constraints that the ICSP interface may require. The external device also provides common clock and control signals. Depending on the implementation, access to all test signals is provided through a standardized, 4-pin interface. A typical application incorporating the JTAG boundary scan interface is shown in Figure 27-3. In this example, a PIC32MX Family microcontroller is daisy-chained to a second JTAG compliant device. Note that the TDI line from the external tester supplies data to the TDI pin of the first device in the chain (in this case, the microcontroller). The resulting test data for this two-device chain is provided from the TDO pin of the second device to the TDO line of the tester. This section describes the JTAG module and its general use. Users interested in using the JTAG interface for device programming should refer to the appropriate PIC32MX Family device programming specification for more information. 27.2.1.6 Enhanced EJTAG Programming Using the JTAG Interface Enhanced EJTAG programming uses the standard JTAG interface but uses a programming executive written to RAM. Use of the programming executive with the JTAG interface provides a significant improvement in programming speed. 27.2.2 27.2.2.1 DEBUGGING ICSP and In-Circuit Debugging ICSP also provides a hardware channel for the In-Circuit Debugger (ICD) which allows externally controlled debugging of software. Using the appropriate hardware interface and software environment, users can force the device to single step through its code, track the actual content of multiple registers and set software breakpoints. The active ICSP debugger port is selected by the ICS Configuration bit. 27.2.2.2 EJTAG Debugging The industry standard EJTAG interface allows third party EJTAG tools to be used for debugging. Using the EJTAG interface, memory and registers can be viewed and modified. Breakpoints can be set and the program execution may be stopped, started or single stepped. 27.2.3 SPECIAL DEBUG MODES FOR SELECT COMMUNICATIONS PERIPHERALS To aid in debugging applications certain I/O peripherals have a user-controllable bit to override the Freeze function in the peripheral. This allows the module to continue to send any data, buffered within the peripheral, even when a debugger attempts to halt the peripheral. The Debug mode control bits for these peripherals are contained in the DDPCON register. 27.2.4 JTAG BOUNDARY SCAN The JTAG boundary scan method is the process of adding a Shift register stage adjacent to each of the component's I/O pins. This permits signals at the component boundaries to be controlled and observed, using a defined set of scan test principles. An external tester or controller provides instructions and reads the results in a serial fashion. DS61143A-page 492 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 27-3: OVERVIEW OF PIC32MX FAMILY-BASED JTAG COMPLIANT APPLICATION SHOWING DAISY-CHAINING OF COMPONENTS PIC32MX Device-Based Application PIC32MX PIC32MX (or other JTAG compliant device) TDO TMS TCK TDO JTAG Controller JTAG Connector TDI TDO TCK TMS In PIC32MX Family devices, the hardware for the JTAG boundary scan is implemented as a peripheral module (i.e., outside of the CPU core) with additional integrated logic in all I/O ports. A logical block diagram of the JTAG module is shown in Figure 27-1. It consists of the following key elements: * TAP Interface Pins (TDI, TMS, TCK and TDO) * TAP Controller * Instruction Shift register and Instruction Register (IR) * Data Registers (DR) The PIC32MX Family implements a 4-pin JTAG interface with these pins: * TCK (Test Clock Input): Provides the clock for test logic. * TMS (Test Mode Select Input): Used by the TAP to control test operations. * TDI (Test Data Input): Serial input for test instructions and data. * TDO (Test Data Output): Serial output for test instructions and data. 27.2.4.1 Test Access Port (TAP) and TAP Controller 27.2.4.2 JTAG Registers The Test Access Port (TAP) on the PIC32MX Family device is a general purpose port that provides test access to many built-in support functions and test logic defined in IEEE 1149.1. The TAP is enabled by the JTAGEN bit in the DDPCON register. The TAP is enabled, JTAGEN = 1, by default when the device exits Power-on-Reset (POR) or any device Reset. Once enabled, the designated I/O pins become dedicated TAP pins. The JTAG module uses a number of registers of various sizes as part of its operation. In terms of bit count, most of the JTAG registers are single bit register cells, integrated into the I/O ports. Regardless of their location within the module, none of the JTAG registers are located within the device data memory space, and cannot be directly accessed by the user in normal operating modes. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 493 TMS TCK TDI TDI PIC32MX FAMILY 27.2.4.3 Instruction Shift Register and Instruction Register 27.2.4.5 Boundary Scan Register (BSR) The Instruction Shift register is a 4-bit Shift register used for selecting the actions to be performed and/or what data registers to be accessed. Instructions are shifted in, Least Significant bit first, and then decoded. A list and description of implemented instructions is given in Section 27.2.4.6 "JTAG Instructions". The BSR is a large Shift register that is comprised of all the I/O Boundary Scan Cells (BSCs), daisy-chained together. Each I/O pin has one BSC, each containing 3 BSC registers, an input cell, an output cell and a control cell. When the SAMPLE/PRELOAD or EXTEST instructions are active, the BSR is placed between the TDI and TDO pins, with the TDI pin as the input and the TDO pin as the output. The size of the BSR depends on the number of I/O pins on the device. For example, the 100-pin PIC32MX general purpose parts have 82 I/O pins. With 3 BSC registers for each of the 82 I/Os, this yields a Boundary Scan register length of 244 bits. This is due to the MCLR pin being an input only BSR cell. Information on the I/O port pin count of other PIC32MX Family devices can be found in their specific device data sheets. 27.2.4.4 Data Registers Once an instruction is shifted in and updated into the Instruction Register, the TAP controller places certain data registers between the TDI and TDO pins. Additional data values can then be shifted into these data registers as needed. The PIC32MX Family device supports three data registers: * BYPASS Register: A single bit register which allows the boundary scan test data to pass through the selected device to adjacent devices. The BYPASS register is placed between the TDI and TDO pins when the BYPASS instruction is active. * DEVID Register: A 32-bit part identifier. It consists of an 11-bit manufacturer ID assigned by the IEEE (29h for Microchip Technology), device part number and device revision identifier. When the IDCODE instruction is active, the device ID register is placed between the TDI and TDO pins. The device data ID is then shifted out on to the TDO pin, on the next 32 falling edges of TCK, after the TAP controller is in the Shift_DR. * MCHP Command Shift Register: An 8-bit Shift register that is placed between the TDI and TDO pins when the MCHP_CMD instruction is active. This Shift register is used to shift in Microchip commands. 27.2.4.6 JTAG Instructions PIC32MX Family devices support the mandatory instruction set specified by IEEE 1149.1, as well as several optional public instructions defined in the specification. These devices also implement instructions that are specific to Microchip devices. The mandatory JTAG instructions are: * BYPASS (0x1F): Used for bypassing a device in a test chain; this allows the testing of off-chip circuitry and board level interconnections. * SAMPLE/PRELOAD (0x02): Captures the I/O states of the component, providing a snapshot of its operation. * EXTEST (0x06): Allows the external circuitry and interconnections to be tested, by either forcing various test patterns on the output pins, or capturing test results from the input pins. Microchip has implemented optional JTAG instructions and manufacturer-specific JTAG commands in PIC32MX Family devices. Please refer to Table 27-3, Table 27-4, Table 27-5 and Table 27-6. TABLE 27-3: Opcode 0x1F 0x00 0x01 0x02 0x06 JTAG COMMANDS Name Device Integration Bypasses device in test chain Places device in a high-impedance state, all pins are forced to inputs Shifts out the device's ID code Samples all pins or loads a specific value into output latch Boundry scan Bypass HIGHZ ID Code Sample/Preload EXTEST TABLE 27-4: Opcode 0x01 0x07 0x04 MICROCHIP TAP IR COMMANDS Name Device Integration Shifts out the device's ID code Configures Microchip TAP controller for DR commands Selects Microchip TAP controller MTAP_IDCODE MTAP_COMMAND MTAP_SW_MTAP DS61143A-page 494 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY Opcode 0x05 Name MTAP_SW_ETAP Selects EJTAG TAP controller Device Integration TABLE 27-5: Opcode 0x00 0xD1 0xD0 0xFC 0xFE 0xFD 0xFF MICROCHIP TAP 8-BIT DR COMMANDS Name Device Integration Performs NOP and returns status Requests Assert Device Reset Performs a chip erase Enables fetches and loads to the Flash from the CPU Disables fetches and loads to the Flash from the CPU Forces device to reread the configuration settings and initialize accordingly MCHP_STATUS MCHP_ASERT_RST MCHP_ERASE MCHP_FLASH_ENABLE MCHP_FLASH_DISABLE MCHP_READ_CONFIG MCHP_DE_ASSERT_RST Requests Deassert Device Reset TABLE 27-6: Opcode 0x00 0x01 0x02 0x03 0x04(2) 0x05(2) 0x06-0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F-0x1B 0x1C-0xFE 0xFF Note 1: 2: EJTAG COMMANDS Name Not used Device Integration Data Length for the Following DR 32 bits IDCODE IMPCODE MTAP_SW_ETAP ADDRESS DATA CONTROL ALL EJTAGBOOT NORMALBOOT FASTDATA Selects the device's ID Code register Not used Selects Implementation register Selects EJTAG TAP controller(1) Not used Selects the Address register Selects the Data register Selects the EJTAG Control register(1) Selects the Address, Data, EJTAG Control register(1) Forces the CPU to take a debug exception after boot Makes the CPU execute the reset handler after a boot Selects the Data and Fast Data registers Reserved Not used Selects the Bypass register MTAP_SW_MTAP Selects Microchip TAP controller 32 bits 32 bits 32 bits 96 bits 1 bit 1 bit 1 bit For complete information about EJTAG commands and protocol, refer to the EJTAG Specification available on MIPS Technologies web site, www.mips.com. Not EJTAG commands but are recognized by the Microchip implementation. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 495 PIC32MX FAMILY 27.2.5 BOUNDARY SCAN TESTING (BST) 27.3 Interrupts Boundary Scan Testing (BST) is the method of controlling and observing the boundary pins of the JTAG compliant device, like those of the PIC32MX Family, utilizing software control. BST can be used to test connectivity between devices by daisy-chaining JTAG compliant devices to form a single scan chain. Several scan chains can exist on a PCB to form multiple scan chains. These multiple scan chains can then be driven simultaneously to test many components in parallel. Scan chains can contain both JTAG compliant devices and non-JTAG compliant devices. A key advantage of BST is that it can be implemented without physical test probes; all that is needed is a 4-wire interface and an appropriate test platform. Since JTAG boundary scan has been available for many years, many software tools exist for testing scan chains without the need for extensive physical probing. The main drawback to BST is that it can only evaluate digital signals and circuit continuity; it cannot measure input or output voltage levels or currents. Programming and debugging operations are not performed during code execution and are therefore not affected by interrupts. Trace operations will report the change in code execution when a interrupt occurs but the trace controller is not affected by interrupts. 27.4 I/O Pins In order to interface the numerous programming and debugging option available and still provide peripheral access to the pins, the pins are multiplexed with peripherals. Table 27-7 describes the function of the programming and debug related pins. 27.2.5.1 Related JTAG Files To implement BST, all JTAG test tools will require a Boundary Scan Description Language (BSDL) file. BSDL is a subset of VHDL (VHSIC Hardware Description Language), and is described as part of IEEE. 1149.1. The device-specific BSDL file describes how the standard is implemented on a particular device and how it operates. The BSDL file for a particular device includes the following: * The pinout and package configuration for the particular device * The physical location of the TAP pins * The Device ID register and the device ID * The length of the Instruction Register * The supported BST instructions and their binary codes * The length and structure of the Boundary Scan register * The boundary scan cell definition Device-specific BSDL files are available at Microchip's web site, www.microchip.com. The name for each BSDL file is the device name and silicon revision-for example, PIC32MX Family 320F128L_A2.BSD is the BSDL file for PIC32MX Family 320F128L, silicon revision A2. DS61143A-page 496 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 27-7: Pin Name MCLR PGC1 PGD1 PGC2 PROGRAMMING AND DEBUGGING PIN FUNCTIONS Function Debug Mode MCLR Trace Mode MCLR Boundary Scan Mode MCLR Alternate Alternate Alternate Program Mode MCLR Description Master Clear, used to enter ICSPTM mode and to override JTAGEN (DDPCON<3>) ICSP clock, determined by ICESEL Configuration bit (DEVCFG0<3>) ICSP data, determined by ICESEL (DEVCFG0<3>) and DEBUG Configuration bits (DEVCFG0<1:0>) Alternate ICSP clock, determined by ICESEL (DEVCFG0<3>) and DEBUG Configuration bits (DEVCFG0<1:0>) Alternate ICSP data, determined by ICESEL (DEVCFG0<3>) and DEBUG Configuration bits (DEVCFG0<1:0>) JTAG clock, determined by JTAGEN control bit (DDPCON<3>) JTAG data out, determined by JTAGEN control bit (DDPCON<3>) JTAG data in, determined by JTAGEN control bit (DDPCON<3>) JTAG test mode select, determined by JTAGEN control bit (DDPCON<3>) Trace clock, determined by TROEN control bit (DDPCON<2>) Trace data, determined by TROEN control bit (DDPCON<2>) Trace data, determined by TROEN control bit (DDPCON<2>) Trace data, determined by TROEN control bit (DDPCON<2>) Trace data, determined by TROEN control bit (DDPCON<2>) PGC1/ PGC1/ PGC1/ Alternate Alternate Alternate PGD1/ PGD1/ PGD1/ Alternate Alternate Alternate PGC2/ PGC2/ PGC2/ Alternate Alternate Alternate PGD2/ PGD2/ PGD2/ Alternate Alternate Alternate TCK TDO TDI TMS TCK TDO TDI TMS TCK TDO TDI TMS TRCLK TRD0 TRD1 TRD2 TRD3 PGD2 Alternate TCK TDO TDI TMS Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate TRCLK Alternate Alternate TRD0 TRD1 TRD2 TRD3 Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 497 PIC32MX FAMILY NOTES: DS61143A-page 498 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 28.0 DEVELOPMENT SUPPORT 28.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 499 PIC32MX FAMILY 28.2 MPASM Assembler 28.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 28.6 MPLAB SIM Software Simulator 28.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 28.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS61143A-page 500 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 28.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 28.9 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 28.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 28.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 501 PIC32MX FAMILY 28.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 28.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 28.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS61143A-page 502 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC32MX Family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX Family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +5.5V Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V Maximum current out of VSS pin ..........................................................................................................................TBD mA Maximum current into VDD pin (Note 2)...............................................................................................................TBD mA Maximum output current sunk by any I/O pin (Note 3) ........................................................................................TBD mA Maximum output current sourced by any I/O pin (Note 3) ...................................................................................TBD mA Maximum current sunk by all ports ......................................................................................................................TBD mA Maximum current sourced by all ports (Note 2)...................................................................................................TBD mA Legend: TBD = To Be Determined Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGCx and PGDx pins, which are able to sink/source 12 mA. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 503 PIC32MX FAMILY 29.1 DC Characteristics OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) 2.5-3.6V Temp Range (in C) -40C to +85C Max Frequency PIC32MX Family 72 MHz(1) TABLE 29-1: Characteristic DC5 Note 1: 20 MHz maximum for PIC32MX300 family variants. TABLE 29-2: PIC32MX Family THERMAL OPERATING CONDITIONS Rating Symbol TJ TA Min -40 -40 Typ -- -- Max +125 +85 Unit C C Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S ({VDD - VOH} x IOH) + S (VOL x IOL) ) Maximum Allowed Power Dissipation PD PINT + PI/O W PDMAX (TJ - TA)/JA W TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ 52.3 38.3 Max -- -- Unit C/W C/W Notes 1 1 Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) Note 1: JA JA Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 DC12 DC16 Supply Voltage VDD VDR VPOR RAM Data Retention Voltage VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal (2) 2.5 -- -- -- TBD VSS 3.6 -- -- V V V DC17 SVDD 0.05 -- -- V/ms Legend: TBD = To Be Determined Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: This is the limit to which VDD can be lowered without losing RAM data. DS61143A -page 504 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)(1) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC21 DC21a DC21b DC22 DC22a DC22b DC23 DC23a DC23b DC24 DC24a DC24b DC25 DC25a DC25b DC26 DC26a DC26b Typical(2) Operating Current (IDD)(3) -- 11 -- -- 25 -- -- 56 -- -- 64 -- -- -- -- TBD 230 TBD -- -- -- TBD -- TBD TBD -- TBD TBD -- TBD TBD -- TBD TBD TBD TBD -- -- -- TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.6V 3.3V LPRC (31 kHz) 2.5V 2.5V -- 3.6V 2.5V -- 3.6V 2.5V -- 3.6V 2.5V -- 3.6V 72 MHz 60 MHz 20 MHz 4 MHz Legend: TBD = To Be Determined Note 1: A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 2: Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, SRAM, program memory and data memory are operational with CPU Wait states disabled, Flash memory Wait states = 7 and program cache disabled. Only digital peripheral modules are enabled (ON bit = 1) and being clocked; however, not accessed. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 505 PIC32MX FAMILY TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC30 DC30a DC30b DC31 DC31a DC31b DC32 DC32a DC32b DC33 DC33a DC33b DC34 DC34a DC34b DC35 DC35a DC35b DC36 DC36a DC36b Typical(1) Idle Current (IIDLE): Core OFF Clock ON Base Current(2) -- 3 -- -- 11 -- -- 31 -- -- 36 -- -- -- -- TBD 200 TBD -- -- -- TBD -- TBD TBD -- TBD TBD -- TBD TBD -- TBD TBD TBD TBD -- -- -- TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.6V 3.3V LPRC (31 kHz) 2.5V 2.5V -- 3.6V 2.5V -- 3.6V 2.5V -- 3.6V 2.5V -- 3.6V 72 MHz 60 MHz 40 MHz 4 MHz Legend: TBD = To Be Determined Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The test conditions for base IIDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in IDLE mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. DS61143A -page 506 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40c DC40d DC40e DC40f DC41 DC41a DC41b DC41c DC41d DC41e DC41f DC42 DC42a DC42b DC42c DC42e DC42f DC42g DC42 DC42a DC42b DC42c DC42e DC42f DC42g Typical(1) Power-Down Current (IPD)(2) -- -- -- 50 -- -- -- -- -- -- 10 -- -- -- -- -- -- 22.5 -- -- -- -- -- -- 880 -- -- -- TBD TBD TBD -- TBD TBD TBD TBD TBD TBD -- TBD TBD TBD TBD TBD TBD -- TBD TBD TBD TBD TBD TBD -- TBD TBD TBD A A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C +25C +85C 3.6V -40C +25C +85C -40C +25C +85C ADC: IADC(3,5) 2.5V 3.6V -40C +25C +85C -40C +25C +85C RTCC + Timer1: IRTCC(3,4) 2.5V 3.6V -40C +25C +85C -40C +25C +85C Watchdog Timer Current: IWDT(3) 2.5V 3.6V -40C +25C +85C Base Power-Down Current 2.5V Module Differential Current Legend: TBD = To Be Determined Note 1: Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals (ON bit = 0) and clocks shut down. All I/Os are configured as outputs and pulled low. WDT, etc., are turned off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for RTCC module differential current are as follows: Timer1 is enabled (T1CON.ON bit = 1), secondary oscillator is enabled (OSCCON.SLPEN = 1), pin SOSCI is driven by external square wave from rail to rail. 5: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 507 PIC32MX FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 Sym VIL Characteristic Input Low Voltage I/O pins: with TTL Buffer with Schmitt Trigger Buffer DI15 DI16 DI17 DI18 DI19 VIH DI20 MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx Input High Voltage I/O pins: with Analog Functions Digital Only with TTL Buffer with Schmitt Trigger Buffer DI25 DI26 DI27 DI28 DI29 DI30 DI50 DI51 DI55 DI56 Note 1: 2: MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx ICNPU CNxx Pull up Current IIL Input Leakage Current(2,3) I/O Ports Analog Input Pins MCLR OSC1 VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 VSS VSS V V V V V SMBus disabled SMBus enabled 0.8 VDD 0.8 VDD 0.25VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 50 -- -- -- -- -- -- -- -- -- -- -- -- -- 250 -- -- -- -- VDD 5.5 5.5 VDD VDD VDD VDD VDD 400 +1 +1 +1 +1 V V VSS VSS V V V V V A A A A A SMBus disabled SMBus enabled, 2.5V VPIN VDD VDD = 3.3V, VPIN = VSS VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes 3: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. DS61143A -page 508 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 DO26 Sym VOL Characteristic Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports OSC2/CLKO 2.4 1.4 2.4 1.4 -- -- -- -- -- -- -- -- V V V V IOH = -15 mA, VDD = 3.6V IOH = -TBD mA, VDD = 2.5V IOH = -TBD mA, VDD = 3.6V IOH = -TBD mA, VDD = 2.5V -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 V V V V IOL = 9 mA, VDD = 3.6V IOL = TBD mA, VDD = 2.5V IOL = TBD mA, VDD = 3.6V IOL = TBD mA, VDD = 2.5V Legend: TBD = To Be Determined Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-10: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. D130 D131 D132B D134 D135 EP VPR VPEW TRETD IDDP TWW D136 D137 TRW TPE TCE Characteristic Program Flash Memory Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time (128 words per row) Page Erase Cycle Time Chip Erase Cycle Time 1000 VMIN 3.0 20 -- 20 3 20 20 -- -- -- -- 10 -- TBD -- -- -- 3.6 3.6 -- -- 40 -- 40 40 E/W -40C to +85C V V Year Provided no other specifications are violated mA s ms ms ms VMIN = Minimum operating voltage Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions Legend: TBD = To Be Determined Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 509 PIC32MX FAMILY TABLE 29-11: COMPARATOR SPECIFICATIONS Operating Conditions: 2.5V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. D300 D301 D302 300 301 * Note 1: Sym VIOFF VICM CMRR TRESP TMC2OV Characteristics Input Offset Voltage Input Common Mode Voltage* Common Mode Rejection Ratio* Response Time*(1) Comparator Mode Change to Output Valid* Min -- 0 55 -- -- Typ 7.5 -- -- 150 -- Max 15 VDD -- 400 10 Units mV V dB ns s Comments These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-12: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 2.5V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. D310 D311 D312 310 Sym VRES VRAA VROZ TSET Characteristics Resolution Absolute Accuracy Output Impedance Settling Time(1) Min VDD/24 -- -- -- Typ -- -- TBD -- Max VDD/32 1/2 -- 10 Units LSb LSb s Comments Legend: TBD = To Be Determined Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. TABLE 29-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param No. Symbol VRGOUT CEFC TPWRT Legend: TBD = To Be Determined Characteristics Regulator Output Voltage External Filter Capacitor Value Min 1.62 TBD -- Typ 1.80 10 64 Max 1.98 -- -- Units V F ms Capacitor must be low series resistance ENVREG = 0 Comments DS61143A -page 510 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX Family AC characteristics and timing parameters. TABLE 29-14: AC CHARACTERISTICS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 29.0 "Electrical Characteristics". AC CHARACTERISTICS FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSC2 Load Condition 1 - for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 29-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSC2/SOSC2 pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1 EC mode In I2CTM mode DO56 DO58 Note 1: CIO CB All I/O pins and OSC2 SCLx, SDAx -- -- -- -- 50 400 pF pF Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 511 PIC32MX FAMILY FIGURE 29-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31 TABLE 29-16: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OS10 Symb FOSC Characteristic External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min DC 4 3 4 10 10 32 -- Typ(1) -- -- -- -- -- -- 32.768 -- Max 50(3) 50 10 1 40(3) 40(3) 100 -- Units MHz MHz MHz MHz MHz MHz kHz -- Conditions EC ECPLL(4) XT XTPLL(4) HS HSPLL(4) SOSC See parameter OS10 for FOSC value EC EC OS20 TOSC TOSC = 1/FOSC = TCY(2) OS30 OS31 Note 1: 2: TosL, TosH TosR, TosF External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time 0.45 x TOSC -- -- -- -- 0.05 x TOSC ns ns 3: 4: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/ or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. 20 MHz maximum for PIC32MX300 family devices. PLL input requirements: 4 MHZ <= FOSC <= 5 MHZ (use PLL prescaler to reduce FOSC). DS61143A -page 512 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V) AC CHARACTERISTICS Param No. OS50 Symbol FPLLI Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic(1) PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Min 4 Typ(2) -- Max 5 Units MHz Conditions ECPLL, HSPLL, MSPLL, FRCPLL modes OS51 OS52 OS53 FSYS TLOC DCLK 60 TBD TBD -- TBD +/-1 230 24 TBD MHz s % Measured over 100 ms period Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-18: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions AC CHARACTERISTICS Param No. F20 Note 1: FRC Characteristic Internal FRC Accuracy @ 8.00 MHz(1) -2 -5.0 -- -- +2 +5.0 % % +25C -40C TA +85C VDD = 3.0 to 3.6V VDD = 3.0 to 3.6V Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 29-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21 Characteristic Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions LPRC @ 31.25 kHz(1) TBD -15 -- -- TBD +15 % % +25C -40C TA +85C VDD = 2.5 to 3.6V VDD = 2.5 to 3.6V Legend: TBD = To Be Determined Note 1: Change of LPRC frequency as VDD changes. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 513 PIC32MX FAMILY FIGURE 29-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) DO31 DO32 Note: Refer to Figure 29-1 for load conditions. TABLE 29-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: 2: Symbol TIOR TIOF TINP TRBP Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time CNx High or Low Time (input) Min -- -- 10 2 Typ(1) 10 10 -- -- Max 20 20 -- -- Units ns ns ns TSYSCLK Conditions Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. DS61143A -page 514 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-4: RESETS TIMING CHARACTERISTICS VDD MCLR Internal POR PWRT Time-out OSC Time-out CPU Core Reset SY12 SY10 SY11 SY30 CPU starts fetching code after 8 SYSCLK cycle delay Note: Refer to Figure 29-1 for load conditions. TABLE 29-21: RESETS TIMING AC CHARACTERISTICS Param No. SY10 SY11 SY12 SY30 Note 1: 2: Symbol TMCL TPWRT TPOR TOST Characteristic(1) MCLR Pulse Width (low) Power-up Timer Period Power-on Reset Delay Oscillator Start-up Timer Period Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 2 48 1 -- Typ(2) -- 64 5 1024 TOSC Max -- 80 10 -- Units s ms s -- Conditions -40C to +85C -40C to +85C -40C to +85C TOSC = OSC1 period These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 515 PIC32MX FAMILY FIGURE 29-5: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 29-1 for load conditions. TABLE 29-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. TA10 Symbol TTXH Characteristic TxCK High Time Synchronous, with prescaler Asynchronous, with prescaler Asynchronous TA11 TTXL TxCK Low Time Synchronous, with prescaler Asynchronous, with prescaler Asynchronous TA15 TTXP TxCK Input Period Synchronous, with prescaler Asynchronous, with prescaler Asynchronous OS60 Ft1 SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) Delay from External TxCK Clock Edge to Timer Increment Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 10 10 10 10 10 10 Greater of: 10 ns or (2 * TPB + 10) Greater of: 10 ns or (2 * TPB + 10)/N 10 32 Typ -- -- -- -- -- -- -- Max Units -- -- -- -- -- -- -- ns ns ns ns ns ns ns Must also meet parameter TA15 Conditions Must also meet parameter TA15 -- -- -- N = prescale value (1, 8, 64, 256) -- -- -- 100 ns kHz TA20 Note 1: TCKEXTMRL -- 10 ns Timer1 is a Type A. DS61143A -page 516 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-23: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TB10 Symbol TtxH Characteristic TxCK High Synchronous, Time no prescaler Synchronous, with prescaler TB11 TtxL TxCK Low Synchronous, Time no prescaler Synchronous, with prescaler TB15 TtxP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min Greater of: 10 ns or (TPB + 5) 20 Greater of: 10 ns or (TPB + 5) 10 Greater of: 10 ns or (2 * TPB + 10) Greater of: 10 ns or (2*TPB + 10)/N -- -- 5 ns Typ -- Max -- Units ns Conditions Must also meet parameter TB15 -- -- -- -- ns ns Must also meet parameter TB15 -- -- -- -- ns ns N = prescale value (1, 2, 4, 8, 16, 32, 64, 256) (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 517 PIC32MX FAMILY FIGURE 29-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 29-1 for load conditions. IC11 TABLE 29-24: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. IC10 Symbol TccL Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic(1) ICx Input Low Time No prescaler Min Greater of: 10 ns or (TPB + 5) 10 Greater of: 20 ns or (TPB + 5) 10 Greater of: 10 ns or (2*TPB + 10)/N Max -- Units ns Conditions With prescaler IC11 TccH ICx Input High Time No prescaler -- -- ns ns With prescaler IC15 TccP ICx Input Period -- -- ns ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 29-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 29-1 for load conditions. DS61143A -page 518 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-25: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. OC10 OC11 Note 1: 2: TccF TccR Characteristic(1) OCx Output Fall Time OCx Output Rise Time Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- -- Typ(2) -- -- Max 10 10 Units ns ns Conditions These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx Note: Refer to Figure 29-1 for load conditions. TABLE 29-26: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OC15 OC20 Note 1: 2: Symbol TFD TFLT Characteristic(1) Fault Input to PWM I/O Change Fault Input Pulse Width Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- 50 Typ(2) -- -- Max 25 -- Units ns ns Conditions These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 519 PIC32MX FAMILY FIGURE 29-9: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SDOx Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL Characteristic(1) SCKx Output Low Time(3) SCKx Output High SCKx Output Fall Time(3) Time(4) (4) (4) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TSCK/2 TSCK/2 -- -- -- -- -- TBD TBD Typ(2) -- -- -- -- TBD TBD -- -- -- -- Max -- -- -- -- TBD TBD TBD Units ns ns ns ns ns ns ns ns ns Conditions SCKx Output Rise Time(4) SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS61143A -page 520 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP35 SP20 LSb SP21 SDOX MSb Bit 14 - - - - - -1 SP30,SP31 SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Symbol TscL TscH TscF TscR TdoF TdoR Characteristic(1) SCKx Output Low Time(3) SCKx Output High Time SCKx Output Rise Time (3) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TSCK/2 TSCK/2 -- -- (4) Typ(2) -- -- -- -- TBD TBD -- -- -- -- Max -- -- -- -- TBD TBD TBD -- -- -- Units ns ns ns ns ns ns ns ns ns ns Conditions SCKx Output Fall Time(4) (4) SDOx Data Output Fall Time SDOx Data Output Rise Time(4) -- -- -- TBD TBD TBD TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdoV2sc, SDOx Data Output Setup to TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 521 PIC32MX FAMILY FIGURE 29-11: SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX SP40 MSb In SP41 Bit 14 - - - -1 Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Symbol TscL TscH TscF TscR TdoF TdoR Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time (3) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TBD TSCK/2 -- -- (3) (3) Typ(2) -- -- TBD TBD TBD TBD -- -- -- -- -- -- Max -- -- TBD TBD TBD TBD TBD Units ns ns ns ns ns ns ns ns Conditions SCKx Input Rise Time(3) SDOx Data Output Fall Time SDOx Data Output Rise Time -- -- -- TBD TBD TBD TBD TBD TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge -- -- TBD -- ns ns ns ns -- TssL2scH, SSx to SCKx or SCKx Input TssL2scL TssH2doZ SSx to SDOx Output High-Impedance(3) TscH2ssH SSx after SCKx Edge TscL2ssH Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPIx pins. DS61143A -page 522 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-12: SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP52 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI SP40 MSb In SP41 Bit 14 - - - -1 LSb In SP72 LSb SP51 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 Note: Refer to Figure 29-1 for load conditions. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 523 PIC32MX FAMILY TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 SP60 Symbol TscL TscH TscF TscR TdoF TdoR Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time(3) SCKx Input Rise Time(3) SDOx Data Output Fall Time (3) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TBD TSCK/2 -- -- -- -- -- TBD TBD TBD TBD TBD -- Typ(2) -- -- TBD TBD TBD TBD -- -- -- -- -- -- -- -- -- TBD -- TBD Max -- -- TBD TBD TBD TBD TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions SDOx Data Output Rise Time(3) TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge TscH2diL, Hold Time of SDIx Data Input TscL2diL to SCKx Edge TssL2scH, SSx to SCKx or SCKx TssL2scL Input TssH2doZ SSx to SDOX Output High-Impedance(4) TscH2ssH SSx after SCKx Edge TscL2ssH TssL2doV SDOx Data Output Valid after SSx Edge Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS61143A -page 524 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 IM33 IM34 SDAx Start Condition Note: Refer to Figure 29-1 for load conditions. Stop Condition FIGURE 29-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-1 for load conditions. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 525 PIC32MX FAMILY TABLE 29-31: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol No. IM10 Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min(1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) TPB/2 (BRG + 1) -- -- -- 4.7 1.3 0.5 -- Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 350 -- -- -- 400 Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s pF -- -- -- Time the bus must be free before a new transmission can start -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- -- -- CB is specified to be from 10 to 400 pF Conditions -- -- -- -- -- -- CB is specified to be from 10 to 400 pF TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (2) IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (2) IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) IM21 TR:SCL IM25 TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time IM26 IM30 IM31 THD:STA Start Condition Hold Time IM33 TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time IM34 IM40 TAA:SCL Output Valid From Clock IM45 TBF:SDA Bus Free Time IM50 Note 1: 2: CB Bus Capacitive Loading BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS61143A -page 526 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Note: Refer to Figure 29-1 for load conditions. Stop Condition FIGURE 29-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-1 for load conditions. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 527 PIC32MX FAMILY TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param No. IS10 Symbol TLO:SCL Characteristic Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS20 TF:SCL SDAx and SCLx Fall Time SDAx and SCLx Rise Time Data Input Setup Time Data Input Hold Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS21 TR:SCL 100 kHz mode 400 kHz mode 1 MHz mode(1) IS25 TSU:DAT 100 kHz mode 400 kHz mode 1 MHz IS26 THD:DAT mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS30 TSU:STA 100 kHz mode 400 kHz mode 1 MHz mode(1) IS31 THD:STA 100 kHz mode 400 kHz mode 1 MHz mode(1) IS33 TSU:STO 100 kHz mode 400 kHz mode 1 MHz IS34 THD:STO mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS40 TAA:SCL Output Valid From 100 kHz mode Clock 400 kHz mode 1 MHz IS45 TBF:SDA Bus Free Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS50 Note 1: CB Bus Capacitive Loading Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4700 600 250 4000 600 250 4000 600 600 4000 600 250 0 0 0 4.7 1.3 0.5 -- 3500 1000 350 -- -- -- 400 Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- Units s s s s s s ns ns ns ns ns ns ns ns ns ns s s s s s s s s s s s ns ns ns ns ns ns s s s pF Time the bus must be free before a new transmission can start After this period, the first clock pulse is generated Only relevant for Repeated Start condition CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS61143A -page 528 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-33: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Symbol Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typ Max. Units Conditions Device Supply AVDD Module VDD Supply Greater of VDD - 0.3 or 2.5 VSS - 0.3 AVSS + 2.0 3.0 VREFL Reference Voltage Low AVSS 0 VREF IREF Absolute Reference Voltage AVss - 0.3 Current Drain -- Analog Input AD12 VINH-VINL Full-Scale Input Span VINL VIN Absolute VINL Input Voltage Absolute Input Voltage Leakage Current VREFL AVSS - 0.3 AVSS - 0.3 -- +/- 0.001 -- VREFH AVDD/2 AVDD + 0.3 +/-0.610 V V V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10K -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 AVDD - 2.0 0 AVss + 0.3 300 3 V AD02 AD05 AD05a AD06 AD06a AD07 AD08 AVSS VREFH Module VSS Supply Reference Voltage High -- -- -- -- -- -- 200 -- V V V V V V A A ADC operating ADC off See Note 1 VREFH = AVDD, VREFL = AVSS = 0 See Note 1 VREFH = AVDD, VREFL = AVSS = 0 Reference Inputs AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity -- -- 10K ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr AD21c INL 10 data bits -- -- <+/-1 bits LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V VINL = AVSS = 0V, AVDD = 3.3V Guaranteed AD22c DNL Differential Nonlinearity -- -- <+/-1 LSb AD23c GERR Gain Error -- -- <+/-2 LSb AD24n EOFF AD25c -- Offset Error Monotonicity -- -- -- -- <+/-2 -- LSb -- Legend: TBD = To Be Determined Note 1: These parameters are not characterized or tested in manufacturing. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 529 PIC32MX FAMILY TABLE 29-33: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typ Max. Units Conditions ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr AD21d INL AD22d DNL AD23d GERR AD24d EOFF AD25d -- Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity -- -- -- -- -- 10 data bits -- -- -- -- -- <+/-1 <+/-1 <+/-4 <+/-2 -- bits LSb LSb LSb LSb -- VINL = AVSS = 0V, AVDD = 3.6V VINL = AVSS = 0V, AVDD = 3.6V VINL = AVSS = 0V, AVDD = 3.6V VINL = AVSS = 0V, AVDD = 3.6V Guaranteed Legend: TBD = To Be Determined Note 1: These parameters are not characterized or tested in manufacturing. TABLE 29-34: A/D CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param No. AD50 AD51 AD55 AD56 AD57 Symbol Characteristic Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min. Typ(1) Max. Units Conditions Clock Parameters TAD tRC tCONV FCNV TSAMP A/D Clock Period(2) 75 -- -- -- -- -- TBD 12 TAD -- 1 TAD -- -- -- 1.1 -- ns ns -- MSPS -- TPB = 75 ns, AVDD = 3.0V -- -- -- -- A/D Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Conversion Rate Timing Parameters AD60 tPCS Conversion Start from Sample Trigger(3) Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1)(3) -- 1.0 TAD -- -- Auto-Convert Trigger (SSRC<2:0> = 111) not selected -- -- AD61 AD62 tPSS tCSS 0.5 TAD -- -- 0.5 TAD 1.5 TAD -- -- -- Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. DS61143A -page 530 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY TABLE 29-34: A/D CONVERSION TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS AD63 tDPU Time to Stabilize Analog Stage from A/D OFF to A/D ON(3) Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C -- -- 2 s -- Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 531 PIC32MX FAMILY FIGURE 29-17: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 Clear SAMP 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in in the "PIC32MX Family Reference Manual" (DS61132). 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS61143A -page 532 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY FIGURE 29-18: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001 AD50 ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc Set ADON TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 TSAMP TCONV 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Convert bit 9. 4 - Convert bit 8. 5 - Convert bit 0. 6 - One TAD for end of conversion. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>. (c) 2007 Microchip Technology Inc. Advance Information DS61143A -page 533 PIC32MX FAMILY FIGURE 29-19: EJTAG TIMING CHARACTERISTICS TABLE 29-35: EJTAG TIMING REQUIREMENTS Symbol Ttckcyc Ttckhigh Ttcklow Ttsetup Tthold Ttdoout Ttdozstate Ttrst*low Trf Description TCK Cycle Time TCK High Time TCK Low Time TAP Signals Setup Time Before Rising TCK TAP Signals Hold Time After Rising TCK TDO Output Delay Time From Falling TCK TDO 3-State Delay Time From Falling TCK TRST* Low Time TAP Signals Rise/Fall Time, All Input and Output Min 25 10 10 5 3 -- -- 25 -- Max -- -- -- -- -- 5 5 -- -- Units ns ns ns ns ns ns ns ns ns DS61143A -page 534 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY 30.0 30.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX300 F032H-I/ PT e3 0510017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC32MX360 F256L-I/PT e3 0510017 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 535 PIC32MX FAMILY 30.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 [[ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 L A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 0,1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS61143A-page 536 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 [[ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 537 PIC32MX FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 [[ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E E1 b N 1 23 NOTE 2 A L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 0,1 NOTE 1 c A1 L1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; A2 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS61143A-page 538 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 [[ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 539 PIC32MX FAMILY NOTES: DS61143A-page 540 Advance Information (c) 2007 Microchip Technology Inc. PIC32MX FAMILY Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 512 H T - I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Flash Memory Family Architecture Product Groups Flash Memory Family MX = 32-bit RISC MCU core 3xx = General purpose microcontroller family F = Flash program memory = 32K = 64K = 128K = 256K = 512K e) Examples: d) PIC32MX300F032H-I/PT: General purpose PIC32MX, 32 KB program memory, 64-pin, Industrial temp., TQFP package. PIC32MX360F256L-I/PT: General purpose PIC32MX, 256 KB program memory, 100-pin, Industrial temp., TQFP package Program Memory Size 32 64 128 256 512 Pin Count H = 64-pin L = 100-pin I PT PF = -40C to +85C (Industrial) = 64-Lead, 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample (c) 2007 Microchip Technology Inc. Advance Information DS61143A-page 541 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/05/07 DS61143A-page 542 Advance Information (c) 2007 Microchip Technology Inc. |
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